1 /* 2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __PLATFORM_DEF_H__ 8 #define __PLATFORM_DEF_H__ 9 10 #include <arch.h> 11 #include "../hikey_def.h" 12 13 /* Special value used to verify platform parameters from BL2 to BL3-1 */ 14 #define HIKEY_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL 15 16 /* 17 * Generic platform constants 18 */ 19 20 /* Size of cacheable stacks */ 21 #define PLATFORM_STACK_SIZE 0x800 22 23 #define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" 24 25 #define PLATFORM_CACHE_LINE_SIZE 64 26 #define PLATFORM_CLUSTER_COUNT 2 27 #define PLATFORM_CORE_COUNT_PER_CLUSTER 4 28 #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * \ 29 PLATFORM_CORE_COUNT_PER_CLUSTER) 30 #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2 31 #define PLAT_NUM_PWR_DOMAINS (PLATFORM_CORE_COUNT + \ 32 PLATFORM_CLUSTER_COUNT + 1) 33 34 #define PLAT_MAX_RET_STATE 1 35 #define PLAT_MAX_OFF_STATE 2 36 37 #define MAX_IO_DEVICES 3 38 #define MAX_IO_HANDLES 4 39 /* eMMC RPMB and eMMC User Data */ 40 #define MAX_IO_BLOCK_DEVICES 2 41 42 /* GIC related constants (no GICR in GIC-400) */ 43 #define PLAT_ARM_GICD_BASE 0xF6801000 44 #define PLAT_ARM_GICC_BASE 0xF6802000 45 #define PLAT_ARM_GICH_BASE 0xF6804000 46 #define PLAT_ARM_GICV_BASE 0xF6806000 47 48 49 /* 50 * Platform memory map related constants 51 */ 52 53 /* 54 * BL1 is stored in XG2RAM0_HIRQ that is 784KB large (0xF980_0000~0xF98C_4000). 55 */ 56 #define ONCHIPROM_PARAM_BASE (XG2RAM0_BASE + 0x700) 57 #define LOADER_RAM_BASE (XG2RAM0_BASE + 0x800) 58 #define BL1_XG2RAM0_OFFSET 0x1000 59 60 /* 61 * BL1 specific defines. 62 * 63 * Both loader and BL1_RO region stay in SRAM since they are used to simulate 64 * ROM. 65 * Loader is used to switch Hi6220 SoC from 32-bit to 64-bit mode. 66 * 67 * ++++++++++ 0xF980_0000 68 * + loader + 69 * ++++++++++ 0xF980_1000 70 * + BL1_RO + 71 * ++++++++++ 0xF981_0000 72 * + BL1_RW + 73 * ++++++++++ 0xF989_8000 74 */ 75 #define BL1_RO_BASE (XG2RAM0_BASE + BL1_XG2RAM0_OFFSET) 76 #define BL1_RO_LIMIT (XG2RAM0_BASE + 0x10000) 77 #define BL1_RW_BASE (BL1_RO_LIMIT) /* 0xf981_0000 */ 78 #define BL1_RW_SIZE (0x00088000) 79 #define BL1_RW_LIMIT (0xF9898000) 80 81 /* 82 * BL2 specific defines. 83 */ 84 #define BL2_BASE (BL1_RW_BASE + 0x8000) /* 0xf981_8000 */ 85 #define BL2_LIMIT (BL2_BASE + 0x40000) 86 87 /* 88 * SCP_BL2 specific defines. 89 * In HiKey, SCP_BL2 means MCU firmware. It's loaded into the temporary buffer 90 * at 0x0100_0000. Then BL2 will parse the sections and loaded them into 91 * predefined separated buffers. 92 */ 93 #define SCP_BL2_BASE (DDR_BASE + 0x01000000) 94 #define SCP_BL2_LIMIT (SCP_BL2_BASE + 0x00100000) 95 #define SCP_BL2_SIZE (SCP_BL2_LIMIT - SCP_BL2_BASE) 96 97 /* 98 * BL31 specific defines. 99 */ 100 #define BL31_BASE BL2_LIMIT /* 0xf985_8000 */ 101 #define BL31_LIMIT 0xF9898000 102 103 /* 104 * BL3-2 specific defines. 105 */ 106 107 /* 108 * The TSP currently executes from TZC secured area of DRAM or SRAM. 109 */ 110 #define BL32_SRAM_BASE BL31_LIMIT 111 #define BL32_SRAM_LIMIT (BL31_LIMIT+0x80000) /* 512K */ 112 113 #define BL32_DRAM_BASE DDR_SEC_BASE 114 #define BL32_DRAM_LIMIT (DDR_SEC_BASE+DDR_SEC_SIZE) 115 116 #if LOAD_IMAGE_V2 117 #ifdef SPD_opteed 118 /* Load pageable part of OP-TEE at end of allocated DRAM space for BL32 */ 119 #define HIKEY_OPTEE_PAGEABLE_LOAD_BASE (BL32_DRAM_LIMIT - HIKEY_OPTEE_PAGEABLE_LOAD_SIZE) /* 0x3FC0_0000 */ 120 #define HIKEY_OPTEE_PAGEABLE_LOAD_SIZE 0x400000 /* 4MB */ 121 #endif 122 #endif 123 124 #if (HIKEY_TSP_RAM_LOCATION_ID == HIKEY_DRAM_ID) 125 #define TSP_SEC_MEM_BASE BL32_DRAM_BASE 126 #define TSP_SEC_MEM_SIZE (BL32_DRAM_LIMIT - BL32_DRAM_BASE) 127 #define BL32_BASE BL32_DRAM_BASE 128 #define BL32_LIMIT BL32_DRAM_LIMIT 129 #elif (HIKEY_TSP_RAM_LOCATION_ID == HIKEY_SRAM_ID) 130 #define TSP_SEC_MEM_BASE BL32_SRAM_BASE 131 #define TSP_SEC_MEM_SIZE (BL32_SRAM_LIMIT - BL32_SRAM_BASE) 132 #define BL32_BASE BL32_SRAM_BASE 133 #define BL32_LIMIT BL32_SRAM_LIMIT 134 #else 135 #error "Currently unsupported HIKEY_TSP_LOCATION_ID value" 136 #endif 137 138 /* BL32 is mandatory in AArch32 */ 139 #ifndef AARCH32 140 #ifdef SPD_none 141 #undef BL32_BASE 142 #endif /* SPD_none */ 143 #endif 144 145 #define NS_BL1U_BASE (BL2_BASE) 146 #define NS_BL1U_SIZE (0x00010000) 147 #define NS_BL1U_LIMIT (NS_BL1U_BASE + NS_BL1U_SIZE) 148 149 /* 150 * Platform specific page table and MMU setup constants 151 */ 152 #define ADDR_SPACE_SIZE (1ull << 32) 153 154 #if defined(IMAGE_BL1) || defined(IMAGE_BL32) 155 #define MAX_XLAT_TABLES 3 156 #endif 157 158 #ifdef IMAGE_BL31 159 #define MAX_XLAT_TABLES 4 160 #endif 161 162 #ifdef IMAGE_BL2 163 #if LOAD_IMAGE_V2 164 #ifdef SPD_opteed 165 #define MAX_XLAT_TABLES 4 166 #else 167 #define MAX_XLAT_TABLES 3 168 #endif 169 #else 170 #define MAX_XLAT_TABLES 3 171 #endif 172 #endif 173 174 #define MAX_MMAP_REGIONS 16 175 176 #define HIKEY_NS_IMAGE_OFFSET (DDR_BASE + 0x35000000) 177 178 /* 179 * Declarations and constants to access the mailboxes safely. Each mailbox is 180 * aligned on the biggest cache line size in the platform. This is known only 181 * to the platform as it might have a combination of integrated and external 182 * caches. Such alignment ensures that two maiboxes do not sit on the same cache 183 * line at any cache level. They could belong to different cpus/clusters & 184 * get written while being protected by different locks causing corruption of 185 * a valid mailbox address. 186 */ 187 #define CACHE_WRITEBACK_SHIFT 6 188 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 189 190 #endif /* __PLATFORM_DEF_H__ */ 191
