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Searched
refs:BL1_RW_BASE
(Results
1 - 14
of
14
) sorted by null
/device/linaro/bootloader/arm-trusted-firmware/plat/arm/css/drivers/scp/
css_scp.h
43
CASSERT(SCP_BL2_LIMIT <=
BL1_RW_BASE
, assert_scp_bl2_limit_overwrite_bl1);
44
CASSERT(SCP_BL2U_LIMIT <=
BL1_RW_BASE
, assert_scp_bl2u_limit_overwrite_bl1);
css_bom_bootloader.c
54
CASSERT(SCP_BL2_LIMIT <=
BL1_RW_BASE
, assert_scp_bl2_overwrite_bl1);
55
CASSERT(SCP_BL2U_LIMIT <=
BL1_RW_BASE
, assert_scp_bl2u_overwrite_bl1);
/device/linaro/bootloader/arm-trusted-firmware/plat/hisilicon/poplar/include/
poplar_layout.h
97
#define
BL1_RW_BASE
(LLOADER_TEXT_BASE + BL1_RW_OFFSET)
98
#define BL1_RW_LIMIT (
BL1_RW_BASE
+ BL1_RW_SIZE)
/device/linaro/bootloader/arm-trusted-firmware/plat/socionext/uniphier/include/
platform_def.h
38
#define
BL1_RW_BASE
((BL1_RW_LIMIT) - 0x00040000)
40
#define BL2_LIMIT (
BL1_RW_BASE
)
/device/linaro/bootloader/arm-trusted-firmware/bl1/
bl1.ld.S
15
RAM (rwx): ORIGIN =
BL1_RW_BASE
, LENGTH = BL1_RW_LIMIT -
BL1_RW_BASE
90
. =
BL1_RW_BASE
;
91
ASSERT(
BL1_RW_BASE
== ALIGN(4096),
92
"
BL1_RW_BASE
address is not aligned on a page boundary.")
bl1_main.c
54
assert(
BL1_RW_BASE
> bl1_mem_layout->total_base);
56
bl2_mem_layout->total_size =
BL1_RW_BASE
- bl1_mem_layout->total_base;
/device/linaro/bootloader/arm-trusted-firmware/include/plat/arm/css/common/
css_def.h
167
#define SCP_BL2_BASE (
BL1_RW_BASE
- PLAT_CSS_MAX_SCP_BL2_SIZE)
168
#define SCP_BL2_LIMIT
BL1_RW_BASE
170
#define SCP_BL2U_BASE (
BL1_RW_BASE
- PLAT_CSS_MAX_SCP_BL2U_SIZE)
171
#define SCP_BL2U_LIMIT
BL1_RW_BASE
/device/linaro/bootloader/arm-trusted-firmware/plat/hisilicon/hikey960/include/
platform_def.h
52
#define
BL1_RW_BASE
(BL1_RO_LIMIT) /* 1AC1_0000 */
59
#define BL2_BASE (
BL1_RW_BASE
+ 0x8000) /* 1AC1_8000 */
/device/linaro/bootloader/arm-trusted-firmware/plat/hisilicon/hikey/include/
platform_def.h
77
#define
BL1_RW_BASE
(BL1_RO_LIMIT) /* 0xf981_0000 */
84
#define BL2_BASE (
BL1_RW_BASE
+ 0x8000) /* 0xf981_8000 */
/device/linaro/bootloader/arm-trusted-firmware/plat/hisilicon/hikey960/aarch64/
hikey960_common.c
28
#define MAP_BL1_RW MAP_REGION_FLAT(
BL1_RW_BASE
, \
29
BL1_RW_LIMIT -
BL1_RW_BASE
, \
/device/linaro/bootloader/arm-trusted-firmware/include/plat/arm/common/
arm_def.h
321
#define
BL1_RW_BASE
(ARM_BL_RAM_BASE + \
335
#define BL2_BASE (
BL1_RW_BASE
- PLAT_ARM_MAX_BL2_SIZE)
336
#define BL2_LIMIT
BL1_RW_BASE
369
#define BL31_PROGBITS_LIMIT
BL1_RW_BASE
429
#define BL2U_LIMIT
BL1_RW_BASE
/device/linaro/bootloader/arm-trusted-firmware/plat/qemu/include/
platform_def.h
105
* Put BL1 RW at the top of the Secure SRAM.
BL1_RW_BASE
is calculated using
110
#define
BL1_RW_BASE
(BL1_RW_LIMIT - 0x12000)
130
#define BL31_PROGBITS_LIMIT
BL1_RW_BASE
/device/linaro/bootloader/arm-trusted-firmware/plat/hisilicon/hikey/
hikey_bl1_setup.c
94
bl1_tzram_layout.total_base =
BL1_RW_BASE
;
99
bl1_tzram_layout.free_base =
BL1_RW_BASE
;
/device/linaro/bootloader/arm-trusted-firmware/plat/hisilicon/hikey960/
hikey960_bl1_setup.c
118
bl1_tzram_layout.total_base =
BL1_RW_BASE
;
123
bl1_tzram_layout.free_base =
BL1_RW_BASE
;
Completed in 129 milliseconds