1 /* 2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __PLATFORM_DEF_H__ 8 #define __PLATFORM_DEF_H__ 9 10 #include <common_def.h> 11 #include <tbbr/tbbr_img_def.h> 12 13 #define PLATFORM_STACK_SIZE 0x1000 14 15 #define CACHE_WRITEBACK_SHIFT 6 16 #define CACHE_WRITEBACK_GRANULE (1 << (CACHE_WRITEBACK_SHIFT)) 17 18 /* topology */ 19 #define UNIPHIER_MAX_CPUS_PER_CLUSTER 4 20 #define UNIPHIER_CLUSTER_COUNT 2 21 22 #define PLATFORM_CORE_COUNT \ 23 ((UNIPHIER_MAX_CPUS_PER_CLUSTER) * (UNIPHIER_CLUSTER_COUNT)) 24 25 #define PLAT_MAX_PWR_LVL 1 26 27 #define PLAT_MAX_OFF_STATE 2 28 #define PLAT_MAX_RET_STATE 1 29 30 #define UNIPHIER_SEC_DRAM_BASE 0x81000000 31 #define UNIPHIER_SEC_DRAM_LIMIT 0x82000000 32 #define UNIPHIER_SEC_DRAM_SIZE ((UNIPHIER_SEC_DRAM_LIMIT) - \ 33 (UNIPHIER_SEC_DRAM_BASE)) 34 35 #define BL1_RO_BASE 0x80000000 36 #define BL1_RO_LIMIT 0x80018000 37 #define BL1_RW_LIMIT (UNIPHIER_SEC_DRAM_LIMIT) 38 #define BL1_RW_BASE ((BL1_RW_LIMIT) - 0x00040000) 39 40 #define BL2_LIMIT (BL1_RW_BASE) 41 #define BL2_BASE ((BL2_LIMIT) - 0x00040000) 42 43 #define BL31_BASE (UNIPHIER_SEC_DRAM_BASE) 44 #define BL31_LIMIT ((BL31_BASE) + 0x00080000) 45 46 #define BL32_BASE (BL31_LIMIT) 47 #define BL32_LIMIT (UNIPHIER_SEC_DRAM_LIMIT) 48 49 #define UNIPHIER_BLOCK_BUF_SIZE 0x00400000 50 #define UNIPHIER_BLOCK_BUF_BASE ((BL2_LIMIT) - \ 51 (UNIPHIER_BLOCK_BUF_SIZE)) 52 53 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 54 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 55 56 #define PLAT_XLAT_TABLES_DYNAMIC 1 57 #define MAX_XLAT_TABLES 7 58 #define MAX_MMAP_REGIONS 6 59 60 #define MAX_IO_HANDLES 2 61 #define MAX_IO_DEVICES 2 62 #define MAX_IO_BLOCK_DEVICES 1 63 64 #define TSP_SEC_MEM_BASE (BL32_BASE) 65 #define TSP_SEC_MEM_SIZE ((BL32_LIMIT) - (BL32_BASE)) 66 #define TSP_PROGBITS_LIMIT (UNIPHIER_BLOCK_BUF_BASE) 67 #define TSP_IRQ_SEC_PHY_TIMER 29 68 69 #endif /* __PLATFORM_DEF_H__ */ 70
