| /external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| HexagonMCELFStreamer.h | 22 std::unique_ptr<MCInstrInfo> MCII;
28 MCII(createHexagonMCInstrInfo()) {}
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| HexagonMCCodeEmitter.h | 30 MCInstrInfo const &MCII;
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| HexagonAsmBackend.cpp | 45 std::unique_ptr <MCInstrInfo> MCII;
63 OSABI(OSABI), MCII (T.createMCInstrInfo()), RelaxTarget(new MCInst *),
523 const MCInstrDesc &MCID = HexagonMCInstrInfo::getDesc(*MCII, HMI);
526 if (llvm::HexagonMCInstrInfo::getType(*MCII, HMI) == HexagonII::TypeJ ||
527 (llvm::HexagonMCInstrInfo::getType(*MCII, HMI) ==
530 (llvm::HexagonMCInstrInfo::getType(*MCII, HMI) == HexagonII::TypeNV &&
532 (llvm::HexagonMCInstrInfo::getType(*MCII, HMI) == HexagonII::TypeCR &&
534 if (HexagonMCInstrInfo::isExtendable(*MCII, HMI)) {
537 HMI.getOperand(HexagonMCInstrInfo::getExtendableOp(*MCII, HMI));
656 *MCII, CrntHMI
[all...] |
| HexagonMCChecker.h | 77 MCInstrInfo const &MCII;
196 explicit HexagonMCChecker(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCInst& mcb, MCInst &mcbdx,
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| HexagonShuffler.h | 85 HexagonCVIResource(TypeUnitsAndLanes *TUL, MCInstrInfo const &MCII,
107 MCInstrInfo const &MCII, MCInst const *id,
109 : ID(id), Extender(Extender), Core(s), CVI(T, MCII, s, id),
147 MCInstrInfo const &MCII;
166 explicit HexagonShuffler(MCInstrInfo const &MCII, MCSubtargetInfo const &STI);
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| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| MipsMCCodeEmitter.h | 36 const MCInstrInfo &MCII;
44 MipsMCCodeEmitter(const MCInstrInfo &mcii, MCContext &Ctx_, bool IsLittle)
45 : MCII(mcii), Ctx(Ctx_), IsLittleEndian(IsLittle) {}
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| /external/llvm/lib/Target/WebAssembly/MCTargetDesc/ |
| WebAssemblyMCCodeEmitter.cpp | 36 const MCInstrInfo &MCII;
48 WebAssemblyMCCodeEmitter(const MCInstrInfo &mcii) : MCII(mcii) {}
52 MCCodeEmitter *llvm::createWebAssemblyMCCodeEmitter(const MCInstrInfo &MCII) {
53 return new WebAssemblyMCCodeEmitter(MCII);
63 const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
78 (1 + MCII.get(MI.getOpcode()).isVariadic() + i) * sizeof(uint64_t),
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| /external/swiftshader/third_party/LLVM/lib/Target/Mips/MCTargetDesc/ |
| MipsMCCodeEmitter.cpp | 32 const MCInstrInfo &MCII;
36 MipsMCCodeEmitter(const MCInstrInfo &mcii, const MCSubtargetInfo &sti,
38 : MCII(mcii), STI(sti) {}
48 MCCodeEmitter *llvm::createMipsMCCodeEmitter(const MCInstrInfo &MCII,
51 return new MipsMCCodeEmitter(MCII, STI, Ctx);
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| /external/llvm/lib/Target/WebAssembly/Disassembler/ |
| WebAssemblyDisassembler.cpp | 34 std::unique_ptr<const MCInstrInfo> MCII;
43 std::unique_ptr<const MCInstrInfo> MCII)
44 : MCDisassembler(STI, Ctx), MCII(std::move(MCII)) {}
51 std::unique_ptr<const MCInstrInfo> MCII(T.createMCInstrInfo());
52 return new WebAssemblyDisassembler(STI, Ctx, std::move(MCII));
79 const MCInstrDesc &Desc = MCII->get(Opcode);
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| /external/llvm/lib/Target/AMDGPU/MCTargetDesc/ |
| SIMCCodeEmitter.cpp | 37 const MCInstrInfo &MCII;
47 SIMCCodeEmitter(const MCInstrInfo &mcii, const MCRegisterInfo &mri,
49 : MCII(mcii), MRI(mri) { }
72 MCCodeEmitter *llvm::createSIMCCodeEmitter(const MCInstrInfo &MCII,
75 return new SIMCCodeEmitter(MCII, MRI, Ctx);
196 const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
281 const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
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| R600MCCodeEmitter.cpp | 37 const MCInstrInfo &MCII;
41 R600MCCodeEmitter(const MCInstrInfo &mcii, const MCRegisterInfo &mri)
42 : MCII(mcii), MRI(mri) { }
80 MCCodeEmitter *llvm::createR600MCCodeEmitter(const MCInstrInfo &MCII,
83 return new R600MCCodeEmitter(MCII, MRI);
89 const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
160 if (HAS_NATIVE_OPERANDS(MCII.get(MI.getOpcode()).TSFlags))
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| /external/swiftshader/third_party/LLVM/lib/Target/MBlaze/MCTargetDesc/ |
| MBlazeMCCodeEmitter.cpp | 34 const MCInstrInfo &MCII;
37 MBlazeMCCodeEmitter(const MCInstrInfo &mcii, const MCSubtargetInfo &sti,
39 : MCII(mcii) {
100 MCCodeEmitter *llvm::createMBlazeMCCodeEmitter(const MCInstrInfo &MCII,
103 return new MBlazeMCCodeEmitter(MCII, STI, Ctx);
183 const MCInstrDesc &Desc = MCII.get(Opcode);
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| /external/llvm/lib/Target/PowerPC/MCTargetDesc/ |
| PPCMCCodeEmitter.cpp | 40 const MCInstrInfo &MCII;
45 PPCMCCodeEmitter(const MCInstrInfo &mcii, MCContext &ctx)
46 : MCII(mcii), CTX(ctx),
109 const MCInstrDesc &Desc = MCII.get(Opcode);
146 MCCodeEmitter *llvm::createPPCMCCodeEmitter(const MCInstrInfo &MCII,
149 return new PPCMCCodeEmitter(MCII, Ctx);
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| /external/llvm/lib/Target/SystemZ/MCTargetDesc/ |
| SystemZMCCodeEmitter.cpp | 29 const MCInstrInfo &MCII;
33 SystemZMCCodeEmitter(const MCInstrInfo &mcii, MCContext &ctx)
34 : MCII(mcii), Ctx(ctx) {
116 MCCodeEmitter *llvm::createSystemZMCCodeEmitter(const MCInstrInfo &MCII,
119 return new SystemZMCCodeEmitter(MCII, Ctx);
127 unsigned Size = MCII.get(MI.getOpcode()).getSize();
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| /external/llvm/lib/Target/Hexagon/ |
| HexagonAsmPrinter.cpp | 59 void HexagonLowerToMC(const MCInstrInfo &MCII, const MachineInstr *MI,
587 const MCInstrInfo &MCII = *Subtarget->getInstrInfo();
599 HexagonLowerToMC(MCII, &*MII, MCB, *this);
602 HexagonLowerToMC(MCII, MI, MCB, *this);
605 MCII, *Subtarget, OutStreamer->getContext(), MCB, nullptr);
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| /external/swiftshader/third_party/LLVM/lib/Target/X86/MCTargetDesc/ |
| X86MCCodeEmitter.cpp | 33 const MCInstrInfo &MCII;
37 X86MCCodeEmitter(const MCInstrInfo &mcii, const MCSubtargetInfo &sti,
39 : MCII(mcii), STI(sti), Ctx(ctx) {
137 MCCodeEmitter *llvm::createX86MCCodeEmitter(const MCInstrInfo &MCII,
140 return new X86MCCodeEmitter(MCII, STI, Ctx);
841 const MCInstrDesc &Desc = MCII.get(Opcode);
[all...] |
| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| ARMMCCodeEmitter.cpp | 42 const MCInstrInfo &MCII;
47 ARMMCCodeEmitter(const MCInstrInfo &mcii, MCContext &ctx, bool IsLittle)
48 : MCII(mcii), CTX(ctx), IsLittleEndian(IsLittle) {
435 MCCodeEmitter *llvm::createARMLEMCCodeEmitter(const MCInstrInfo &MCII,
438 return new ARMMCCodeEmitter(MCII, Ctx, true);
441 MCCodeEmitter *llvm::createARMBEMCCodeEmitter(const MCInstrInfo &MCII,
444 return new ARMMCCodeEmitter(MCII, Ctx, false);
[all...] |
| /external/llvm/lib/Target/X86/MCTargetDesc/ |
| X86MCCodeEmitter.cpp | 35 const MCInstrInfo &MCII;
38 X86MCCodeEmitter(const MCInstrInfo &mcii, MCContext &ctx)
39 : MCII(mcii), Ctx(ctx) {
151 MCCodeEmitter *llvm::createX86MCCodeEmitter(const MCInstrInfo &MCII,
154 return new X86MCCodeEmitter(MCII, Ctx);
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/MCTargetDesc/ |
| ARMMCCodeEmitter.cpp | 39 const MCInstrInfo &MCII;
43 ARMMCCodeEmitter(const MCInstrInfo &mcii, const MCSubtargetInfo &sti,
45 : MCII(mcii), STI(sti) {
337 MCCodeEmitter *llvm::createARMMCCodeEmitter(const MCInstrInfo &MCII,
340 return new ARMMCCodeEmitter(MCII, STI, Ctx);
[all...] |
| /external/llvm/lib/Target/Hexagon/Disassembler/ |
| HexagonDisassembler.cpp | 43 std::unique_ptr<MCInstrInfo const> const MCII;
46 MCInstrInfo const *MCII)
47 : MCDisassembler(STI, Ctx), MCII(MCII), CurrentBundle(new MCInst *) {}
176 HexagonMCChecker Checker (*MCII, STI, MI, MI, *getContext().getRegisterInfo());
332 if (llvm::HexagonMCInstrInfo::getType(*MCII, MI) ==
344 if (HexagonMCInstrInfo::isNewValue(*MCII, MI)) {
345 unsigned OpIndex = HexagonMCInstrInfo::getNewValueOp(*MCII, MI);
355 bool Vector = HexagonMCInstrInfo::isVector(*MCII, MI);
362 if (Vector && !HexagonMCInstrInfo::isVector(*MCII, *i->getInst())
[all...] |
| /external/llvm/lib/Target/Hexagon/AsmParser/ |
| HexagonAsmParser.cpp | 81 MCInstrInfo const &MCII;
141 MCII (MII), MCB(HexagonMCInstrInfo::createBundle()), InBrackets(false) {
627 HexagonMCChecker Check(MCII, getSTI(), MCB, MCB, *RI);
629 bool CheckOk = HexagonMCInstrInfo::canonicalizePacket(MCII, getSTI(),
854 getParser().getContext(), MCII, MCB, *SubInst);
[all...] |
