1 //===-- MipsMCCodeEmitter.h - Convert Mips Code to Machine Code -----------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines the MipsMCCodeEmitter class. 11 // 12 //===----------------------------------------------------------------------===// 13 // 14 15 #ifndef LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSMCCODEEMITTER_H 16 #define LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSMCCODEEMITTER_H 17 18 #include "llvm/MC/MCCodeEmitter.h" 19 #include "llvm/Support/DataTypes.h" 20 21 using namespace llvm; 22 23 namespace llvm { 24 class MCContext; 25 class MCExpr; 26 class MCInst; 27 class MCInstrInfo; 28 class MCFixup; 29 class MCOperand; 30 class MCSubtargetInfo; 31 class raw_ostream; 32 33 class MipsMCCodeEmitter : public MCCodeEmitter { 34 MipsMCCodeEmitter(const MipsMCCodeEmitter &) = delete; 35 void operator=(const MipsMCCodeEmitter &) = delete; 36 const MCInstrInfo &MCII; 37 MCContext &Ctx; 38 bool IsLittleEndian; 39 40 bool isMicroMips(const MCSubtargetInfo &STI) const; 41 bool isMips32r6(const MCSubtargetInfo &STI) const; 42 43 public: 44 MipsMCCodeEmitter(const MCInstrInfo &mcii, MCContext &Ctx_, bool IsLittle) 45 : MCII(mcii), Ctx(Ctx_), IsLittleEndian(IsLittle) {} 46 47 ~MipsMCCodeEmitter() override {} 48 49 void EmitByte(unsigned char C, raw_ostream &OS) const; 50 51 void EmitInstruction(uint64_t Val, unsigned Size, const MCSubtargetInfo &STI, 52 raw_ostream &OS) const; 53 54 void encodeInstruction(const MCInst &MI, raw_ostream &OS, 55 SmallVectorImpl<MCFixup> &Fixups, 56 const MCSubtargetInfo &STI) const override; 57 58 // getBinaryCodeForInstr - TableGen'erated function for getting the 59 // binary encoding for an instruction. 60 uint64_t getBinaryCodeForInstr(const MCInst &MI, 61 SmallVectorImpl<MCFixup> &Fixups, 62 const MCSubtargetInfo &STI) const; 63 64 // getJumpTargetOpValue - Return binary encoding of the jump 65 // target operand. If the machine operand requires relocation, 66 // record the relocation and return zero. 67 unsigned getJumpTargetOpValue(const MCInst &MI, unsigned OpNo, 68 SmallVectorImpl<MCFixup> &Fixups, 69 const MCSubtargetInfo &STI) const; 70 71 // getBranchJumpOpValueMM - Return binary encoding of the microMIPS jump 72 // target operand. If the machine operand requires relocation, 73 // record the relocation and return zero. 74 unsigned getJumpTargetOpValueMM(const MCInst &MI, unsigned OpNo, 75 SmallVectorImpl<MCFixup> &Fixups, 76 const MCSubtargetInfo &STI) const; 77 78 // getUImm5Lsl2Encoding - Return binary encoding of the microMIPS jump 79 // target operand. 80 unsigned getUImm5Lsl2Encoding(const MCInst &MI, unsigned OpNo, 81 SmallVectorImpl<MCFixup> &Fixups, 82 const MCSubtargetInfo &STI) const; 83 84 unsigned getSImm3Lsa2Value(const MCInst &MI, unsigned OpNo, 85 SmallVectorImpl<MCFixup> &Fixups, 86 const MCSubtargetInfo &STI) const; 87 88 unsigned getUImm6Lsl2Encoding(const MCInst &MI, unsigned OpNo, 89 SmallVectorImpl<MCFixup> &Fixups, 90 const MCSubtargetInfo &STI) const; 91 92 // getSImm9AddiuspValue - Return binary encoding of the microMIPS addiusp 93 // instruction immediate operand. 94 unsigned getSImm9AddiuspValue(const MCInst &MI, unsigned OpNo, 95 SmallVectorImpl<MCFixup> &Fixups, 96 const MCSubtargetInfo &STI) const; 97 98 // getBranchTargetOpValue - Return binary encoding of the branch 99 // target operand. If the machine operand requires relocation, 100 // record the relocation and return zero. 101 unsigned getBranchTargetOpValue(const MCInst &MI, unsigned OpNo, 102 SmallVectorImpl<MCFixup> &Fixups, 103 const MCSubtargetInfo &STI) const; 104 105 // getBranchTargetOpValue1SImm16 - Return binary encoding of the branch 106 // target operand. If the machine operand requires relocation, 107 // record the relocation and return zero. 108 unsigned getBranchTargetOpValue1SImm16(const MCInst &MI, unsigned OpNo, 109 SmallVectorImpl<MCFixup> &Fixups, 110 const MCSubtargetInfo &STI) const; 111 112 // getBranchTargetOpValueMMR6 - Return binary encoding of the branch 113 // target operand. If the machine operand requires relocation, 114 // record the relocation and return zero. 115 unsigned getBranchTargetOpValueMMR6(const MCInst &MI, unsigned OpNo, 116 SmallVectorImpl<MCFixup> &Fixups, 117 const MCSubtargetInfo &STI) const; 118 119 // getBranchTarget7OpValue - Return binary encoding of the microMIPS branch 120 // target operand. If the machine operand requires relocation, 121 // record the relocation and return zero. 122 unsigned getBranchTarget7OpValueMM(const MCInst &MI, unsigned OpNo, 123 SmallVectorImpl<MCFixup> &Fixups, 124 const MCSubtargetInfo &STI) const; 125 126 // getBranchTargetOpValueMMPC10 - Return binary encoding of the microMIPS 127 // 10-bit branch target operand. If the machine operand requires relocation, 128 // record the relocation and return zero. 129 unsigned getBranchTargetOpValueMMPC10(const MCInst &MI, unsigned OpNo, 130 SmallVectorImpl<MCFixup> &Fixups, 131 const MCSubtargetInfo &STI) const; 132 133 // getBranchTargetOpValue - Return binary encoding of the microMIPS branch 134 // target operand. If the machine operand requires relocation, 135 // record the relocation and return zero. 136 unsigned getBranchTargetOpValueMM(const MCInst &MI, unsigned OpNo, 137 SmallVectorImpl<MCFixup> &Fixups, 138 const MCSubtargetInfo &STI) const; 139 140 // getBranchTarget21OpValue - Return binary encoding of the branch 141 // offset operand. If the machine operand requires relocation, 142 // record the relocation and return zero. 143 unsigned getBranchTarget21OpValue(const MCInst &MI, unsigned OpNo, 144 SmallVectorImpl<MCFixup> &Fixups, 145 const MCSubtargetInfo &STI) const; 146 147 // getBranchTarget21OpValueMM - Return binary encoding of the branch 148 // offset operand for microMIPS. If the machine operand requires 149 // relocation,record the relocation and return zero. 150 unsigned getBranchTarget21OpValueMM(const MCInst &MI, unsigned OpNo, 151 SmallVectorImpl<MCFixup> &Fixups, 152 const MCSubtargetInfo &STI) const; 153 154 // getBranchTarget26OpValue - Return binary encoding of the branch 155 // offset operand. If the machine operand requires relocation, 156 // record the relocation and return zero. 157 unsigned getBranchTarget26OpValue(const MCInst &MI, unsigned OpNo, 158 SmallVectorImpl<MCFixup> &Fixups, 159 const MCSubtargetInfo &STI) const; 160 161 // getBranchTarget26OpValueMM - Return binary encoding of the branch 162 // offset operand. If the machine operand requires relocation, 163 // record the relocation and return zero. 164 unsigned getBranchTarget26OpValueMM(const MCInst &MI, unsigned OpNo, 165 SmallVectorImpl<MCFixup> &Fixups, 166 const MCSubtargetInfo &STI) const; 167 168 // getJumpOffset16OpValue - Return binary encoding of the jump 169 // offset operand. If the machine operand requires relocation, 170 // record the relocation and return zero. 171 unsigned getJumpOffset16OpValue(const MCInst &MI, unsigned OpNo, 172 SmallVectorImpl<MCFixup> &Fixups, 173 const MCSubtargetInfo &STI) const; 174 175 // getMachineOpValue - Return binary encoding of operand. If the machin 176 // operand requires relocation, record the relocation and return zero. 177 unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO, 178 SmallVectorImpl<MCFixup> &Fixups, 179 const MCSubtargetInfo &STI) const; 180 181 unsigned getMSAMemEncoding(const MCInst &MI, unsigned OpNo, 182 SmallVectorImpl<MCFixup> &Fixups, 183 const MCSubtargetInfo &STI) const; 184 185 template <unsigned ShiftAmount = 0> 186 unsigned getMemEncoding(const MCInst &MI, unsigned OpNo, 187 SmallVectorImpl<MCFixup> &Fixups, 188 const MCSubtargetInfo &STI) const; 189 unsigned getMemEncodingMMImm4(const MCInst &MI, unsigned OpNo, 190 SmallVectorImpl<MCFixup> &Fixups, 191 const MCSubtargetInfo &STI) const; 192 unsigned getMemEncodingMMImm4Lsl1(const MCInst &MI, unsigned OpNo, 193 SmallVectorImpl<MCFixup> &Fixups, 194 const MCSubtargetInfo &STI) const; 195 unsigned getMemEncodingMMImm4Lsl2(const MCInst &MI, unsigned OpNo, 196 SmallVectorImpl<MCFixup> &Fixups, 197 const MCSubtargetInfo &STI) const; 198 unsigned getMemEncodingMMSPImm5Lsl2(const MCInst &MI, unsigned OpNo, 199 SmallVectorImpl<MCFixup> &Fixups, 200 const MCSubtargetInfo &STI) const; 201 unsigned getMemEncodingMMGPImm7Lsl2(const MCInst &MI, unsigned OpNo, 202 SmallVectorImpl<MCFixup> &Fixups, 203 const MCSubtargetInfo &STI) const; 204 unsigned getMemEncodingMMImm9(const MCInst &MI, unsigned OpNo, 205 SmallVectorImpl<MCFixup> &Fixups, 206 const MCSubtargetInfo &STI) const; 207 unsigned getMemEncodingMMImm11(const MCInst &MI, unsigned OpNo, 208 SmallVectorImpl<MCFixup> &Fixups, 209 const MCSubtargetInfo &STI) const; 210 unsigned getMemEncodingMMImm12(const MCInst &MI, unsigned OpNo, 211 SmallVectorImpl<MCFixup> &Fixups, 212 const MCSubtargetInfo &STI) const; 213 unsigned getMemEncodingMMImm16(const MCInst &MI, unsigned OpNo, 214 SmallVectorImpl<MCFixup> &Fixups, 215 const MCSubtargetInfo &STI) const; 216 unsigned getMemEncodingMMImm4sp(const MCInst &MI, unsigned OpNo, 217 SmallVectorImpl<MCFixup> &Fixups, 218 const MCSubtargetInfo &STI) const; 219 unsigned getSizeInsEncoding(const MCInst &MI, unsigned OpNo, 220 SmallVectorImpl<MCFixup> &Fixups, 221 const MCSubtargetInfo &STI) const; 222 223 /// Subtract Offset then encode as a N-bit unsigned integer. 224 template <unsigned Bits, int Offset> 225 unsigned getUImmWithOffsetEncoding(const MCInst &MI, unsigned OpNo, 226 SmallVectorImpl<MCFixup> &Fixups, 227 const MCSubtargetInfo &STI) const; 228 229 unsigned getSimm19Lsl2Encoding(const MCInst &MI, unsigned OpNo, 230 SmallVectorImpl<MCFixup> &Fixups, 231 const MCSubtargetInfo &STI) const; 232 233 unsigned getSimm18Lsl3Encoding(const MCInst &MI, unsigned OpNo, 234 SmallVectorImpl<MCFixup> &Fixups, 235 const MCSubtargetInfo &STI) const; 236 237 unsigned getUImm3Mod8Encoding(const MCInst &MI, unsigned OpNo, 238 SmallVectorImpl<MCFixup> &Fixups, 239 const MCSubtargetInfo &STI) const; 240 unsigned getUImm4AndValue(const MCInst &MI, unsigned OpNo, 241 SmallVectorImpl<MCFixup> &Fixups, 242 const MCSubtargetInfo &STI) const; 243 244 unsigned getRegisterPairOpValue(const MCInst &MI, unsigned OpNo, 245 SmallVectorImpl<MCFixup> &Fixups, 246 const MCSubtargetInfo &STI) const; 247 248 unsigned getMovePRegPairOpValue(const MCInst &MI, unsigned OpNo, 249 SmallVectorImpl<MCFixup> &Fixups, 250 const MCSubtargetInfo &STI) const; 251 252 unsigned getSimm23Lsl2Encoding(const MCInst &MI, unsigned OpNo, 253 SmallVectorImpl<MCFixup> &Fixups, 254 const MCSubtargetInfo &STI) const; 255 256 unsigned getExprOpValue(const MCExpr *Expr, SmallVectorImpl<MCFixup> &Fixups, 257 const MCSubtargetInfo &STI) const; 258 259 unsigned getRegisterListOpValue(const MCInst &MI, unsigned OpNo, 260 SmallVectorImpl<MCFixup> &Fixups, 261 const MCSubtargetInfo &STI) const; 262 263 unsigned getRegisterListOpValue16(const MCInst &MI, unsigned OpNo, 264 SmallVectorImpl<MCFixup> &Fixups, 265 const MCSubtargetInfo &STI) const; 266 private: 267 void LowerCompactBranch(MCInst& Inst) const; 268 }; // class MipsMCCodeEmitter 269 } // namespace llvm. 270 271 #endif 272
