| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| RegisterClassInfo.cpp | 86 unsigned PhysReg = RawOrder[i];
88 if (Reserved.test(PhysReg))
90 if (CSRNum[PhysReg])
91 // PhysReg aliases a CSR, save it for later.
92 CSRAlias.push_back(PhysReg);
94 RCI.Order[N++] = PhysReg;
|
| VirtRegMap.cpp | 120 unsigned physReg = Hint.second;
121 if (TargetRegisterInfo::isVirtualRegister(physReg) && hasPhys(physReg))
122 physReg = getPhys(physReg);
124 return (TargetRegisterInfo::isPhysicalRegister(physReg))
125 ? physReg : 0;
126 return TRI->ResolveRegAllocHint(Hint.first, physReg, *MF);
282 unsigned PhysReg = getPhys(VirtReg);
283 assert(PhysReg != NO_PHYS_REG && "Instruction uses unmapped VirtReg")
[all...] |
| InterferenceCache.h | 37 /// of PhysReg in all basic blocks.
39 /// PhysReg - The register currently represented.
40 unsigned PhysReg;
59 /// PhysReg.
74 Entry() : PhysReg(0), Tag(0), RefCount(0), Indexes(0) {}
78 PhysReg = 0;
83 unsigned getPhysReg() const { return PhysReg; }
91 /// valid - Return true if this is a valid entry for physReg.
94 /// reset - Initialize entry to represent physReg's aliases.
95 void reset(unsigned physReg,
[all...] |
| RegAllocBasic.cpp | 189 for (unsigned PhysReg = 0; PhysReg < PhysReg2LiveUnion.numRegs(); ++PhysReg) {
190 DEBUG(PhysReg2LiveUnion[PhysReg].print(dbgs(), TRI));
191 LiveVirtRegBitSet &VRegs = unionVRegs[PhysReg];
192 PhysReg2LiveUnion[PhysReg].verify(VRegs);
205 unsigned PhysReg = VRM->getPhys(reg);
206 if (!unionVRegs[PhysReg].test(reg)) {
208 TRI->getName(PhysReg) << "\n";
276 void RegAllocBase::assign(LiveInterval &VirtReg, unsigned PhysReg) {
[all...] |
| RegAllocFast.cpp | 74 unsigned PhysReg; // Currently held here.
78 LiveReg(unsigned p=0) : LastUse(0), PhysReg(p), LastOpNum(0),
160 void definePhysReg(MachineInstr *MI, unsigned PhysReg, RegState NewState);
161 unsigned calcSpillCost(unsigned PhysReg) const;
162 void assignVirtToPhysReg(LiveRegEntry &LRE, unsigned PhysReg);
169 bool setPhysReg(MachineInstr *MI, unsigned OpNum, unsigned PhysReg);
216 if (MO.getReg() == LR.PhysReg)
219 LR.LastUse->addRegisterKilled(LR.PhysReg, TRI, true);
227 assert(PhysRegState[LR.PhysReg] == LRI->first && "Broken RegState mapping");
228 PhysRegState[LR.PhysReg] = regFree
[all...] |
| RegAllocGreedy.cpp | 184 unsigned PhysReg;
189 // Interference for PhysReg.
197 PhysReg = Reg;
217 /// Candidate info for for each PhysReg in AllocationOrder.
359 if (unsigned PhysReg = VRM->getPhys(VirtReg)) {
360 unassign(LIS->getInterval(VirtReg), PhysReg);
369 unsigned PhysReg = VRM->getPhys(VirtReg);
370 if (!PhysReg)
375 unassign(LI, PhysReg);
448 unsigned PhysReg;
[all...] |
| /external/llvm/lib/CodeGen/ |
| LiveRegMatrix.cpp | 75 unsigned PhysReg, Callable Func) {
77 for (MCRegUnitMaskIterator Units(PhysReg, TRI); Units.isValid(); ++Units) {
89 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) {
97 void LiveRegMatrix::assign(LiveInterval &VirtReg, unsigned PhysReg) {
99 << " to " << PrintReg(PhysReg, TRI) << ':');
101 VRM->assignVirt2Phys(VirtReg.reg, PhysReg);
103 foreachUnit(TRI, VirtReg, PhysReg, [&](unsigned Unit,
115 unsigned PhysReg = VRM->getPhys(VirtReg.reg);
117 << " from " << PrintReg(PhysReg, TRI) << ':');
120 foreachUnit(TRI, VirtReg, PhysReg, [&](unsigned Unit
[all...] |
| RegisterClassInfo.cpp | 99 unsigned PhysReg = RawOrder[i];
101 if (Reserved.test(PhysReg))
103 unsigned Cost = TRI->getCostPerUse(PhysReg);
106 if (CSRNum[PhysReg])
107 // PhysReg aliases a CSR, save it for later.
108 CSRAlias.push_back(PhysReg);
112 RCI.Order[N++] = PhysReg;
121 unsigned PhysReg = CSRAlias[i];
122 unsigned Cost = TRI->getCostPerUse(PhysReg);
125 RCI.Order[N++] = PhysReg;
[all...] |
| InterferenceCache.h | 39 /// of PhysReg in all basic blocks.
41 /// PhysReg - The register currently represented.
42 unsigned PhysReg;
63 /// RegUnitInfo - Information tracked about each RegUnit in PhysReg.
86 /// Info for each RegUnit in PhysReg. It is very rare ofr a PHysReg to have
97 Entry() : PhysReg(0), Tag(0), RefCount(0), Indexes(nullptr), LIS(nullptr) {}
101 PhysReg = 0;
107 unsigned getPhysReg() const { return PhysReg; }
115 /// valid - Return true if this is a valid entry for physReg
[all...] |
| ShrinkWrap.cpp | 233 unsigned PhysReg = MO.getReg();
234 if (!PhysReg)
236 assert(TargetRegisterInfo::isPhysicalRegister(PhysReg) &&
238 UseOrDefCSR = RCI.getLastCalleeSavedAlias(PhysReg);
|
| VirtRegMap.cpp | 168 void addLiveInsForSubRanges(const LiveInterval &LI, unsigned PhysReg) const;
245 unsigned PhysReg) const {
283 MBB->addLiveIn(PhysReg, LaneMask);
298 // assigned PhysReg must be marked as live-in to those blocks.
299 unsigned PhysReg = VRM->getPhys(VirtReg);
300 assert(PhysReg != VirtRegMap::NO_PHYS_REG && "Unmapped virtual register.");
303 addLiveInsForSubRanges(LI, PhysReg);
313 MBB->addLiveIn(PhysReg);
319 // Sort and unique MBB LiveIns as we've not checked if SubReg/PhysReg were in
399 unsigned PhysReg = VRM->getPhys(VirtReg)
[all...] |
| RegAllocFast.cpp | 72 unsigned PhysReg; // Currently held here.
77 : LastUse(nullptr), VirtReg(v), PhysReg(0), LastOpNum(0), Dirty(false){}
122 // Mark a physreg as used in this instruction.
123 void markRegUsedInInstr(unsigned PhysReg) {
124 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units)
128 // Check if a physreg or any of its aliases are used in this instruction.
129 bool isRegUsedInInstr(unsigned PhysReg) const {
130 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units)
181 void definePhysReg(MachineInstr &MI, unsigned PhysReg, RegState NewState);
182 unsigned calcSpillCost(unsigned PhysReg) const
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| FunctionLoweringInfo.cpp | 187 std::pair<unsigned, const TargetRegisterClass *> PhysReg =
190 if (PhysReg.first == SP)
|
| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| ScheduleDAGSDNodes.cpp | 105 unsigned &PhysReg, int &Cost) {
118 PhysReg = Reg;
428 unsigned PhysReg = 0;
431 CheckForPhysRegDependency(OpN, N, i, TRI, TII, PhysReg, Cost);
432 assert((PhysReg == 0 || !isChain) &&
433 "Chain dependence via physreg data?");
440 PhysReg = 0;
449 OpLatency, PhysReg);
|
| /prebuilts/clang/host/darwin-x86/clang-4393122/include/llvm/CodeGen/ |
| MachineBasicBlock.h | 73 MCPhysReg PhysReg;
76 RegisterMaskPair(MCPhysReg PhysReg, LaneBitmask LaneMask)
77 : PhysReg(PhysReg), LaneMask(LaneMask) {}
289 void addLiveIn(MCPhysReg PhysReg,
291 LiveIns.push_back(RegisterMaskPair(PhysReg, LaneMask));
305 /// Add PhysReg as live in to this block, and ensure that there is a copy of
306 /// PhysReg to a virtual register of class RC. Return the virtual register
307 /// that is a copy of the live in PhysReg.
308 unsigned addLiveIn(MCPhysReg PhysReg, const TargetRegisterClass *RC)
[all...] |
| /prebuilts/clang/host/darwin-x86/clang-4479392/include/llvm/CodeGen/ |
| MachineBasicBlock.h | 73 MCPhysReg PhysReg;
76 RegisterMaskPair(MCPhysReg PhysReg, LaneBitmask LaneMask)
77 : PhysReg(PhysReg), LaneMask(LaneMask) {}
289 void addLiveIn(MCPhysReg PhysReg,
291 LiveIns.push_back(RegisterMaskPair(PhysReg, LaneMask));
305 /// Add PhysReg as live in to this block, and ensure that there is a copy of
306 /// PhysReg to a virtual register of class RC. Return the virtual register
307 /// that is a copy of the live in PhysReg.
308 unsigned addLiveIn(MCPhysReg PhysReg, const TargetRegisterClass *RC)
[all...] |
| /prebuilts/clang/host/darwin-x86/clang-4579689/include/llvm/CodeGen/ |
| MachineBasicBlock.h | 73 MCPhysReg PhysReg;
76 RegisterMaskPair(MCPhysReg PhysReg, LaneBitmask LaneMask)
77 : PhysReg(PhysReg), LaneMask(LaneMask) {}
289 void addLiveIn(MCPhysReg PhysReg,
291 LiveIns.push_back(RegisterMaskPair(PhysReg, LaneMask));
305 /// Add PhysReg as live in to this block, and ensure that there is a copy of
306 /// PhysReg to a virtual register of class RC. Return the virtual register
307 /// that is a copy of the live in PhysReg.
308 unsigned addLiveIn(MCPhysReg PhysReg, const TargetRegisterClass *RC)
[all...] |
| /prebuilts/clang/host/darwin-x86/clang-4630689/include/llvm/CodeGen/ |
| MachineBasicBlock.h | 73 MCPhysReg PhysReg;
76 RegisterMaskPair(MCPhysReg PhysReg, LaneBitmask LaneMask)
77 : PhysReg(PhysReg), LaneMask(LaneMask) {}
289 void addLiveIn(MCPhysReg PhysReg,
291 LiveIns.push_back(RegisterMaskPair(PhysReg, LaneMask));
305 /// Add PhysReg as live in to this block, and ensure that there is a copy of
306 /// PhysReg to a virtual register of class RC. Return the virtual register
307 /// that is a copy of the live in PhysReg.
308 unsigned addLiveIn(MCPhysReg PhysReg, const TargetRegisterClass *RC)
[all...] |
| /prebuilts/clang/host/darwin-x86/clang-4639204/include/llvm/CodeGen/ |
| MachineBasicBlock.h | 73 MCPhysReg PhysReg;
76 RegisterMaskPair(MCPhysReg PhysReg, LaneBitmask LaneMask)
77 : PhysReg(PhysReg), LaneMask(LaneMask) {}
289 void addLiveIn(MCPhysReg PhysReg,
291 LiveIns.push_back(RegisterMaskPair(PhysReg, LaneMask));
305 /// Add PhysReg as live in to this block, and ensure that there is a copy of
306 /// PhysReg to a virtual register of class RC. Return the virtual register
307 /// that is a copy of the live in PhysReg.
308 unsigned addLiveIn(MCPhysReg PhysReg, const TargetRegisterClass *RC)
[all...] |
| /prebuilts/clang/host/darwin-x86/clang-4691093/include/llvm/CodeGen/ |
| MachineBasicBlock.h | 73 MCPhysReg PhysReg;
76 RegisterMaskPair(MCPhysReg PhysReg, LaneBitmask LaneMask)
77 : PhysReg(PhysReg), LaneMask(LaneMask) {}
289 void addLiveIn(MCPhysReg PhysReg,
291 LiveIns.push_back(RegisterMaskPair(PhysReg, LaneMask));
305 /// Add PhysReg as live in to this block, and ensure that there is a copy of
306 /// PhysReg to a virtual register of class RC. Return the virtual register
307 /// that is a copy of the live in PhysReg.
308 unsigned addLiveIn(MCPhysReg PhysReg, const TargetRegisterClass *RC)
[all...] |
| /prebuilts/clang/host/linux-x86/clang-4393122/include/llvm/CodeGen/ |
| MachineBasicBlock.h | 73 MCPhysReg PhysReg;
76 RegisterMaskPair(MCPhysReg PhysReg, LaneBitmask LaneMask)
77 : PhysReg(PhysReg), LaneMask(LaneMask) {}
289 void addLiveIn(MCPhysReg PhysReg,
291 LiveIns.push_back(RegisterMaskPair(PhysReg, LaneMask));
305 /// Add PhysReg as live in to this block, and ensure that there is a copy of
306 /// PhysReg to a virtual register of class RC. Return the virtual register
307 /// that is a copy of the live in PhysReg.
308 unsigned addLiveIn(MCPhysReg PhysReg, const TargetRegisterClass *RC)
[all...] |
| /prebuilts/clang/host/linux-x86/clang-4479392/include/llvm/CodeGen/ |
| MachineBasicBlock.h | 73 MCPhysReg PhysReg;
76 RegisterMaskPair(MCPhysReg PhysReg, LaneBitmask LaneMask)
77 : PhysReg(PhysReg), LaneMask(LaneMask) {}
289 void addLiveIn(MCPhysReg PhysReg,
291 LiveIns.push_back(RegisterMaskPair(PhysReg, LaneMask));
305 /// Add PhysReg as live in to this block, and ensure that there is a copy of
306 /// PhysReg to a virtual register of class RC. Return the virtual register
307 /// that is a copy of the live in PhysReg.
308 unsigned addLiveIn(MCPhysReg PhysReg, const TargetRegisterClass *RC)
[all...] |
| /prebuilts/clang/host/linux-x86/clang-4579689/include/llvm/CodeGen/ |
| MachineBasicBlock.h | 73 MCPhysReg PhysReg;
76 RegisterMaskPair(MCPhysReg PhysReg, LaneBitmask LaneMask)
77 : PhysReg(PhysReg), LaneMask(LaneMask) {}
289 void addLiveIn(MCPhysReg PhysReg,
291 LiveIns.push_back(RegisterMaskPair(PhysReg, LaneMask));
305 /// Add PhysReg as live in to this block, and ensure that there is a copy of
306 /// PhysReg to a virtual register of class RC. Return the virtual register
307 /// that is a copy of the live in PhysReg.
308 unsigned addLiveIn(MCPhysReg PhysReg, const TargetRegisterClass *RC)
[all...] |
| /prebuilts/clang/host/linux-x86/clang-4630689/include/llvm/CodeGen/ |
| MachineBasicBlock.h | 73 MCPhysReg PhysReg;
76 RegisterMaskPair(MCPhysReg PhysReg, LaneBitmask LaneMask)
77 : PhysReg(PhysReg), LaneMask(LaneMask) {}
289 void addLiveIn(MCPhysReg PhysReg,
291 LiveIns.push_back(RegisterMaskPair(PhysReg, LaneMask));
305 /// Add PhysReg as live in to this block, and ensure that there is a copy of
306 /// PhysReg to a virtual register of class RC. Return the virtual register
307 /// that is a copy of the live in PhysReg.
308 unsigned addLiveIn(MCPhysReg PhysReg, const TargetRegisterClass *RC)
[all...] |
| /prebuilts/clang/host/linux-x86/clang-4639204/include/llvm/CodeGen/ |
| MachineBasicBlock.h | 73 MCPhysReg PhysReg;
76 RegisterMaskPair(MCPhysReg PhysReg, LaneBitmask LaneMask)
77 : PhysReg(PhysReg), LaneMask(LaneMask) {}
289 void addLiveIn(MCPhysReg PhysReg,
291 LiveIns.push_back(RegisterMaskPair(PhysReg, LaneMask));
305 /// Add PhysReg as live in to this block, and ensure that there is a copy of
306 /// PhysReg to a virtual register of class RC. Return the virtual register
307 /// that is a copy of the live in PhysReg.
308 unsigned addLiveIn(MCPhysReg PhysReg, const TargetRegisterClass *RC)
[all...] |
