| /external/llvm/lib/Target/AArch64/ |
| AArch64PBQPRegAlloc.cpp | 159 bool A57ChainingConstraint::addIntraChainConstraint(PBQPRAGraph &G, unsigned Rd,
161 if (Rd == Ra)
166 if (TRI->isPhysicalRegister(Rd) || TRI->isPhysicalRegister(Ra)) {
167 DEBUG(dbgs() << "Rd is a physical reg:" << TRI->isPhysicalRegister(Rd)
174 PBQPRAGraph::NodeId node1 = G.getMetadata().getNodeIdForVReg(Rd);
187 const LiveInterval &ld = LIs.getInterval(Rd);
243 void A57ChainingConstraint::addInterChainConstraint(PBQPRAGraph &G, unsigned Rd,
249 if (Rd != Ra) {
251 << PrintReg(Rd, TRI) << '\n';)
[all...] |
| /prebuilts/go/darwin-x86/src/crypto/md5/ |
| md5block_arm.s | 15 #define Rd R5 // MD5 accumulator
65 MOVM.IA (Rc0), [Ra,Rb,Rc,Rd]
69 #define ROUND1(Ra, Rb, Rc, Rd, index, shift, Rconst) \
70 EOR Rc, Rd, Rt0 ; \
72 EOR Rd, Rt0 ; \
80 ROUND1(Ra, Rb, Rc, Rd, 0, 7, Rc0)
81 ROUND1(Rd, Ra, Rb, Rc, 1, 12, Rc1)
82 ROUND1(Rc, Rd, Ra, Rb, 2, 17, Rc2)
83 ROUND1(Rb, Rc, Rd, Ra, 3, 22, Rc3)
86 ROUND1(Ra, Rb, Rc, Rd, 4, 7, Rc0
[all...] |
| /prebuilts/go/linux-x86/src/crypto/md5/ |
| md5block_arm.s | 15 #define Rd R5 // MD5 accumulator
65 MOVM.IA (Rc0), [Ra,Rb,Rc,Rd]
69 #define ROUND1(Ra, Rb, Rc, Rd, index, shift, Rconst) \
70 EOR Rc, Rd, Rt0 ; \
72 EOR Rd, Rt0 ; \
80 ROUND1(Ra, Rb, Rc, Rd, 0, 7, Rc0)
81 ROUND1(Rd, Ra, Rb, Rc, 1, 12, Rc1)
82 ROUND1(Rc, Rd, Ra, Rb, 2, 17, Rc2)
83 ROUND1(Rb, Rc, Rd, Ra, 3, 22, Rc3)
86 ROUND1(Ra, Rb, Rc, Rd, 4, 7, Rc0
[all...] |
| /device/linaro/bootloader/edk2/ArmPkg/Library/ArmDisassemblerLib/ |
| ArmDisassembler.c | 169 UINT32 Rn, Rd, Rm;
183 Rd = (OpCode >> 12) & 0xf;
196 // A4.1.27 LDREX{<cond>} <Rd>, [<Rn>]
197 AsciiSPrint (Buf, Size, "LDREX%a %a, [%a]", COND (OpCode), gReg[Rd], gReg[Rn]);
199 // A4.1.103 STREX{<cond>} <Rd>, <Rm>, [<Rn>]
200 AsciiSPrint (Buf, Size, "STREX%a %a, %a, [%a]", COND (OpCode), gReg[Rd], gReg[Rn], gReg[Rn]);
226 Index = AsciiSPrint (Buf, Size, "%a%a%a%a %a, ", L ? "LDR" : "STR", COND (OpCode), BYTE (B), (!(P) && W) ? "T":"", gReg[Rd]);
297 // LDR|STR{<cond>}H|SH|SB|D <Rd>, <addressing_mode>
316 Index = AsciiSPrint (Buf, Size, Root, COND (OpCode), gReg[Rd]);
346 // A4.1.108 SWP SWP{<cond>}B <Rd>, <Rm>, [<Rn>]
[all...] |
| ThumbDisassembler.c | 115 { "ADR", 0xa000, 0xf800, ADR_FORMAT }, // ADR <Rd>, <label>
165 { "LSRS", 0x0800, 0xf800, DATA_FORMAT4 }, // LSRS <Rd>, <Rm>, #<imm5>
216 { "ADR", 0xf2af0000, 0xfbff8000, ADR_THUMB2 }, // ADDR <Rd>, <label> ;Needs to go before ADDW
225 { "MOV", 0xf04f0000, 0xfbef8000, ADD_IMM12_1REG }, // MOV <Rd>, #<const>
226 { "MOVW", 0xf2400000, 0xfbe08000, THUMB2_IMM16 }, // MOVW <Rd>, #<const>
227 { "MOVT", 0xf2c00000, 0xfbe08000, THUMB2_IMM16 }, // MOVT <Rd>, #<const>
229 { "ADC", 0xf1400000, 0xfbe08000, ADD_IMM12 }, // ADC{S} <Rd>, <Rn>, #<const>
230 { "ADC", 0xeb400000, 0xffe08000, ADD_IMM5 }, // ADC{S} <Rd>, <Rn>, <Rm> {,<shift> #<const>}
231 { "ADD", 0xf1000000, 0xfbe08000, ADD_IMM12 }, // ADD{S} <Rd>, <Rn>, #<const>
232 { "ADD", 0xeb000000, 0xffe08000, ADD_IMM5 }, // ADD{S} <Rd>, <Rn>, <Rm> {,<shift> #<const>}
[all...] |
| /prebuilts/go/darwin-x86/src/crypto/sha1/ |
| sha1block_arm.s | 31 #define Rd R5 // SHA-1 accumulator
83 #define FUNC1(Ra, Rb, Rc, Rd, Re) \
86 AND Rd, Rt1, Rt1 ; \
90 #define FUNC2(Ra, Rb, Rc, Rd, Re) \
92 EOR Rd, Rt1, Rt1
96 #define FUNC3(Ra, Rb, Rc, Rd, Re) \
99 AND Rd, Rt0, Rt0 ; \
107 #define MIX(Ra, Rb, Rc, Rd, Re) \
113 #define ROUND1(Ra, Rb, Rc, Rd, Re) \
115 FUNC1(Ra, Rb, Rc, Rd, Re) ;
[all...] |
| /prebuilts/go/linux-x86/src/crypto/sha1/ |
| sha1block_arm.s | 31 #define Rd R5 // SHA-1 accumulator
83 #define FUNC1(Ra, Rb, Rc, Rd, Re) \
86 AND Rd, Rt1, Rt1 ; \
90 #define FUNC2(Ra, Rb, Rc, Rd, Re) \
92 EOR Rd, Rt1, Rt1
96 #define FUNC3(Ra, Rb, Rc, Rd, Re) \
99 AND Rd, Rt0, Rt0 ; \
107 #define MIX(Ra, Rb, Rc, Rd, Re) \
113 #define ROUND1(Ra, Rb, Rc, Rd, Re) \
115 FUNC1(Ra, Rb, Rc, Rd, Re) ;
[all...] |
| /external/mesa3d/src/mesa/swrast/ |
| s_blend.c | 486 const GLfloat Rd = dest[i][RCOMP];
508 sR = Rd;
513 sR = 1.0F - Rd;
670 dR = Rd;
675 dR = 1.0F - Rd;
740 r = Rs * sR + Rd * dR;
746 r = Rs * sR - Rd * dR;
752 r = Rd * dR - Rs * sR;
758 r = MIN2( Rd, Rs );
763 r = MAX2( Rd, Rs )
[all...] |
| /external/llvm/lib/Target/AArch64/Disassembler/ |
| AArch64Disassembler.cpp | 652 unsigned Rd = fieldFromInstruction(Insn, 0, 5);
657 DecodeFPR128RegisterClass(Inst, Rd, Address, Decoder);
660 DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder);
[all...] |
| /external/capstone/arch/AArch64/ |
| AArch64Disassembler.c | 738 unsigned Rd = fieldFromInstruction(Insn, 0, 5);
743 DecodeFPR128RegisterClass(Inst, Rd, Address, Decoder);
746 DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder);
843 unsigned Rd = fieldFromInstruction(insn, 0, 5);
872 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
893 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
907 unsigned Rd = fieldFromInstruction(insn, 0, 5);
921 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
926 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
[all...] |
| /system/core/libpixelflinger/tests/arch-arm64/assembler/ |
| arm64_assembler_test.cpp | 413 void dataOpTest(dataOpTest_t test, ARMAssemblerInterface *a64asm, uint32_t Rd = 0,
427 regs[Rd] = test.RdValue;
449 case INSTR_ADD: a64asm->ADD(test.cond, test.setFlags, Rd,Rn,op2); break;
450 case INSTR_SUB: a64asm->SUB(test.cond, test.setFlags, Rd,Rn,op2); break;
451 case INSTR_RSB: a64asm->RSB(test.cond, test.setFlags, Rd,Rn,op2); break;
452 case INSTR_AND: a64asm->AND(test.cond, test.setFlags, Rd,Rn,op2); break;
453 case INSTR_ORR: a64asm->ORR(test.cond, test.setFlags, Rd,Rn,op2); break;
454 case INSTR_BIC: a64asm->BIC(test.cond, test.setFlags, Rd,Rn,op2); break;
455 case INSTR_MUL: a64asm->MUL(test.cond, test.setFlags, Rd,Rm,Rs); break;
456 case INSTR_MLA: a64asm->MLA(test.cond, test.setFlags, Rd,Rm,Rs,Rn); break
[all...] |
| /external/capstone/arch/ARM/ |
| ARMDisassembler.c | [all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/Disassembler/ |
| ARMDisassembler.cpp | [all...] |
| /external/swiftshader/third_party/subzero/src/ |
| IceAssemblerMIPS32.cpp | 245 llvm::report_fatal_error(std::string(InsnName) + ": Invalid 3rd operand");
271 const IValueT Rd = encodeGPRegister(OpRd, "Rd", InsnName);
275 Opcode |= Rd << 11;
284 const IValueT Rd = encodeGPRegister(OpRd, "Rd", InsnName);
290 Opcode |= Rd << 11;
527 const IValueT Rd = encodeGPRegister(OpRd, "Rd", "clz");
529 Opcode |= Rd << 11
[all...] |
| /external/vixl/src/aarch64/ |
| assembler-aarch64.h | 602 void add(const Register& rd, const Register& rn, const Operand& operand);
605 void adds(const Register& rd, const Register& rn, const Operand& operand);
611 void sub(const Register& rd, const Register& rn, const Operand& operand);
614 void subs(const Register& rd, const Register& rn, const Operand& operand);
620 void neg(const Register& rd, const Operand& operand);
623 void negs(const Register& rd, const Operand& operand);
626 void adc(const Register& rd, const Register& rn, const Operand& operand);
629 void adcs(const Register& rd, const Register& rn, const Operand& operand);
632 void sbc(const Register& rd, const Register& rn, const Operand& operand);
635 void sbcs(const Register& rd, const Register& rn, const Operand& operand)
[all...] |
| /external/llvm/lib/Target/ARM/Disassembler/ |
| ARMDisassembler.cpp | [all...] |
| /external/llvm/lib/Target/Hexagon/AsmParser/ |
| HexagonAsmParser.cpp | [all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonFrameLowering.cpp | 115 // Rd = ALLOCA Rs, A
117 // Rd - address of the allocated space
[all...] |
| HexagonInstrInfo.cpp | [all...] |
| /toolchain/binutils/binutils-2.27/gas/config/ |
| tc-arm.c | 22527 int rd; local
23626 int rd = (newval >> 4) & 0xf; local
23825 int rd, rs; local
[all...] |
| /toolchain/binutils/binutils-2.27/opcodes/ |
| i386-dis.c | 282 #define Rd { OP_R, d_mode }
[all...] |
