1 /** @file 2 Declaration of IO handling routines. 3 4 Copyright (c) 2013-2015 Intel Corporation. 5 6 This program and the accompanying materials 7 are licensed and made available under the terms and conditions of the BSD License 8 which accompanies this distribution. The full text of the license may be found at 9 http://opensource.org/licenses/bsd-license.php 10 11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 13 14 **/ 15 #ifndef __IO_H 16 #define __IO_H 17 18 #include "core_types.h" 19 20 #include "general_definitions.h" 21 #include "gen5_iosf_sb_definitions.h" 22 23 // Instruction not present on Quark 24 #define SFENCE() 25 26 #define DEAD_LOOP() for(;;); 27 28 //// 29 // Define each of the IOSF_SB ports used by MRC 30 // 31 32 // 33 // Has to be 0 because of emulation static data 34 // initialisation: 35 // Space_t EmuSpace[ SPACE_COUNT] = {0}; 36 // 37 #define FREE 0x000 38 39 // Pseudo side-band ports for access abstraction 40 // See Wr32/Rd32 functions 41 #define MEM 0x101 42 #define MMIO 0x102 43 #define DCMD 0x0A0 44 45 // Real side-band ports 46 // See Wr32/Rd32 functions 47 #define MCU 0x001 48 #define HOST_BRIDGE 0x003 49 #define MEMORY_MANAGER 0x005 50 #define HTE 0x011 51 #define DDRPHY 0x012 52 #define FUSE 0x033 53 54 // End of IOSF_SB ports 55 //// 56 57 // Pciexbar address 58 #define EC_BASE 0xE0000000 59 60 #define PCIADDR(bus,dev,fn,reg) ( \ 61 (EC_BASE) + \ 62 ((bus) << 20) + \ 63 ((dev) << 15) + \ 64 ((fn) << 12) + \ 65 (reg)) 66 67 // Various offsets used in the building sideband commands. 68 #define SB_OPCODE_OFFSET 24 69 #define SB_PORT_OFFSET 16 70 #define SB_REG_OFFEST 8 71 72 // Sideband opcodes 73 #define SB_REG_READ_OPCODE 0x10 74 #define SB_REG_WRITE_OPCODE 0x11 75 76 #define SB_FUSE_REG_READ_OPCODE 0x06 77 #define SB_FUSE_REG_WRITE_OPCODE 0x07 78 79 #define SB_DDRIO_REG_READ_OPCODE 0x06 80 #define SB_DDRIO_REG_WRITE_OPCODE 0x07 81 82 #define SB_DRAM_CMND_OPCODE 0x68 83 #define SB_WAKE_CMND_OPCODE 0xCA 84 #define SB_SUSPEND_CMND_OPCODE 0xCC 85 86 // Register addresses for sideband command and data. 87 #define SB_PACKET_REG 0x00D0 88 #define SB_DATA_REG 0x00D4 89 #define SB_HADR_REG 0x00D8 90 91 // We always flag all 4 bytes in the register reads/writes as required. 92 #define SB_ALL_BYTES_ENABLED 0xF0 93 94 #define SB_COMMAND(Opcode, Port, Reg) \ 95 ((Opcode << SB_OPCODE_OFFSET) | \ 96 (Port << SB_PORT_OFFSET) | \ 97 (Reg << SB_REG_OFFEST) | \ 98 SB_ALL_BYTES_ENABLED) 99 100 // iosf 101 #define isbM32m WrMask32 102 #define isbW32m Wr32 103 #define isbR32m Rd32 104 105 // pci 106 107 void pciwrite32( 108 uint32_t bus, 109 uint32_t dev, 110 uint32_t fn, 111 uint32_t reg, 112 uint32_t data); 113 114 uint32_t pciread32( 115 uint32_t bus, 116 uint32_t dev, 117 uint32_t fn, 118 uint32_t reg); 119 120 // general 121 122 uint32_t Rd32( 123 uint32_t unit, 124 uint32_t addr); 125 126 void Wr32( 127 uint32_t unit, 128 uint32_t addr, 129 uint32_t data); 130 131 void WrMask32( 132 uint32_t unit, 133 uint32_t addr, 134 uint32_t data, 135 uint32_t mask); 136 137 138 #endif 139
