1 /* 2 * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __PSCI_PRIVATE_H__ 8 #define __PSCI_PRIVATE_H__ 9 10 #include <arch.h> 11 #include <bakery_lock.h> 12 #include <bl_common.h> 13 #include <cpu_data.h> 14 #include <psci.h> 15 #include <spinlock.h> 16 17 #if HW_ASSISTED_COHERENCY 18 19 /* 20 * On systems with hardware-assisted coherency, make PSCI cache operations NOP, 21 * as PSCI participants are cache-coherent, and there's no need for explicit 22 * cache maintenance operations or barriers to coordinate their state. 23 */ 24 #define psci_flush_dcache_range(addr, size) 25 #define psci_flush_cpu_data(member) 26 #define psci_inv_cpu_data(member) 27 28 #define psci_dsbish() 29 30 /* 31 * On systems where participant CPUs are cache-coherent, we can use spinlocks 32 * instead of bakery locks. 33 */ 34 #define DEFINE_PSCI_LOCK(_name) spinlock_t _name 35 #define DECLARE_PSCI_LOCK(_name) extern DEFINE_PSCI_LOCK(_name) 36 37 #define psci_lock_get(non_cpu_pd_node) \ 38 spin_lock(&psci_locks[(non_cpu_pd_node)->lock_index]) 39 #define psci_lock_release(non_cpu_pd_node) \ 40 spin_unlock(&psci_locks[(non_cpu_pd_node)->lock_index]) 41 42 #else 43 44 /* 45 * If not all PSCI participants are cache-coherent, perform cache maintenance 46 * and issue barriers wherever required to coordinate state. 47 */ 48 #define psci_flush_dcache_range(addr, size) flush_dcache_range(addr, size) 49 #define psci_flush_cpu_data(member) flush_cpu_data(member) 50 #define psci_inv_cpu_data(member) inv_cpu_data(member) 51 52 #define psci_dsbish() dsbish() 53 54 /* 55 * Use bakery locks for state coordination as not all PSCI participants are 56 * cache coherent. 57 */ 58 #define DEFINE_PSCI_LOCK(_name) DEFINE_BAKERY_LOCK(_name) 59 #define DECLARE_PSCI_LOCK(_name) DECLARE_BAKERY_LOCK(_name) 60 61 #define psci_lock_get(non_cpu_pd_node) \ 62 bakery_lock_get(&psci_locks[(non_cpu_pd_node)->lock_index]) 63 #define psci_lock_release(non_cpu_pd_node) \ 64 bakery_lock_release(&psci_locks[(non_cpu_pd_node)->lock_index]) 65 66 #endif 67 68 #define psci_lock_init(non_cpu_pd_node, idx) \ 69 ((non_cpu_pd_node)[(idx)].lock_index = (idx)) 70 71 /* 72 * The PSCI capability which are provided by the generic code but does not 73 * depend on the platform or spd capabilities. 74 */ 75 #define PSCI_GENERIC_CAP \ 76 (define_psci_cap(PSCI_VERSION) | \ 77 define_psci_cap(PSCI_AFFINITY_INFO_AARCH64) | \ 78 define_psci_cap(PSCI_FEATURES)) 79 80 /* 81 * The PSCI capabilities mask for 64 bit functions. 82 */ 83 #define PSCI_CAP_64BIT_MASK \ 84 (define_psci_cap(PSCI_CPU_SUSPEND_AARCH64) | \ 85 define_psci_cap(PSCI_CPU_ON_AARCH64) | \ 86 define_psci_cap(PSCI_AFFINITY_INFO_AARCH64) | \ 87 define_psci_cap(PSCI_MIG_AARCH64) | \ 88 define_psci_cap(PSCI_MIG_INFO_UP_CPU_AARCH64) | \ 89 define_psci_cap(PSCI_NODE_HW_STATE_AARCH64) | \ 90 define_psci_cap(PSCI_SYSTEM_SUSPEND_AARCH64) | \ 91 define_psci_cap(PSCI_STAT_RESIDENCY_AARCH64) | \ 92 define_psci_cap(PSCI_STAT_COUNT_AARCH64) | \ 93 define_psci_cap(PSCI_SYSTEM_RESET2_AARCH64) | \ 94 define_psci_cap(PSCI_MEM_CHK_RANGE_AARCH64)) 95 96 /* 97 * Helper macros to get/set the fields of PSCI per-cpu data. 98 */ 99 #define psci_set_aff_info_state(aff_state) \ 100 set_cpu_data(psci_svc_cpu_data.aff_info_state, aff_state) 101 #define psci_get_aff_info_state() \ 102 get_cpu_data(psci_svc_cpu_data.aff_info_state) 103 #define psci_get_aff_info_state_by_idx(idx) \ 104 get_cpu_data_by_index(idx, psci_svc_cpu_data.aff_info_state) 105 #define psci_set_aff_info_state_by_idx(idx, aff_state) \ 106 set_cpu_data_by_index(idx, psci_svc_cpu_data.aff_info_state,\ 107 aff_state) 108 #define psci_get_suspend_pwrlvl() \ 109 get_cpu_data(psci_svc_cpu_data.target_pwrlvl) 110 #define psci_set_suspend_pwrlvl(target_lvl) \ 111 set_cpu_data(psci_svc_cpu_data.target_pwrlvl, target_lvl) 112 #define psci_set_cpu_local_state(state) \ 113 set_cpu_data(psci_svc_cpu_data.local_state, state) 114 #define psci_get_cpu_local_state() \ 115 get_cpu_data(psci_svc_cpu_data.local_state) 116 #define psci_get_cpu_local_state_by_idx(idx) \ 117 get_cpu_data_by_index(idx, psci_svc_cpu_data.local_state) 118 119 /* 120 * Helper macros for the CPU level spinlocks 121 */ 122 #define psci_spin_lock_cpu(idx) spin_lock(&psci_cpu_pd_nodes[idx].cpu_lock) 123 #define psci_spin_unlock_cpu(idx) spin_unlock(&psci_cpu_pd_nodes[idx].cpu_lock) 124 125 /* Helper macro to identify a CPU standby request in PSCI Suspend call */ 126 #define is_cpu_standby_req(is_power_down_state, retn_lvl) \ 127 (((!(is_power_down_state)) && ((retn_lvl) == 0)) ? 1 : 0) 128 129 /******************************************************************************* 130 * The following two data structures implement the power domain tree. The tree 131 * is used to track the state of all the nodes i.e. power domain instances 132 * described by the platform. The tree consists of nodes that describe CPU power 133 * domains i.e. leaf nodes and all other power domains which are parents of a 134 * CPU power domain i.e. non-leaf nodes. 135 ******************************************************************************/ 136 typedef struct non_cpu_pwr_domain_node { 137 /* 138 * Index of the first CPU power domain node level 0 which has this node 139 * as its parent. 140 */ 141 unsigned int cpu_start_idx; 142 143 /* 144 * Number of CPU power domains which are siblings of the domain indexed 145 * by 'cpu_start_idx' i.e. all the domains in the range 'cpu_start_idx 146 * -> cpu_start_idx + ncpus' have this node as their parent. 147 */ 148 unsigned int ncpus; 149 150 /* 151 * Index of the parent power domain node. 152 * TODO: Figure out whether to whether using pointer is more efficient. 153 */ 154 unsigned int parent_node; 155 156 plat_local_state_t local_state; 157 158 unsigned char level; 159 160 /* For indexing the psci_lock array*/ 161 unsigned char lock_index; 162 } non_cpu_pd_node_t; 163 164 typedef struct cpu_pwr_domain_node { 165 u_register_t mpidr; 166 167 /* 168 * Index of the parent power domain node. 169 * TODO: Figure out whether to whether using pointer is more efficient. 170 */ 171 unsigned int parent_node; 172 173 /* 174 * A CPU power domain does not require state coordination like its 175 * parent power domains. Hence this node does not include a bakery 176 * lock. A spinlock is required by the CPU_ON handler to prevent a race 177 * when multiple CPUs try to turn ON the same target CPU. 178 */ 179 spinlock_t cpu_lock; 180 } cpu_pd_node_t; 181 182 /******************************************************************************* 183 * Data prototypes 184 ******************************************************************************/ 185 extern const plat_psci_ops_t *psci_plat_pm_ops; 186 extern non_cpu_pd_node_t psci_non_cpu_pd_nodes[PSCI_NUM_NON_CPU_PWR_DOMAINS]; 187 extern cpu_pd_node_t psci_cpu_pd_nodes[PLATFORM_CORE_COUNT]; 188 extern unsigned int psci_caps; 189 190 /* One lock is required per non-CPU power domain node */ 191 DECLARE_PSCI_LOCK(psci_locks[PSCI_NUM_NON_CPU_PWR_DOMAINS]); 192 193 /******************************************************************************* 194 * SPD's power management hooks registered with PSCI 195 ******************************************************************************/ 196 extern const spd_pm_ops_t *psci_spd_pm; 197 198 /******************************************************************************* 199 * Function prototypes 200 ******************************************************************************/ 201 /* Private exported functions from psci_common.c */ 202 int psci_validate_power_state(unsigned int power_state, 203 psci_power_state_t *state_info); 204 void psci_query_sys_suspend_pwrstate(psci_power_state_t *state_info); 205 int psci_validate_mpidr(u_register_t mpidr); 206 void psci_init_req_local_pwr_states(void); 207 void psci_get_target_local_pwr_states(unsigned int end_pwrlvl, 208 psci_power_state_t *target_state); 209 int psci_validate_entry_point(entry_point_info_t *ep, 210 uintptr_t entrypoint, u_register_t context_id); 211 void psci_get_parent_pwr_domain_nodes(unsigned int cpu_idx, 212 unsigned int end_lvl, 213 unsigned int node_index[]); 214 void psci_do_state_coordination(unsigned int end_pwrlvl, 215 psci_power_state_t *state_info); 216 void psci_acquire_pwr_domain_locks(unsigned int end_pwrlvl, 217 unsigned int cpu_idx); 218 void psci_release_pwr_domain_locks(unsigned int end_pwrlvl, 219 unsigned int cpu_idx); 220 int psci_validate_suspend_req(const psci_power_state_t *state_info, 221 unsigned int is_power_down_state_req); 222 unsigned int psci_find_max_off_lvl(const psci_power_state_t *state_info); 223 unsigned int psci_find_target_suspend_lvl(const psci_power_state_t *state_info); 224 void psci_set_pwr_domains_to_run(unsigned int end_pwrlvl); 225 void psci_print_power_domain_map(void); 226 unsigned int psci_is_last_on_cpu(void); 227 int psci_spd_migrate_info(u_register_t *mpidr); 228 void psci_do_pwrdown_sequence(unsigned int power_level); 229 230 /* 231 * CPU power down is directly called only when HW_ASSISTED_COHERENCY is 232 * available. Otherwise, this needs post-call stack maintenance, which is 233 * handled in assembly. 234 */ 235 void prepare_cpu_pwr_dwn(unsigned int power_level); 236 237 /* Private exported functions from psci_on.c */ 238 int psci_cpu_on_start(u_register_t target_cpu, 239 entry_point_info_t *ep); 240 241 void psci_cpu_on_finish(unsigned int cpu_idx, 242 psci_power_state_t *state_info); 243 244 /* Private exported functions from psci_off.c */ 245 int psci_do_cpu_off(unsigned int end_pwrlvl); 246 247 /* Private exported functions from psci_suspend.c */ 248 void psci_cpu_suspend_start(entry_point_info_t *ep, 249 unsigned int end_pwrlvl, 250 psci_power_state_t *state_info, 251 unsigned int is_power_down_state_req); 252 253 void psci_cpu_suspend_finish(unsigned int cpu_idx, 254 psci_power_state_t *state_info); 255 256 /* Private exported functions from psci_helpers.S */ 257 void psci_do_pwrdown_cache_maintenance(unsigned int pwr_level); 258 void psci_do_pwrup_cache_maintenance(void); 259 260 /* Private exported functions from psci_system_off.c */ 261 void __dead2 psci_system_off(void); 262 void __dead2 psci_system_reset(void); 263 int psci_system_reset2(uint32_t reset_type, u_register_t cookie); 264 265 /* Private exported functions from psci_stat.c */ 266 void psci_stats_update_pwr_down(unsigned int end_pwrlvl, 267 const psci_power_state_t *state_info); 268 void psci_stats_update_pwr_up(unsigned int end_pwrlvl, 269 const psci_power_state_t *state_info); 270 u_register_t psci_stat_residency(u_register_t target_cpu, 271 unsigned int power_state); 272 u_register_t psci_stat_count(u_register_t target_cpu, 273 unsigned int power_state); 274 275 /* Private exported functions from psci_mem_protect.c */ 276 int psci_mem_protect(unsigned int enable); 277 int psci_mem_chk_range(uintptr_t base, u_register_t length); 278 279 #endif /* __PSCI_PRIVATE_H__ */ 280
