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      1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
      2 
      3 /*
      4  * Copyright (C) 2012 Rob Clark <robclark (at) freedesktop.org>
      5  *
      6  * Permission is hereby granted, free of charge, to any person obtaining a
      7  * copy of this software and associated documentation files (the "Software"),
      8  * to deal in the Software without restriction, including without limitation
      9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
     10  * and/or sell copies of the Software, and to permit persons to whom the
     11  * Software is furnished to do so, subject to the following conditions:
     12  *
     13  * The above copyright notice and this permission notice (including the next
     14  * paragraph) shall be included in all copies or substantial portions of the
     15  * Software.
     16  *
     17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
     20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
     21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
     22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
     23  * SOFTWARE.
     24  *
     25  * Authors:
     26  *    Rob Clark <robclark (at) freedesktop.org>
     27  */
     28 
     29 
     30 #include "pipe/p_defines.h"
     31 #include "pipe/p_screen.h"
     32 #include "pipe/p_state.h"
     33 
     34 #include "util/u_memory.h"
     35 #include "util/u_inlines.h"
     36 #include "util/u_format.h"
     37 #include "util/u_format_s3tc.h"
     38 #include "util/u_string.h"
     39 #include "util/u_debug.h"
     40 
     41 #include "os/os_time.h"
     42 
     43 #include <stdio.h>
     44 #include <errno.h>
     45 #include <stdlib.h>
     46 
     47 #include "freedreno_screen.h"
     48 #include "freedreno_resource.h"
     49 #include "freedreno_fence.h"
     50 #include "freedreno_query.h"
     51 #include "freedreno_util.h"
     52 
     53 #include "a2xx/fd2_screen.h"
     54 #include "a3xx/fd3_screen.h"
     55 #include "a4xx/fd4_screen.h"
     56 #include "a5xx/fd5_screen.h"
     57 
     58 #include "ir3/ir3_nir.h"
     59 
     60 /* XXX this should go away */
     61 #include "state_tracker/drm_driver.h"
     62 
     63 static const struct debug_named_value debug_options[] = {
     64 		{"msgs",      FD_DBG_MSGS,   "Print debug messages"},
     65 		{"disasm",    FD_DBG_DISASM, "Dump TGSI and adreno shader disassembly"},
     66 		{"dclear",    FD_DBG_DCLEAR, "Mark all state dirty after clear"},
     67 		{"ddraw",     FD_DBG_DDRAW,  "Mark all state dirty after draw"},
     68 		{"noscis",    FD_DBG_NOSCIS, "Disable scissor optimization"},
     69 		{"direct",    FD_DBG_DIRECT, "Force inline (SS_DIRECT) state loads"},
     70 		{"nobypass",  FD_DBG_NOBYPASS, "Disable GMEM bypass"},
     71 		{"fraghalf",  FD_DBG_FRAGHALF, "Use half-precision in fragment shader"},
     72 		{"nobin",     FD_DBG_NOBIN,  "Disable hw binning"},
     73 		{"optmsgs",   FD_DBG_OPTMSGS,"Enable optimizer debug messages"},
     74 		{"glsl120",   FD_DBG_GLSL120,"Temporary flag to force GLSL 1.20 (rather than 1.30) on a3xx+"},
     75 		{"shaderdb",  FD_DBG_SHADERDB, "Enable shaderdb output"},
     76 		{"flush",     FD_DBG_FLUSH,  "Force flush after every draw"},
     77 		{"deqp",      FD_DBG_DEQP,   "Enable dEQP hacks"},
     78 		{"nir",       FD_DBG_NIR,    "Prefer NIR as native IR"},
     79 		{"reorder",   FD_DBG_REORDER,"Enable reordering for draws/blits"},
     80 		{"bstat",     FD_DBG_BSTAT,  "Print batch stats at context destroy"},
     81 		{"nogrow",    FD_DBG_NOGROW, "Disable \"growable\" cmdstream buffers, even if kernel supports it"},
     82 		DEBUG_NAMED_VALUE_END
     83 };
     84 
     85 DEBUG_GET_ONCE_FLAGS_OPTION(fd_mesa_debug, "FD_MESA_DEBUG", debug_options, 0)
     86 
     87 int fd_mesa_debug = 0;
     88 bool fd_binning_enabled = true;
     89 static bool glsl120 = false;
     90 
     91 static const char *
     92 fd_screen_get_name(struct pipe_screen *pscreen)
     93 {
     94 	static char buffer[128];
     95 	util_snprintf(buffer, sizeof(buffer), "FD%03d",
     96 			fd_screen(pscreen)->device_id);
     97 	return buffer;
     98 }
     99 
    100 static const char *
    101 fd_screen_get_vendor(struct pipe_screen *pscreen)
    102 {
    103 	return "freedreno";
    104 }
    105 
    106 static const char *
    107 fd_screen_get_device_vendor(struct pipe_screen *pscreen)
    108 {
    109 	return "Qualcomm";
    110 }
    111 
    112 
    113 static uint64_t
    114 fd_screen_get_timestamp(struct pipe_screen *pscreen)
    115 {
    116 	struct fd_screen *screen = fd_screen(pscreen);
    117 
    118 	if (screen->has_timestamp) {
    119 		uint64_t n;
    120 		fd_pipe_get_param(screen->pipe, FD_TIMESTAMP, &n);
    121 		debug_assert(screen->max_freq > 0);
    122 		return n * 1000000000 / screen->max_freq;
    123 	} else {
    124 		int64_t cpu_time = os_time_get() * 1000;
    125 		return cpu_time + screen->cpu_gpu_time_delta;
    126 	}
    127 
    128 }
    129 
    130 static void
    131 fd_screen_destroy(struct pipe_screen *pscreen)
    132 {
    133 	struct fd_screen *screen = fd_screen(pscreen);
    134 
    135 	if (screen->pipe)
    136 		fd_pipe_del(screen->pipe);
    137 
    138 	if (screen->dev)
    139 		fd_device_del(screen->dev);
    140 
    141 	fd_bc_fini(&screen->batch_cache);
    142 
    143 	slab_destroy_parent(&screen->transfer_pool);
    144 
    145 	pipe_mutex_destroy(screen->lock);
    146 
    147 	free(screen);
    148 }
    149 
    150 /*
    151 TODO either move caps to a2xx/a3xx specific code, or maybe have some
    152 tables for things that differ if the delta is not too much..
    153  */
    154 static int
    155 fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
    156 {
    157 	struct fd_screen *screen = fd_screen(pscreen);
    158 
    159 	/* this is probably not totally correct.. but it's a start: */
    160 	switch (param) {
    161 	/* Supported features (boolean caps). */
    162 	case PIPE_CAP_NPOT_TEXTURES:
    163 	case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
    164 	case PIPE_CAP_TWO_SIDED_STENCIL:
    165 	case PIPE_CAP_ANISOTROPIC_FILTER:
    166 	case PIPE_CAP_POINT_SPRITE:
    167 	case PIPE_CAP_TEXTURE_SHADOW_MAP:
    168 	case PIPE_CAP_BLEND_EQUATION_SEPARATE:
    169 	case PIPE_CAP_TEXTURE_SWIZZLE:
    170 	case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
    171 	case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
    172 	case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
    173 	case PIPE_CAP_SEAMLESS_CUBE_MAP:
    174 	case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
    175 	case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
    176 	case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
    177 	case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
    178 	case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
    179 	case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
    180 	case PIPE_CAP_STRING_MARKER:
    181 	case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
    182 		return 1;
    183 
    184 	case PIPE_CAP_VERTEXID_NOBASE:
    185 		return is_a3xx(screen) || is_a4xx(screen);
    186 
    187 	case PIPE_CAP_USER_CONSTANT_BUFFERS:
    188 		return is_a4xx(screen) ? 0 : 1;
    189 
    190 	case PIPE_CAP_SHADER_STENCIL_EXPORT:
    191 	case PIPE_CAP_TGSI_TEXCOORD:
    192 	case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
    193 	case PIPE_CAP_TEXTURE_MULTISAMPLE:
    194 	case PIPE_CAP_TEXTURE_BARRIER:
    195 	case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
    196 	case PIPE_CAP_COMPUTE:
    197 	case PIPE_CAP_QUERY_MEMORY_INFO:
    198 	case PIPE_CAP_PCI_GROUP:
    199 	case PIPE_CAP_PCI_BUS:
    200 	case PIPE_CAP_PCI_DEVICE:
    201 	case PIPE_CAP_PCI_FUNCTION:
    202 		return 0;
    203 
    204 	case PIPE_CAP_SM3:
    205 	case PIPE_CAP_PRIMITIVE_RESTART:
    206 	case PIPE_CAP_TGSI_INSTANCEID:
    207 	case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
    208 	case PIPE_CAP_INDEP_BLEND_ENABLE:
    209 	case PIPE_CAP_INDEP_BLEND_FUNC:
    210 	case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
    211 	case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
    212 	case PIPE_CAP_CONDITIONAL_RENDER:
    213 	case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
    214 	case PIPE_CAP_FAKE_SW_MSAA:
    215 	case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
    216 	case PIPE_CAP_DEPTH_CLIP_DISABLE:
    217 	case PIPE_CAP_CLIP_HALFZ:
    218 		return is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen);
    219 
    220 	case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
    221 		return 0;
    222 	case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
    223 		if (is_a3xx(screen)) return 16;
    224 		if (is_a4xx(screen)) return 32;
    225 		if (is_a5xx(screen)) return 32;
    226 		return 0;
    227 	case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
    228 		/* We could possibly emulate more by pretending 2d/rect textures and
    229 		 * splitting high bits of index into 2nd dimension..
    230 		 */
    231 		if (is_a3xx(screen)) return 8192;
    232 		if (is_a4xx(screen)) return 16384;
    233 		if (is_a5xx(screen)) return 16384;
    234 		return 0;
    235 
    236 	case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
    237 	case PIPE_CAP_CUBE_MAP_ARRAY:
    238 	case PIPE_CAP_START_INSTANCE:
    239 	case PIPE_CAP_SAMPLER_VIEW_TARGET:
    240 	case PIPE_CAP_TEXTURE_QUERY_LOD:
    241 		return is_a4xx(screen) || is_a5xx(screen);
    242 
    243 	case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
    244 		return 64;
    245 
    246 	case PIPE_CAP_GLSL_FEATURE_LEVEL:
    247 		if (glsl120)
    248 			return 120;
    249 		return is_ir3(screen) ? 140 : 120;
    250 
    251 	/* Unsupported features. */
    252 	case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
    253 	case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
    254 	case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
    255 	case PIPE_CAP_USER_VERTEX_BUFFERS:
    256 	case PIPE_CAP_USER_INDEX_BUFFERS:
    257 	case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
    258 	case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
    259 	case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
    260 	case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
    261 	case PIPE_CAP_TEXTURE_GATHER_SM5:
    262 	case PIPE_CAP_SAMPLE_SHADING:
    263 	case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
    264 	case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
    265 	case PIPE_CAP_DRAW_INDIRECT:
    266 	case PIPE_CAP_MULTI_DRAW_INDIRECT:
    267 	case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
    268 	case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
    269 	case PIPE_CAP_POLYGON_OFFSET_CLAMP:
    270 	case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
    271 	case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
    272 	case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
    273 	case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
    274 	case PIPE_CAP_DEPTH_BOUNDS_TEST:
    275 	case PIPE_CAP_TGSI_TXQS:
    276 	/* TODO if we need this, do it in nir/ir3 backend to avoid breaking precompile: */
    277 	case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
    278 	case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
    279 	case PIPE_CAP_CLEAR_TEXTURE:
    280 	case PIPE_CAP_DRAW_PARAMETERS:
    281 	case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
    282 	case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
    283 	case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
    284 	case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
    285 	case PIPE_CAP_INVALIDATE_BUFFER:
    286 	case PIPE_CAP_GENERATE_MIPMAP:
    287 	case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
    288 	case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
    289 	case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
    290 	case PIPE_CAP_CULL_DISTANCE:
    291 	case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
    292 	case PIPE_CAP_TGSI_VOTE:
    293 	case PIPE_CAP_MAX_WINDOW_RECTANGLES:
    294 	case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
    295 	case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
    296 	case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
    297 	case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
    298 	case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
    299 	case PIPE_CAP_TGSI_FS_FBFETCH:
    300 		return 0;
    301 
    302 	case PIPE_CAP_MAX_VIEWPORTS:
    303 		return 1;
    304 
    305 	case PIPE_CAP_SHAREABLE_SHADERS:
    306 	/* manage the variants for these ourself, to avoid breaking precompile: */
    307 	case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
    308 	case PIPE_CAP_VERTEX_COLOR_CLAMPED:
    309 		if (is_ir3(screen))
    310 			return 1;
    311 		return 0;
    312 
    313 	/* Stream output. */
    314 	case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
    315 		if (is_ir3(screen))
    316 			return PIPE_MAX_SO_BUFFERS;
    317 		return 0;
    318 	case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
    319 	case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
    320 		if (is_ir3(screen))
    321 			return 1;
    322 		return 0;
    323 	case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
    324 	case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
    325 		if (is_ir3(screen))
    326 			return 16 * 4;   /* should only be shader out limit? */
    327 		return 0;
    328 
    329 	/* Geometry shader output, unsupported. */
    330 	case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
    331 	case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
    332 	case PIPE_CAP_MAX_VERTEX_STREAMS:
    333 		return 0;
    334 
    335 	case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
    336 		return 2048;
    337 
    338 	/* Texturing. */
    339 	case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
    340 	case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
    341 		return MAX_MIP_LEVELS;
    342 	case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
    343 		return 11;
    344 
    345 	case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
    346 		return (is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen)) ? 256 : 0;
    347 
    348 	/* Render targets. */
    349 	case PIPE_CAP_MAX_RENDER_TARGETS:
    350 		return screen->max_rts;
    351 	case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
    352 		return is_a3xx(screen) ? 1 : 0;
    353 
    354 	/* Queries. */
    355 	case PIPE_CAP_QUERY_BUFFER_OBJECT:
    356 		return 0;
    357 	case PIPE_CAP_OCCLUSION_QUERY:
    358 		return is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen);
    359 	case PIPE_CAP_QUERY_TIMESTAMP:
    360 	case PIPE_CAP_QUERY_TIME_ELAPSED:
    361 		/* only a4xx, requires new enough kernel so we know max_freq: */
    362 		return (screen->max_freq > 0) && is_a4xx(screen);
    363 
    364 	case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
    365 	case PIPE_CAP_MIN_TEXEL_OFFSET:
    366 		return -8;
    367 
    368 	case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
    369 	case PIPE_CAP_MAX_TEXEL_OFFSET:
    370 		return 7;
    371 
    372 	case PIPE_CAP_ENDIANNESS:
    373 		return PIPE_ENDIAN_LITTLE;
    374 
    375 	case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
    376 		return 64;
    377 
    378 	case PIPE_CAP_VENDOR_ID:
    379 		return 0x5143;
    380 	case PIPE_CAP_DEVICE_ID:
    381 		return 0xFFFFFFFF;
    382 	case PIPE_CAP_ACCELERATED:
    383 		return 1;
    384 	case PIPE_CAP_VIDEO_MEMORY:
    385 		DBG("FINISHME: The value returned is incorrect\n");
    386 		return 10;
    387 	case PIPE_CAP_UMA:
    388 		return 1;
    389 	case PIPE_CAP_NATIVE_FENCE_FD:
    390 		return fd_device_version(screen->dev) >= FD_VERSION_FENCE_FD;
    391 	}
    392 	debug_printf("unknown param %d\n", param);
    393 	return 0;
    394 }
    395 
    396 static float
    397 fd_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
    398 {
    399 	switch (param) {
    400 	case PIPE_CAPF_MAX_LINE_WIDTH:
    401 	case PIPE_CAPF_MAX_LINE_WIDTH_AA:
    402 		/* NOTE: actual value is 127.0f, but this is working around a deqp
    403 		 * bug.. dEQP-GLES3.functional.rasterization.primitives.lines_wide
    404 		 * uses too small of a render target size, and gets confused when
    405 		 * the lines start going offscreen.
    406 		 *
    407 		 * See: https://code.google.com/p/android/issues/detail?id=206513
    408 		 */
    409 		if (fd_mesa_debug & FD_DBG_DEQP)
    410 			return 48.0f;
    411 		return 127.0f;
    412 	case PIPE_CAPF_MAX_POINT_WIDTH:
    413 	case PIPE_CAPF_MAX_POINT_WIDTH_AA:
    414 		return 4092.0f;
    415 	case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
    416 		return 16.0f;
    417 	case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
    418 		return 15.0f;
    419 	case PIPE_CAPF_GUARD_BAND_LEFT:
    420 	case PIPE_CAPF_GUARD_BAND_TOP:
    421 	case PIPE_CAPF_GUARD_BAND_RIGHT:
    422 	case PIPE_CAPF_GUARD_BAND_BOTTOM:
    423 		return 0.0f;
    424 	}
    425 	debug_printf("unknown paramf %d\n", param);
    426 	return 0;
    427 }
    428 
    429 static int
    430 fd_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
    431 		enum pipe_shader_cap param)
    432 {
    433 	struct fd_screen *screen = fd_screen(pscreen);
    434 
    435 	switch(shader)
    436 	{
    437 	case PIPE_SHADER_FRAGMENT:
    438 	case PIPE_SHADER_VERTEX:
    439 		break;
    440 	case PIPE_SHADER_COMPUTE:
    441 	case PIPE_SHADER_GEOMETRY:
    442 		/* maye we could emulate.. */
    443 		return 0;
    444 	default:
    445 		DBG("unknown shader type %d", shader);
    446 		return 0;
    447 	}
    448 
    449 	/* this is probably not totally correct.. but it's a start: */
    450 	switch (param) {
    451 	case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
    452 	case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
    453 	case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
    454 	case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
    455 		return 16384;
    456 	case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
    457 		return 8; /* XXX */
    458 	case PIPE_SHADER_CAP_MAX_INPUTS:
    459 	case PIPE_SHADER_CAP_MAX_OUTPUTS:
    460 		return 16;
    461 	case PIPE_SHADER_CAP_MAX_TEMPS:
    462 		return 64; /* Max native temporaries. */
    463 	case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
    464 		/* NOTE: seems to be limit for a3xx is actually 512 but
    465 		 * split between VS and FS.  Use lower limit of 256 to
    466 		 * avoid getting into impossible situations:
    467 		 */
    468 		return ((is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen)) ? 4096 : 64) * sizeof(float[4]);
    469 	case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
    470 		return is_ir3(screen) ? 16 : 1;
    471 	case PIPE_SHADER_CAP_MAX_PREDS:
    472 		return 0; /* nothing uses this */
    473 	case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
    474 		return 1;
    475 	case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
    476 	case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
    477 		/* Technically this should be the same as for TEMP/CONST, since
    478 		 * everything is just normal registers.  This is just temporary
    479 		 * hack until load_input/store_output handle arrays in a similar
    480 		 * way as load_var/store_var..
    481 		 */
    482 		return 0;
    483 	case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
    484 	case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
    485 		/* a2xx compiler doesn't handle indirect: */
    486 		return is_ir3(screen) ? 1 : 0;
    487 	case PIPE_SHADER_CAP_SUBROUTINES:
    488 	case PIPE_SHADER_CAP_DOUBLES:
    489 	case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
    490 	case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
    491 	case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
    492 	case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
    493 		return 0;
    494 	case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
    495 		return 1;
    496 	case PIPE_SHADER_CAP_INTEGERS:
    497 		if (glsl120)
    498 			return 0;
    499 		return is_ir3(screen) ? 1 : 0;
    500 	case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
    501 	case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
    502 		return 16;
    503 	case PIPE_SHADER_CAP_PREFERRED_IR:
    504 		if ((fd_mesa_debug & FD_DBG_NIR) && is_ir3(screen))
    505 			return PIPE_SHADER_IR_NIR;
    506 		return PIPE_SHADER_IR_TGSI;
    507 	case PIPE_SHADER_CAP_SUPPORTED_IRS:
    508 		return 0;
    509 	case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
    510 		return 32;
    511 	case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
    512 	case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
    513 	case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
    514 		return 0;
    515 	}
    516 	debug_printf("unknown shader param %d\n", param);
    517 	return 0;
    518 }
    519 
    520 static const void *
    521 fd_get_compiler_options(struct pipe_screen *pscreen,
    522 		enum pipe_shader_ir ir, unsigned shader)
    523 {
    524 	struct fd_screen *screen = fd_screen(pscreen);
    525 
    526 	if (is_ir3(screen))
    527 		return ir3_get_compiler_options();
    528 
    529 	return NULL;
    530 }
    531 
    532 boolean
    533 fd_screen_bo_get_handle(struct pipe_screen *pscreen,
    534 		struct fd_bo *bo,
    535 		unsigned stride,
    536 		struct winsys_handle *whandle)
    537 {
    538 	whandle->stride = stride;
    539 
    540 	if (whandle->type == DRM_API_HANDLE_TYPE_SHARED) {
    541 		return fd_bo_get_name(bo, &whandle->handle) == 0;
    542 	} else if (whandle->type == DRM_API_HANDLE_TYPE_KMS) {
    543 		whandle->handle = fd_bo_handle(bo);
    544 		return TRUE;
    545 	} else if (whandle->type == DRM_API_HANDLE_TYPE_FD) {
    546 		whandle->handle = fd_bo_dmabuf(bo);
    547 		return TRUE;
    548 	} else {
    549 		return FALSE;
    550 	}
    551 }
    552 
    553 struct fd_bo *
    554 fd_screen_bo_from_handle(struct pipe_screen *pscreen,
    555 		struct winsys_handle *whandle)
    556 {
    557 	struct fd_screen *screen = fd_screen(pscreen);
    558 	struct fd_bo *bo;
    559 
    560 	if (whandle->type == DRM_API_HANDLE_TYPE_SHARED) {
    561 		bo = fd_bo_from_name(screen->dev, whandle->handle);
    562 	} else if (whandle->type == DRM_API_HANDLE_TYPE_KMS) {
    563 		bo = fd_bo_from_handle(screen->dev, whandle->handle, 0);
    564 	} else if (whandle->type == DRM_API_HANDLE_TYPE_FD) {
    565 		bo = fd_bo_from_dmabuf(screen->dev, whandle->handle);
    566 	} else {
    567 		DBG("Attempt to import unsupported handle type %d", whandle->type);
    568 		return NULL;
    569 	}
    570 
    571 	if (!bo) {
    572 		DBG("ref name 0x%08x failed", whandle->handle);
    573 		return NULL;
    574 	}
    575 
    576 	return bo;
    577 }
    578 
    579 struct pipe_screen *
    580 fd_screen_create(struct fd_device *dev)
    581 {
    582 	struct fd_screen *screen = CALLOC_STRUCT(fd_screen);
    583 	struct pipe_screen *pscreen;
    584 	uint64_t val;
    585 
    586 	fd_mesa_debug = debug_get_option_fd_mesa_debug();
    587 
    588 	if (fd_mesa_debug & FD_DBG_NOBIN)
    589 		fd_binning_enabled = false;
    590 
    591 	glsl120 = !!(fd_mesa_debug & FD_DBG_GLSL120);
    592 
    593 	if (!screen)
    594 		return NULL;
    595 
    596 	pscreen = &screen->base;
    597 
    598 	screen->dev = dev;
    599 	screen->refcnt = 1;
    600 
    601 	// maybe this should be in context?
    602 	screen->pipe = fd_pipe_new(screen->dev, FD_PIPE_3D);
    603 	if (!screen->pipe) {
    604 		DBG("could not create 3d pipe");
    605 		goto fail;
    606 	}
    607 
    608 	if (fd_pipe_get_param(screen->pipe, FD_GMEM_SIZE, &val)) {
    609 		DBG("could not get GMEM size");
    610 		goto fail;
    611 	}
    612 	screen->gmemsize_bytes = val;
    613 
    614 	if (fd_pipe_get_param(screen->pipe, FD_DEVICE_ID, &val)) {
    615 		DBG("could not get device-id");
    616 		goto fail;
    617 	}
    618 	screen->device_id = val;
    619 
    620 	if (fd_pipe_get_param(screen->pipe, FD_MAX_FREQ, &val)) {
    621 		DBG("could not get gpu freq");
    622 		/* this limits what performance related queries are
    623 		 * supported but is not fatal
    624 		 */
    625 		screen->max_freq = 0;
    626 	} else {
    627 		screen->max_freq = val;
    628 		if (fd_pipe_get_param(screen->pipe, FD_TIMESTAMP, &val) == 0)
    629 			screen->has_timestamp = true;
    630 	}
    631 
    632 	if (fd_pipe_get_param(screen->pipe, FD_GPU_ID, &val)) {
    633 		DBG("could not get gpu-id");
    634 		goto fail;
    635 	}
    636 	screen->gpu_id = val;
    637 
    638 	if (fd_pipe_get_param(screen->pipe, FD_CHIP_ID, &val)) {
    639 		DBG("could not get chip-id");
    640 		/* older kernels may not have this property: */
    641 		unsigned core  = screen->gpu_id / 100;
    642 		unsigned major = (screen->gpu_id % 100) / 10;
    643 		unsigned minor = screen->gpu_id % 10;
    644 		unsigned patch = 0;  /* assume the worst */
    645 		val = (patch & 0xff) | ((minor & 0xff) << 8) |
    646 			((major & 0xff) << 16) | ((core & 0xff) << 24);
    647 	}
    648 	screen->chip_id = val;
    649 
    650 	DBG("Pipe Info:");
    651 	DBG(" GPU-id:          %d", screen->gpu_id);
    652 	DBG(" Chip-id:         0x%08x", screen->chip_id);
    653 	DBG(" GMEM size:       0x%08x", screen->gmemsize_bytes);
    654 
    655 	/* explicitly checking for GPU revisions that are known to work.  This
    656 	 * may be overly conservative for a3xx, where spoofing the gpu_id with
    657 	 * the blob driver seems to generate identical cmdstream dumps.  But
    658 	 * on a2xx, there seem to be small differences between the GPU revs
    659 	 * so it is probably better to actually test first on real hardware
    660 	 * before enabling:
    661 	 *
    662 	 * If you have a different adreno version, feel free to add it to one
    663 	 * of the cases below and see what happens.  And if it works, please
    664 	 * send a patch ;-)
    665 	 */
    666 	switch (screen->gpu_id) {
    667 	case 220:
    668 		fd2_screen_init(pscreen);
    669 		break;
    670 	case 305:
    671 	case 307:
    672 	case 320:
    673 	case 330:
    674 		fd3_screen_init(pscreen);
    675 		break;
    676 	case 420:
    677 	case 430:
    678 		fd4_screen_init(pscreen);
    679 		break;
    680 	case 530:
    681 		fd5_screen_init(pscreen);
    682 		break;
    683 	default:
    684 		debug_printf("unsupported GPU: a%03d\n", screen->gpu_id);
    685 		goto fail;
    686 	}
    687 
    688 	if (screen->gpu_id >= 500) {
    689 		screen->gmem_alignw = 64;
    690 		screen->gmem_alignh = 32;
    691 	} else {
    692 		screen->gmem_alignw = 32;
    693 		screen->gmem_alignh = 32;
    694 	}
    695 
    696 	/* NOTE: don't enable reordering on a2xx, since completely untested.
    697 	 * Also, don't enable if we have too old of a kernel to support
    698 	 * growable cmdstream buffers, since memory requirement for cmdstream
    699 	 * buffers would be too much otherwise.
    700 	 */
    701 	if ((screen->gpu_id >= 300) && (fd_device_version(dev) >= FD_VERSION_UNLIMITED_CMDS))
    702 		screen->reorder = !!(fd_mesa_debug & FD_DBG_REORDER);
    703 
    704 	fd_bc_init(&screen->batch_cache);
    705 
    706 	pipe_mutex_init(screen->lock);
    707 
    708 	pscreen->destroy = fd_screen_destroy;
    709 	pscreen->get_param = fd_screen_get_param;
    710 	pscreen->get_paramf = fd_screen_get_paramf;
    711 	pscreen->get_shader_param = fd_screen_get_shader_param;
    712 	pscreen->get_compiler_options = fd_get_compiler_options;
    713 
    714 	fd_resource_screen_init(pscreen);
    715 	fd_query_screen_init(pscreen);
    716 
    717 	pscreen->get_name = fd_screen_get_name;
    718 	pscreen->get_vendor = fd_screen_get_vendor;
    719 	pscreen->get_device_vendor = fd_screen_get_device_vendor;
    720 
    721 	pscreen->get_timestamp = fd_screen_get_timestamp;
    722 
    723 	pscreen->fence_reference = fd_fence_ref;
    724 	pscreen->fence_finish = fd_fence_finish;
    725 	pscreen->fence_get_fd = fd_fence_get_fd;
    726 
    727 	slab_create_parent(&screen->transfer_pool, sizeof(struct fd_transfer), 16);
    728 
    729 	util_format_s3tc_init();
    730 
    731 	return pscreen;
    732 
    733 fail:
    734 	fd_screen_destroy(pscreen);
    735 	return NULL;
    736 }
    737