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  /device/linaro/bootloader/arm-trusted-firmware/lib/psci/
psci_off.c 22 unsigned int lvl; local
24 for (lvl = PSCI_CPU_PWR_LVL; lvl <= PLAT_MAX_PWR_LVL; lvl++)
25 state_info->pwr_domain_state[lvl] = PLAT_MAX_OFF_STATE;
psci_stat.c 75 unsigned int lvl, parent_idx, cpu_idx = plat_my_core_pos(); local
82 for (lvl = PSCI_CPU_PWR_LVL + 1; lvl <= end_pwrlvl; lvl++) {
85 if (is_local_state_run(state_info->pwr_domain_state[lvl]))
107 unsigned int lvl, parent_idx, cpu_idx = plat_my_core_pos(); local
132 for (lvl = PSCI_CPU_PWR_LVL + 1; lvl <= end_pwrlvl; lvl++) {
133 local_state = state_info->pwr_domain_state[lvl];
169 unsigned int pwrlvl, lvl, parent_idx, stat_idx, target_idx; local
    [all...]
psci_common.c 287 unsigned int parent_idx, lvl; local
294 for (lvl = PSCI_CPU_PWR_LVL + 1; lvl <= end_pwrlvl; lvl++) {
295 pd_state[lvl] = get_non_cpu_pd_node_local_state(parent_idx);
300 for (; lvl <= PLAT_MAX_PWR_LVL; lvl++)
301 target_state->pwr_domain_state[lvl] = PSCI_LOCAL_STATE_RUN;
313 unsigned int parent_idx, lvl; local
327 for (lvl = 1; lvl <= end_pwrlvl; lvl++)
357 unsigned int parent_idx, cpu_idx = plat_my_core_pos(), lvl; local
400 unsigned int lvl, parent_idx, cpu_idx = plat_my_core_pos(); local
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  /external/ltp/testcases/kernel/io/disktest/
sfunc.h 109 typedef enum lvl { enum
  /external/libvpx/libvpx/vp8/common/
loopfilter.h 46 unsigned char lvl[4][4][4]; member in struct:__anon26118
  /external/mesa3d/src/gallium/drivers/freedreno/a3xx/
fd3_texture.c 219 unsigned lvl; local
243 lvl = 0;
251 lvl = fd_sampler_first_level(cso);
252 miplevels = fd_sampler_last_level(cso) - lvl;
257 A3XX_TEX_CONST_1_WIDTH(u_minify(prsc->width0, lvl)) |
258 A3XX_TEX_CONST_1_HEIGHT(u_minify(prsc->height0, lvl));
262 A3XX_TEX_CONST_2_PITCH(fd3_pipe2nblocksx(cso->format, rsc->slices[lvl].pitch) * rsc->cpp);
272 A3XX_TEX_CONST_3_DEPTH(u_minify(prsc->depth0, lvl)) |
273 A3XX_TEX_CONST_3_LAYERSZ1(rsc->slices[lvl].size0);
274 while (lvl < cso->u.tex.last_level && sz2 != rsc->slices[lvl+1].size0
    [all...]
fd3_emit.c 315 unsigned lvl = psurf[i]->u.tex.level; local
316 struct fd_resource_slice *slice = fd_resource_slice(rsc, lvl);
346 unsigned lvl = psurf[i]->u.tex.level; local
347 uint32_t offset = fd_resource_offset(rsc, lvl, psurf[i]->u.tex.first_layer);
    [all...]
  /external/mesa3d/src/gallium/drivers/freedreno/a4xx/
fd4_texture.c 227 unsigned lvl, layers; local
254 lvl = 0;
265 lvl = fd_sampler_first_level(cso);
266 miplevels = fd_sampler_last_level(cso) - lvl;
271 A4XX_TEX_CONST_1_WIDTH(u_minify(prsc->width0, lvl)) |
272 A4XX_TEX_CONST_1_HEIGHT(u_minify(prsc->height0, lvl));
277 cso->format, rsc->slices[lvl].pitch) * rsc->cpp);
278 so->offset = fd_resource_offset(rsc, lvl, cso->u.tex.first_layer);
296 A4XX_TEX_CONST_3_DEPTH(u_minify(prsc->depth0, lvl)) |
297 A4XX_TEX_CONST_3_LAYERSZ(rsc->slices[lvl].size0)
    [all...]
fd4_emit.c 308 unsigned lvl = bufs[i]->u.tex.level; local
309 struct fd_resource_slice *slice = fd_resource_slice(rsc, lvl);
310 unsigned offset = fd_resource_offset(rsc, lvl, bufs[i]->u.tex.first_layer);
  /external/mesa3d/src/gallium/drivers/freedreno/a5xx/
fd5_texture.c 225 unsigned lvl, layers; local
251 lvl = 0;
262 lvl = fd_sampler_first_level(cso);
263 miplevels = fd_sampler_last_level(cso) - lvl;
268 A5XX_TEX_CONST_1_WIDTH(u_minify(prsc->width0, lvl)) |
269 A5XX_TEX_CONST_1_HEIGHT(u_minify(prsc->height0, lvl));
274 cso->format, rsc->slices[lvl].pitch) * rsc->cpp);
275 so->offset = fd_resource_offset(rsc, lvl, cso->u.tex.first_layer);
303 while (lvl < cso->u.tex.last_level && sz2 != rsc->slices[lvl+1].size0
    [all...]
  /external/mesa3d/src/mesa/main/
texcompress_cpal.c 113 int lvl; local
125 for (lvl = 0; lvl < num_levels; lvl++) {
126 w = width >> lvl;
129 h = height >> lvl;
154 GLint lvl, num_levels; local
174 for (lvl = 0; lvl < num_levels; lvl++)
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  /dalvik/dx/src/com/android/dx/cf/code/
ConcreteMethod.java 93 LocalVariableList lvl = LocalVariableList.EMPTY; local
107 lvl = LocalVariableList.concat(lvl, lvt.getLocalVariables());
121 lvl = LocalVariableList.mergeDescriptorsAndSignatures(lvl, typeList);
124 this.localVariables = lvl;
  /device/linaro/bootloader/arm-trusted-firmware/plat/arm/css/drivers/scp/
css_pm_scmi.c 48 #define SCMI_SET_PWR_STATE_LVL(pwr_state, lvl, lvl_state) \
50 << (SCMI_PWR_STATE_LVL_WIDTH * (lvl))
51 #define SCMI_GET_PWR_STATE_LVL(pwr_state, lvl) \
52 (((pwr_state) >> (SCMI_PWR_STATE_LVL_WIDTH * (lvl))) & \
87 int lvl, ret; local
119 for (lvl = ARM_PWR_LVL1; lvl <= PLAT_MAX_PWR_LVL; lvl++) {
120 if (target_state->pwr_domain_state[lvl] == ARM_LOCAL_STATE_RUN)
123 assert(target_state->pwr_domain_state[lvl] =
152 int lvl = 0, ret; local
192 int lvl = 0, ret, core_pos; local
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  /device/linaro/bootloader/arm-trusted-firmware/plat/rockchip/common/
plat_pm.c 48 int rockchip_soc_hlvl_pwr_dm_off(uint32_t lvl,
69 int rockchip_soc_hlvl_pwr_dm_suspend(uint32_t lvl,
75 int rockchip_soc_hlvl_pwr_dm_on_finish(uint32_t lvl,
91 int rockchip_soc_hlvl_pwr_dm_resume(uint32_t lvl,
215 uint32_t lvl; local
228 for (lvl = MPIDR_AFFLVL1; lvl <= PLAT_MAX_PWR_LVL; lvl++) {
229 lvl_state = target_state->pwr_domain_state[lvl];
230 ret = rockchip_soc_hlvl_pwr_dm_off(lvl, lvl_state)
242 uint32_t lvl; local
279 uint32_t lvl; local
316 uint32_t lvl; local
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  /external/libxkbcommon/xkbcommon/src/
context.c 204 enum xkb_log_level lvl; local
207 lvl = strtol(level, &endptr, 10);
209 return lvl;
  /external/mesa3d/src/gallium/drivers/nouveau/nvc0/
nvc0_miptree.c 207 struct nv50_miptree_level *lvl = &mt->level[l]; local
212 lvl->offset = mt->total_size;
214 lvl->tile_mode = nvc0_tex_choose_tile_dims(nbx, nby, d, mt->layout_3d);
216 tsx = NVC0_TILE_SIZE_X(lvl->tile_mode); /* x is tile row pitch in bytes */
217 tsy = NVC0_TILE_SIZE_Y(lvl->tile_mode);
218 tsz = NVC0_TILE_SIZE_Z(lvl->tile_mode);
220 lvl->pitch = align(nbx * blocksize, tsx);
222 mt->total_size += lvl->pitch * align(nby, tsy) * align(d, tsz);
nvc0_tex.c 908 struct nv50_miptree_level *lvl = &mt->level[view->u.tex.level]; local
924 address += lvl->offset;
930 info[3] = (0x88 << 24) | (lvl->pitch / 64);
932 info[4] |= (lvl->tile_mode & 0x0f0) << 25;
933 info[4] |= NVC0_TILE_SHIFT_Y(lvl->tile_mode) << 22;
936 info[6] |= (lvl->tile_mode & 0xf00) << 21;
937 info[6] |= NVC0_TILE_SHIFT_Z(lvl->tile_mode) << 22;
1033 struct nv50_miptree_level *lvl = &mt->level[view->u.tex.level] local
    [all...]
  /external/mesa3d/src/mesa/drivers/dri/radeon/
radeon_state_init.c 425 radeon_mipmap_level *lvl; local
446 lvl = &t->mt->levels[0];
449 OUT_BATCH_RELOC(lvl->faces[j].offset, t->mt->bo, lvl->faces[j].offset,
462 radeon_mipmap_level *lvl; local
486 lvl = &t->mt->levels[t->minLod];
487 OUT_BATCH_RELOC(lvl->faces[5].offset, t->mt->bo, lvl->faces[5].offset,
    [all...]
radeon_mipmap_tree.c 129 radeon_mipmap_level *lvl = &mt->levels[level]; local
132 height = _mesa_next_pow_two_32(lvl->height);
134 lvl->rowstride = get_texture_image_row_stride(rmesa, mt->mesaFormat, lvl->width, mt->tilebits, mt->target);
135 lvl->size = get_texture_image_size(mt->mesaFormat, lvl->rowstride, height, lvl->depth, mt->tilebits);
137 assert(lvl->size > 0);
139 lvl->faces[face].offset = *curOffset;
140 *curOffset += lvl->size
293 radeon_mipmap_level *lvl; local
    [all...]
radeon_texture.c 184 radeon_mipmap_level *lvl = &image->mt->levels[texImage->Level]; local
187 base = mt->bo->ptr + lvl->faces[image->base.Base.Face].offset;
189 *stride = lvl->rowstride;
  /external/libvpx/libvpx/vp9/common/
vp9_loopfilter.h 48 uint8_t lvl[MAX_SEGMENTS][MAX_REF_FRAMES][MAX_MODE_LF_DELTAS]; member in struct:__anon26180
  /external/mesa3d/src/gallium/drivers/nouveau/nv30/
nv30_miptree.c 41 struct nv30_miptree_level *lvl = &mt->level[level]; local
44 return (layer * mt->layer_size) + lvl->offset;
46 return lvl->offset + (layer * lvl->zslice_size);
94 struct nv30_miptree_level *lvl = &mt->level[level]; local
109 rect->pitch = lvl->pitch;
426 struct nv30_miptree_level *lvl = &mt->level[l]; local
430 lvl->offset = size;
431 lvl->pitch = mt->uniform_pitch;
432 if (!lvl->pitch
506 struct nv30_miptree_level *lvl = &mt->level[tmpl->u.tex.level]; local
    [all...]
  /external/mesa3d/src/gallium/drivers/nouveau/nv50/
nv50_miptree.c 304 struct nv50_miptree_level *lvl = &mt->level[l]; local
309 lvl->offset = mt->total_size;
311 lvl->tile_mode = nv50_tex_choose_tile_dims(nbx, nby, d, mt->layout_3d);
313 tsx = NV50_TILE_SIZE_X(lvl->tile_mode); /* x is tile row pitch in bytes */
314 tsy = NV50_TILE_SIZE_Y(lvl->tile_mode);
315 tsz = NV50_TILE_SIZE_Z(lvl->tile_mode);
317 lvl->pitch = align(nbx * blocksize, tsx);
319 mt->total_size += lvl->pitch * align(nby, tsy) * align(d, tsz);
  /external/mesa3d/src/mesa/drivers/dri/r200/
r200_state_init.c 600 radeon_mipmap_level *lvl; local
608 lvl = &t->mt->levels[0];
611 OUT_BATCH_RELOC(lvl->faces[j].offset, t->mt->bo, lvl->faces[j].offset,
    [all...]
  /external/apache-http/src/org/apache/commons/logging/impl/
SimpleLog.java 214 String lvl = getStringProperty(systemPrefix + "log." + logName); local
216 while(null == lvl && i > -1) {
218 lvl = getStringProperty(systemPrefix + "log." + name);
222 if(null == lvl) {
223 lvl = getStringProperty(systemPrefix + "defaultlog");
226 if("all".equalsIgnoreCase(lvl)) {
228 } else if("trace".equalsIgnoreCase(lvl)) {
230 } else if("debug".equalsIgnoreCase(lvl)) {
232 } else if("info".equalsIgnoreCase(lvl)) {
234 } else if("warn".equalsIgnoreCase(lvl)) {
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