1 /* BFD back-end for Renesas Super-H COFF binaries. 2 Copyright (C) 1993-2016 Free Software Foundation, Inc. 3 Contributed by Cygnus Support. 4 Written by Steve Chamberlain, <sac (at) cygnus.com>. 5 Relaxing code written by Ian Lance Taylor, <ian (at) cygnus.com>. 6 7 This file is part of BFD, the Binary File Descriptor library. 8 9 This program is free software; you can redistribute it and/or modify 10 it under the terms of the GNU General Public License as published by 11 the Free Software Foundation; either version 3 of the License, or 12 (at your option) any later version. 13 14 This program is distributed in the hope that it will be useful, 15 but WITHOUT ANY WARRANTY; without even the implied warranty of 16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 GNU General Public License for more details. 18 19 You should have received a copy of the GNU General Public License 20 along with this program; if not, write to the Free Software 21 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, 22 MA 02110-1301, USA. */ 23 24 #include "sysdep.h" 25 #include "bfd.h" 26 #include "libiberty.h" 27 #include "libbfd.h" 28 #include "bfdlink.h" 29 #include "coff/sh.h" 30 #include "coff/internal.h" 31 32 #undef bfd_pe_print_pdata 33 34 #ifdef COFF_WITH_PE 35 #include "coff/pe.h" 36 37 #ifndef COFF_IMAGE_WITH_PE 38 static bfd_boolean sh_align_load_span 39 (bfd *, asection *, bfd_byte *, 40 bfd_boolean (*) (bfd *, asection *, void *, bfd_byte *, bfd_vma), 41 void *, bfd_vma **, bfd_vma *, bfd_vma, bfd_vma, bfd_boolean *); 42 43 #define _bfd_sh_align_load_span sh_align_load_span 44 #endif 45 46 #define bfd_pe_print_pdata _bfd_pe_print_ce_compressed_pdata 47 48 #else 49 50 #define bfd_pe_print_pdata NULL 51 52 #endif /* COFF_WITH_PE. */ 53 54 #include "libcoff.h" 55 56 /* Internal functions. */ 57 58 #ifdef COFF_WITH_PE 59 /* Can't build import tables with 2**4 alignment. */ 60 #define COFF_DEFAULT_SECTION_ALIGNMENT_POWER 2 61 #else 62 /* Default section alignment to 2**4. */ 63 #define COFF_DEFAULT_SECTION_ALIGNMENT_POWER 4 64 #endif 65 66 #ifdef COFF_IMAGE_WITH_PE 67 /* Align PE executables. */ 68 #define COFF_PAGE_SIZE 0x1000 69 #endif 70 71 /* Generate long file names. */ 72 #define COFF_LONG_FILENAMES 73 74 #ifdef COFF_WITH_PE 75 /* Return TRUE if this relocation should 76 appear in the output .reloc section. */ 77 78 static bfd_boolean 79 in_reloc_p (bfd * abfd ATTRIBUTE_UNUSED, 80 reloc_howto_type * howto) 81 { 82 return ! howto->pc_relative && howto->type != R_SH_IMAGEBASE; 83 } 84 #endif 85 86 static bfd_reloc_status_type 87 sh_reloc (bfd *, arelent *, asymbol *, void *, asection *, bfd *, char **); 88 static bfd_boolean 89 sh_relocate_section (bfd *, struct bfd_link_info *, bfd *, asection *, 90 bfd_byte *, struct internal_reloc *, 91 struct internal_syment *, asection **); 92 static bfd_boolean 93 sh_align_loads (bfd *, asection *, struct internal_reloc *, 94 bfd_byte *, bfd_boolean *); 95 96 /* The supported relocations. There are a lot of relocations defined 97 in coff/internal.h which we do not expect to ever see. */ 98 static reloc_howto_type sh_coff_howtos[] = 99 { 100 EMPTY_HOWTO (0), 101 EMPTY_HOWTO (1), 102 #ifdef COFF_WITH_PE 103 /* Windows CE */ 104 HOWTO (R_SH_IMM32CE, /* type */ 105 0, /* rightshift */ 106 2, /* size (0 = byte, 1 = short, 2 = long) */ 107 32, /* bitsize */ 108 FALSE, /* pc_relative */ 109 0, /* bitpos */ 110 complain_overflow_bitfield, /* complain_on_overflow */ 111 sh_reloc, /* special_function */ 112 "r_imm32ce", /* name */ 113 TRUE, /* partial_inplace */ 114 0xffffffff, /* src_mask */ 115 0xffffffff, /* dst_mask */ 116 FALSE), /* pcrel_offset */ 117 #else 118 EMPTY_HOWTO (2), 119 #endif 120 EMPTY_HOWTO (3), /* R_SH_PCREL8 */ 121 EMPTY_HOWTO (4), /* R_SH_PCREL16 */ 122 EMPTY_HOWTO (5), /* R_SH_HIGH8 */ 123 EMPTY_HOWTO (6), /* R_SH_IMM24 */ 124 EMPTY_HOWTO (7), /* R_SH_LOW16 */ 125 EMPTY_HOWTO (8), 126 EMPTY_HOWTO (9), /* R_SH_PCDISP8BY4 */ 127 128 HOWTO (R_SH_PCDISP8BY2, /* type */ 129 1, /* rightshift */ 130 1, /* size (0 = byte, 1 = short, 2 = long) */ 131 8, /* bitsize */ 132 TRUE, /* pc_relative */ 133 0, /* bitpos */ 134 complain_overflow_signed, /* complain_on_overflow */ 135 sh_reloc, /* special_function */ 136 "r_pcdisp8by2", /* name */ 137 TRUE, /* partial_inplace */ 138 0xff, /* src_mask */ 139 0xff, /* dst_mask */ 140 TRUE), /* pcrel_offset */ 141 142 EMPTY_HOWTO (11), /* R_SH_PCDISP8 */ 143 144 HOWTO (R_SH_PCDISP, /* type */ 145 1, /* rightshift */ 146 1, /* size (0 = byte, 1 = short, 2 = long) */ 147 12, /* bitsize */ 148 TRUE, /* pc_relative */ 149 0, /* bitpos */ 150 complain_overflow_signed, /* complain_on_overflow */ 151 sh_reloc, /* special_function */ 152 "r_pcdisp12by2", /* name */ 153 TRUE, /* partial_inplace */ 154 0xfff, /* src_mask */ 155 0xfff, /* dst_mask */ 156 TRUE), /* pcrel_offset */ 157 158 EMPTY_HOWTO (13), 159 160 HOWTO (R_SH_IMM32, /* type */ 161 0, /* rightshift */ 162 2, /* size (0 = byte, 1 = short, 2 = long) */ 163 32, /* bitsize */ 164 FALSE, /* pc_relative */ 165 0, /* bitpos */ 166 complain_overflow_bitfield, /* complain_on_overflow */ 167 sh_reloc, /* special_function */ 168 "r_imm32", /* name */ 169 TRUE, /* partial_inplace */ 170 0xffffffff, /* src_mask */ 171 0xffffffff, /* dst_mask */ 172 FALSE), /* pcrel_offset */ 173 174 EMPTY_HOWTO (15), 175 #ifdef COFF_WITH_PE 176 HOWTO (R_SH_IMAGEBASE, /* type */ 177 0, /* rightshift */ 178 2, /* size (0 = byte, 1 = short, 2 = long) */ 179 32, /* bitsize */ 180 FALSE, /* pc_relative */ 181 0, /* bitpos */ 182 complain_overflow_bitfield, /* complain_on_overflow */ 183 sh_reloc, /* special_function */ 184 "rva32", /* name */ 185 TRUE, /* partial_inplace */ 186 0xffffffff, /* src_mask */ 187 0xffffffff, /* dst_mask */ 188 FALSE), /* pcrel_offset */ 189 #else 190 EMPTY_HOWTO (16), /* R_SH_IMM8 */ 191 #endif 192 EMPTY_HOWTO (17), /* R_SH_IMM8BY2 */ 193 EMPTY_HOWTO (18), /* R_SH_IMM8BY4 */ 194 EMPTY_HOWTO (19), /* R_SH_IMM4 */ 195 EMPTY_HOWTO (20), /* R_SH_IMM4BY2 */ 196 EMPTY_HOWTO (21), /* R_SH_IMM4BY4 */ 197 198 HOWTO (R_SH_PCRELIMM8BY2, /* type */ 199 1, /* rightshift */ 200 1, /* size (0 = byte, 1 = short, 2 = long) */ 201 8, /* bitsize */ 202 TRUE, /* pc_relative */ 203 0, /* bitpos */ 204 complain_overflow_unsigned, /* complain_on_overflow */ 205 sh_reloc, /* special_function */ 206 "r_pcrelimm8by2", /* name */ 207 TRUE, /* partial_inplace */ 208 0xff, /* src_mask */ 209 0xff, /* dst_mask */ 210 TRUE), /* pcrel_offset */ 211 212 HOWTO (R_SH_PCRELIMM8BY4, /* type */ 213 2, /* rightshift */ 214 1, /* size (0 = byte, 1 = short, 2 = long) */ 215 8, /* bitsize */ 216 TRUE, /* pc_relative */ 217 0, /* bitpos */ 218 complain_overflow_unsigned, /* complain_on_overflow */ 219 sh_reloc, /* special_function */ 220 "r_pcrelimm8by4", /* name */ 221 TRUE, /* partial_inplace */ 222 0xff, /* src_mask */ 223 0xff, /* dst_mask */ 224 TRUE), /* pcrel_offset */ 225 226 HOWTO (R_SH_IMM16, /* type */ 227 0, /* rightshift */ 228 1, /* size (0 = byte, 1 = short, 2 = long) */ 229 16, /* bitsize */ 230 FALSE, /* pc_relative */ 231 0, /* bitpos */ 232 complain_overflow_bitfield, /* complain_on_overflow */ 233 sh_reloc, /* special_function */ 234 "r_imm16", /* name */ 235 TRUE, /* partial_inplace */ 236 0xffff, /* src_mask */ 237 0xffff, /* dst_mask */ 238 FALSE), /* pcrel_offset */ 239 240 HOWTO (R_SH_SWITCH16, /* type */ 241 0, /* rightshift */ 242 1, /* size (0 = byte, 1 = short, 2 = long) */ 243 16, /* bitsize */ 244 FALSE, /* pc_relative */ 245 0, /* bitpos */ 246 complain_overflow_bitfield, /* complain_on_overflow */ 247 sh_reloc, /* special_function */ 248 "r_switch16", /* name */ 249 TRUE, /* partial_inplace */ 250 0xffff, /* src_mask */ 251 0xffff, /* dst_mask */ 252 FALSE), /* pcrel_offset */ 253 254 HOWTO (R_SH_SWITCH32, /* type */ 255 0, /* rightshift */ 256 2, /* size (0 = byte, 1 = short, 2 = long) */ 257 32, /* bitsize */ 258 FALSE, /* pc_relative */ 259 0, /* bitpos */ 260 complain_overflow_bitfield, /* complain_on_overflow */ 261 sh_reloc, /* special_function */ 262 "r_switch32", /* name */ 263 TRUE, /* partial_inplace */ 264 0xffffffff, /* src_mask */ 265 0xffffffff, /* dst_mask */ 266 FALSE), /* pcrel_offset */ 267 268 HOWTO (R_SH_USES, /* type */ 269 0, /* rightshift */ 270 1, /* size (0 = byte, 1 = short, 2 = long) */ 271 16, /* bitsize */ 272 FALSE, /* pc_relative */ 273 0, /* bitpos */ 274 complain_overflow_bitfield, /* complain_on_overflow */ 275 sh_reloc, /* special_function */ 276 "r_uses", /* name */ 277 TRUE, /* partial_inplace */ 278 0xffff, /* src_mask */ 279 0xffff, /* dst_mask */ 280 FALSE), /* pcrel_offset */ 281 282 HOWTO (R_SH_COUNT, /* type */ 283 0, /* rightshift */ 284 2, /* size (0 = byte, 1 = short, 2 = long) */ 285 32, /* bitsize */ 286 FALSE, /* pc_relative */ 287 0, /* bitpos */ 288 complain_overflow_bitfield, /* complain_on_overflow */ 289 sh_reloc, /* special_function */ 290 "r_count", /* name */ 291 TRUE, /* partial_inplace */ 292 0xffffffff, /* src_mask */ 293 0xffffffff, /* dst_mask */ 294 FALSE), /* pcrel_offset */ 295 296 HOWTO (R_SH_ALIGN, /* type */ 297 0, /* rightshift */ 298 2, /* size (0 = byte, 1 = short, 2 = long) */ 299 32, /* bitsize */ 300 FALSE, /* pc_relative */ 301 0, /* bitpos */ 302 complain_overflow_bitfield, /* complain_on_overflow */ 303 sh_reloc, /* special_function */ 304 "r_align", /* name */ 305 TRUE, /* partial_inplace */ 306 0xffffffff, /* src_mask */ 307 0xffffffff, /* dst_mask */ 308 FALSE), /* pcrel_offset */ 309 310 HOWTO (R_SH_CODE, /* type */ 311 0, /* rightshift */ 312 2, /* size (0 = byte, 1 = short, 2 = long) */ 313 32, /* bitsize */ 314 FALSE, /* pc_relative */ 315 0, /* bitpos */ 316 complain_overflow_bitfield, /* complain_on_overflow */ 317 sh_reloc, /* special_function */ 318 "r_code", /* name */ 319 TRUE, /* partial_inplace */ 320 0xffffffff, /* src_mask */ 321 0xffffffff, /* dst_mask */ 322 FALSE), /* pcrel_offset */ 323 324 HOWTO (R_SH_DATA, /* type */ 325 0, /* rightshift */ 326 2, /* size (0 = byte, 1 = short, 2 = long) */ 327 32, /* bitsize */ 328 FALSE, /* pc_relative */ 329 0, /* bitpos */ 330 complain_overflow_bitfield, /* complain_on_overflow */ 331 sh_reloc, /* special_function */ 332 "r_data", /* name */ 333 TRUE, /* partial_inplace */ 334 0xffffffff, /* src_mask */ 335 0xffffffff, /* dst_mask */ 336 FALSE), /* pcrel_offset */ 337 338 HOWTO (R_SH_LABEL, /* type */ 339 0, /* rightshift */ 340 2, /* size (0 = byte, 1 = short, 2 = long) */ 341 32, /* bitsize */ 342 FALSE, /* pc_relative */ 343 0, /* bitpos */ 344 complain_overflow_bitfield, /* complain_on_overflow */ 345 sh_reloc, /* special_function */ 346 "r_label", /* name */ 347 TRUE, /* partial_inplace */ 348 0xffffffff, /* src_mask */ 349 0xffffffff, /* dst_mask */ 350 FALSE), /* pcrel_offset */ 351 352 HOWTO (R_SH_SWITCH8, /* type */ 353 0, /* rightshift */ 354 0, /* size (0 = byte, 1 = short, 2 = long) */ 355 8, /* bitsize */ 356 FALSE, /* pc_relative */ 357 0, /* bitpos */ 358 complain_overflow_bitfield, /* complain_on_overflow */ 359 sh_reloc, /* special_function */ 360 "r_switch8", /* name */ 361 TRUE, /* partial_inplace */ 362 0xff, /* src_mask */ 363 0xff, /* dst_mask */ 364 FALSE) /* pcrel_offset */ 365 }; 366 367 #define SH_COFF_HOWTO_COUNT (sizeof sh_coff_howtos / sizeof sh_coff_howtos[0]) 368 369 /* Check for a bad magic number. */ 370 #define BADMAG(x) SHBADMAG(x) 371 372 /* Customize coffcode.h (this is not currently used). */ 373 #define SH 1 374 375 /* FIXME: This should not be set here. */ 376 #define __A_MAGIC_SET__ 377 378 #ifndef COFF_WITH_PE 379 /* Swap the r_offset field in and out. */ 380 #define SWAP_IN_RELOC_OFFSET H_GET_32 381 #define SWAP_OUT_RELOC_OFFSET H_PUT_32 382 383 /* Swap out extra information in the reloc structure. */ 384 #define SWAP_OUT_RELOC_EXTRA(abfd, src, dst) \ 385 do \ 386 { \ 387 dst->r_stuff[0] = 'S'; \ 388 dst->r_stuff[1] = 'C'; \ 389 } \ 390 while (0) 391 #endif 392 393 /* Get the value of a symbol, when performing a relocation. */ 394 395 static long 396 get_symbol_value (asymbol *symbol) 397 { 398 bfd_vma relocation; 399 400 if (bfd_is_com_section (symbol->section)) 401 relocation = 0; 402 else 403 relocation = (symbol->value + 404 symbol->section->output_section->vma + 405 symbol->section->output_offset); 406 407 return relocation; 408 } 409 410 #ifdef COFF_WITH_PE 411 /* Convert an rtype to howto for the COFF backend linker. 412 Copied from coff-i386. */ 413 #define coff_rtype_to_howto coff_sh_rtype_to_howto 414 415 416 static reloc_howto_type * 417 coff_sh_rtype_to_howto (bfd * abfd ATTRIBUTE_UNUSED, 418 asection * sec, 419 struct internal_reloc * rel, 420 struct coff_link_hash_entry * h, 421 struct internal_syment * sym, 422 bfd_vma * addendp) 423 { 424 reloc_howto_type * howto; 425 426 howto = sh_coff_howtos + rel->r_type; 427 428 *addendp = 0; 429 430 if (howto->pc_relative) 431 *addendp += sec->vma; 432 433 if (sym != NULL && sym->n_scnum == 0 && sym->n_value != 0) 434 { 435 /* This is a common symbol. The section contents include the 436 size (sym->n_value) as an addend. The relocate_section 437 function will be adding in the final value of the symbol. We 438 need to subtract out the current size in order to get the 439 correct result. */ 440 BFD_ASSERT (h != NULL); 441 } 442 443 if (howto->pc_relative) 444 { 445 *addendp -= 4; 446 447 /* If the symbol is defined, then the generic code is going to 448 add back the symbol value in order to cancel out an 449 adjustment it made to the addend. However, we set the addend 450 to 0 at the start of this function. We need to adjust here, 451 to avoid the adjustment the generic code will make. FIXME: 452 This is getting a bit hackish. */ 453 if (sym != NULL && sym->n_scnum != 0) 454 *addendp -= sym->n_value; 455 } 456 457 if (rel->r_type == R_SH_IMAGEBASE) 458 *addendp -= pe_data (sec->output_section->owner)->pe_opthdr.ImageBase; 459 460 return howto; 461 } 462 463 #endif /* COFF_WITH_PE */ 464 465 /* This structure is used to map BFD reloc codes to SH PE relocs. */ 466 struct shcoff_reloc_map 467 { 468 bfd_reloc_code_real_type bfd_reloc_val; 469 unsigned char shcoff_reloc_val; 470 }; 471 472 #ifdef COFF_WITH_PE 473 /* An array mapping BFD reloc codes to SH PE relocs. */ 474 static const struct shcoff_reloc_map sh_reloc_map[] = 475 { 476 { BFD_RELOC_32, R_SH_IMM32CE }, 477 { BFD_RELOC_RVA, R_SH_IMAGEBASE }, 478 { BFD_RELOC_CTOR, R_SH_IMM32CE }, 479 }; 480 #else 481 /* An array mapping BFD reloc codes to SH PE relocs. */ 482 static const struct shcoff_reloc_map sh_reloc_map[] = 483 { 484 { BFD_RELOC_32, R_SH_IMM32 }, 485 { BFD_RELOC_CTOR, R_SH_IMM32 }, 486 }; 487 #endif 488 489 /* Given a BFD reloc code, return the howto structure for the 490 corresponding SH PE reloc. */ 491 #define coff_bfd_reloc_type_lookup sh_coff_reloc_type_lookup 492 #define coff_bfd_reloc_name_lookup sh_coff_reloc_name_lookup 493 494 static reloc_howto_type * 495 sh_coff_reloc_type_lookup (bfd * abfd ATTRIBUTE_UNUSED, 496 bfd_reloc_code_real_type code) 497 { 498 unsigned int i; 499 500 for (i = ARRAY_SIZE (sh_reloc_map); i--;) 501 if (sh_reloc_map[i].bfd_reloc_val == code) 502 return &sh_coff_howtos[(int) sh_reloc_map[i].shcoff_reloc_val]; 503 504 (*_bfd_error_handler) (_("SH Error: unknown reloc type %d"), code); 505 return NULL; 506 } 507 508 static reloc_howto_type * 509 sh_coff_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED, 510 const char *r_name) 511 { 512 unsigned int i; 513 514 for (i = 0; i < sizeof (sh_coff_howtos) / sizeof (sh_coff_howtos[0]); i++) 515 if (sh_coff_howtos[i].name != NULL 516 && strcasecmp (sh_coff_howtos[i].name, r_name) == 0) 517 return &sh_coff_howtos[i]; 518 519 return NULL; 520 } 521 522 /* This macro is used in coffcode.h to get the howto corresponding to 523 an internal reloc. */ 524 525 #define RTYPE2HOWTO(relent, internal) \ 526 ((relent)->howto = \ 527 ((internal)->r_type < SH_COFF_HOWTO_COUNT \ 528 ? &sh_coff_howtos[(internal)->r_type] \ 529 : (reloc_howto_type *) NULL)) 530 531 /* This is the same as the macro in coffcode.h, except that it copies 532 r_offset into reloc_entry->addend for some relocs. */ 533 #define CALC_ADDEND(abfd, ptr, reloc, cache_ptr) \ 534 { \ 535 coff_symbol_type *coffsym = (coff_symbol_type *) NULL; \ 536 if (ptr && bfd_asymbol_bfd (ptr) != abfd) \ 537 coffsym = (obj_symbols (abfd) \ 538 + (cache_ptr->sym_ptr_ptr - symbols)); \ 539 else if (ptr) \ 540 coffsym = coff_symbol_from (ptr); \ 541 if (coffsym != (coff_symbol_type *) NULL \ 542 && coffsym->native->u.syment.n_scnum == 0) \ 543 cache_ptr->addend = 0; \ 544 else if (ptr && bfd_asymbol_bfd (ptr) == abfd \ 545 && ptr->section != (asection *) NULL) \ 546 cache_ptr->addend = - (ptr->section->vma + ptr->value); \ 547 else \ 548 cache_ptr->addend = 0; \ 549 if ((reloc).r_type == R_SH_SWITCH8 \ 550 || (reloc).r_type == R_SH_SWITCH16 \ 551 || (reloc).r_type == R_SH_SWITCH32 \ 552 || (reloc).r_type == R_SH_USES \ 553 || (reloc).r_type == R_SH_COUNT \ 554 || (reloc).r_type == R_SH_ALIGN) \ 555 cache_ptr->addend = (reloc).r_offset; \ 556 } 557 558 /* This is the howto function for the SH relocations. */ 559 560 static bfd_reloc_status_type 561 sh_reloc (bfd * abfd, 562 arelent * reloc_entry, 563 asymbol * symbol_in, 564 void * data, 565 asection * input_section, 566 bfd * output_bfd, 567 char ** error_message ATTRIBUTE_UNUSED) 568 { 569 unsigned long insn; 570 bfd_vma sym_value; 571 unsigned short r_type; 572 bfd_vma addr = reloc_entry->address; 573 bfd_byte *hit_data = addr + (bfd_byte *) data; 574 575 r_type = reloc_entry->howto->type; 576 577 if (output_bfd != NULL) 578 { 579 /* Partial linking--do nothing. */ 580 reloc_entry->address += input_section->output_offset; 581 return bfd_reloc_ok; 582 } 583 584 /* Almost all relocs have to do with relaxing. If any work must be 585 done for them, it has been done in sh_relax_section. */ 586 if (r_type != R_SH_IMM32 587 #ifdef COFF_WITH_PE 588 && r_type != R_SH_IMM32CE 589 && r_type != R_SH_IMAGEBASE 590 #endif 591 && (r_type != R_SH_PCDISP 592 || (symbol_in->flags & BSF_LOCAL) != 0)) 593 return bfd_reloc_ok; 594 595 if (symbol_in != NULL 596 && bfd_is_und_section (symbol_in->section)) 597 return bfd_reloc_undefined; 598 599 sym_value = get_symbol_value (symbol_in); 600 601 switch (r_type) 602 { 603 case R_SH_IMM32: 604 #ifdef COFF_WITH_PE 605 case R_SH_IMM32CE: 606 #endif 607 insn = bfd_get_32 (abfd, hit_data); 608 insn += sym_value + reloc_entry->addend; 609 bfd_put_32 (abfd, (bfd_vma) insn, hit_data); 610 break; 611 #ifdef COFF_WITH_PE 612 case R_SH_IMAGEBASE: 613 insn = bfd_get_32 (abfd, hit_data); 614 insn += sym_value + reloc_entry->addend; 615 insn -= pe_data (input_section->output_section->owner)->pe_opthdr.ImageBase; 616 bfd_put_32 (abfd, (bfd_vma) insn, hit_data); 617 break; 618 #endif 619 case R_SH_PCDISP: 620 insn = bfd_get_16 (abfd, hit_data); 621 sym_value += reloc_entry->addend; 622 sym_value -= (input_section->output_section->vma 623 + input_section->output_offset 624 + addr 625 + 4); 626 sym_value += (insn & 0xfff) << 1; 627 if (insn & 0x800) 628 sym_value -= 0x1000; 629 insn = (insn & 0xf000) | (sym_value & 0xfff); 630 bfd_put_16 (abfd, (bfd_vma) insn, hit_data); 631 if (sym_value < (bfd_vma) -0x1000 || sym_value >= 0x1000) 632 return bfd_reloc_overflow; 633 break; 634 default: 635 abort (); 636 break; 637 } 638 639 return bfd_reloc_ok; 640 } 641 642 #define coff_bfd_merge_private_bfd_data _bfd_generic_verify_endian_match 643 644 /* We can do relaxing. */ 645 #define coff_bfd_relax_section sh_relax_section 646 647 /* We use the special COFF backend linker. */ 648 #define coff_relocate_section sh_relocate_section 649 650 /* When relaxing, we need to use special code to get the relocated 651 section contents. */ 652 #define coff_bfd_get_relocated_section_contents \ 653 sh_coff_get_relocated_section_contents 654 655 #include "coffcode.h" 656 657 static bfd_boolean 659 sh_relax_delete_bytes (bfd *, asection *, bfd_vma, int); 660 661 /* This function handles relaxing on the SH. 662 663 Function calls on the SH look like this: 664 665 movl L1,r0 666 ... 667 jsr @r0 668 ... 669 L1: 670 .long function 671 672 The compiler and assembler will cooperate to create R_SH_USES 673 relocs on the jsr instructions. The r_offset field of the 674 R_SH_USES reloc is the PC relative offset to the instruction which 675 loads the register (the r_offset field is computed as though it 676 were a jump instruction, so the offset value is actually from four 677 bytes past the instruction). The linker can use this reloc to 678 determine just which function is being called, and thus decide 679 whether it is possible to replace the jsr with a bsr. 680 681 If multiple function calls are all based on a single register load 682 (i.e., the same function is called multiple times), the compiler 683 guarantees that each function call will have an R_SH_USES reloc. 684 Therefore, if the linker is able to convert each R_SH_USES reloc 685 which refers to that address, it can safely eliminate the register 686 load. 687 688 When the assembler creates an R_SH_USES reloc, it examines it to 689 determine which address is being loaded (L1 in the above example). 690 It then counts the number of references to that address, and 691 creates an R_SH_COUNT reloc at that address. The r_offset field of 692 the R_SH_COUNT reloc will be the number of references. If the 693 linker is able to eliminate a register load, it can use the 694 R_SH_COUNT reloc to see whether it can also eliminate the function 695 address. 696 697 SH relaxing also handles another, unrelated, matter. On the SH, if 698 a load or store instruction is not aligned on a four byte boundary, 699 the memory cycle interferes with the 32 bit instruction fetch, 700 causing a one cycle bubble in the pipeline. Therefore, we try to 701 align load and store instructions on four byte boundaries if we 702 can, by swapping them with one of the adjacent instructions. */ 703 704 static bfd_boolean 705 sh_relax_section (bfd *abfd, 706 asection *sec, 707 struct bfd_link_info *link_info, 708 bfd_boolean *again) 709 { 710 struct internal_reloc *internal_relocs; 711 bfd_boolean have_code; 712 struct internal_reloc *irel, *irelend; 713 bfd_byte *contents = NULL; 714 715 *again = FALSE; 716 717 if (bfd_link_relocatable (link_info) 718 || (sec->flags & SEC_RELOC) == 0 719 || sec->reloc_count == 0) 720 return TRUE; 721 722 if (coff_section_data (abfd, sec) == NULL) 723 { 724 bfd_size_type amt = sizeof (struct coff_section_tdata); 725 sec->used_by_bfd = bfd_zalloc (abfd, amt); 726 if (sec->used_by_bfd == NULL) 727 return FALSE; 728 } 729 730 internal_relocs = (_bfd_coff_read_internal_relocs 731 (abfd, sec, link_info->keep_memory, 732 (bfd_byte *) NULL, FALSE, 733 (struct internal_reloc *) NULL)); 734 if (internal_relocs == NULL) 735 goto error_return; 736 737 have_code = FALSE; 738 739 irelend = internal_relocs + sec->reloc_count; 740 for (irel = internal_relocs; irel < irelend; irel++) 741 { 742 bfd_vma laddr, paddr, symval; 743 unsigned short insn; 744 struct internal_reloc *irelfn, *irelscan, *irelcount; 745 struct internal_syment sym; 746 bfd_signed_vma foff; 747 748 if (irel->r_type == R_SH_CODE) 749 have_code = TRUE; 750 751 if (irel->r_type != R_SH_USES) 752 continue; 753 754 /* Get the section contents. */ 755 if (contents == NULL) 756 { 757 if (coff_section_data (abfd, sec)->contents != NULL) 758 contents = coff_section_data (abfd, sec)->contents; 759 else 760 { 761 if (!bfd_malloc_and_get_section (abfd, sec, &contents)) 762 goto error_return; 763 } 764 } 765 766 /* The r_offset field of the R_SH_USES reloc will point us to 767 the register load. The 4 is because the r_offset field is 768 computed as though it were a jump offset, which are based 769 from 4 bytes after the jump instruction. */ 770 laddr = irel->r_vaddr - sec->vma + 4; 771 /* Careful to sign extend the 32-bit offset. */ 772 laddr += ((irel->r_offset & 0xffffffff) ^ 0x80000000) - 0x80000000; 773 if (laddr >= sec->size) 774 { 775 (*_bfd_error_handler) ("%B: 0x%lx: warning: bad R_SH_USES offset", 776 abfd, (unsigned long) irel->r_vaddr); 777 continue; 778 } 779 insn = bfd_get_16 (abfd, contents + laddr); 780 781 /* If the instruction is not mov.l NN,rN, we don't know what to do. */ 782 if ((insn & 0xf000) != 0xd000) 783 { 784 ((*_bfd_error_handler) 785 ("%B: 0x%lx: warning: R_SH_USES points to unrecognized insn 0x%x", 786 abfd, (unsigned long) irel->r_vaddr, insn)); 787 continue; 788 } 789 790 /* Get the address from which the register is being loaded. The 791 displacement in the mov.l instruction is quadrupled. It is a 792 displacement from four bytes after the movl instruction, but, 793 before adding in the PC address, two least significant bits 794 of the PC are cleared. We assume that the section is aligned 795 on a four byte boundary. */ 796 paddr = insn & 0xff; 797 paddr *= 4; 798 paddr += (laddr + 4) &~ (bfd_vma) 3; 799 if (paddr >= sec->size) 800 { 801 ((*_bfd_error_handler) 802 ("%B: 0x%lx: warning: bad R_SH_USES load offset", 803 abfd, (unsigned long) irel->r_vaddr)); 804 continue; 805 } 806 807 /* Get the reloc for the address from which the register is 808 being loaded. This reloc will tell us which function is 809 actually being called. */ 810 paddr += sec->vma; 811 for (irelfn = internal_relocs; irelfn < irelend; irelfn++) 812 if (irelfn->r_vaddr == paddr 813 #ifdef COFF_WITH_PE 814 && (irelfn->r_type == R_SH_IMM32 815 || irelfn->r_type == R_SH_IMM32CE 816 || irelfn->r_type == R_SH_IMAGEBASE) 817 818 #else 819 && irelfn->r_type == R_SH_IMM32 820 #endif 821 ) 822 break; 823 if (irelfn >= irelend) 824 { 825 ((*_bfd_error_handler) 826 ("%B: 0x%lx: warning: could not find expected reloc", 827 abfd, (unsigned long) paddr)); 828 continue; 829 } 830 831 /* Get the value of the symbol referred to by the reloc. */ 832 if (! _bfd_coff_get_external_symbols (abfd)) 833 goto error_return; 834 bfd_coff_swap_sym_in (abfd, 835 ((bfd_byte *) obj_coff_external_syms (abfd) 836 + (irelfn->r_symndx 837 * bfd_coff_symesz (abfd))), 838 &sym); 839 if (sym.n_scnum != 0 && sym.n_scnum != sec->target_index) 840 { 841 ((*_bfd_error_handler) 842 ("%B: 0x%lx: warning: symbol in unexpected section", 843 abfd, (unsigned long) paddr)); 844 continue; 845 } 846 847 if (sym.n_sclass != C_EXT) 848 { 849 symval = (sym.n_value 850 - sec->vma 851 + sec->output_section->vma 852 + sec->output_offset); 853 } 854 else 855 { 856 struct coff_link_hash_entry *h; 857 858 h = obj_coff_sym_hashes (abfd)[irelfn->r_symndx]; 859 BFD_ASSERT (h != NULL); 860 if (h->root.type != bfd_link_hash_defined 861 && h->root.type != bfd_link_hash_defweak) 862 { 863 /* This appears to be a reference to an undefined 864 symbol. Just ignore it--it will be caught by the 865 regular reloc processing. */ 866 continue; 867 } 868 869 symval = (h->root.u.def.value 870 + h->root.u.def.section->output_section->vma 871 + h->root.u.def.section->output_offset); 872 } 873 874 symval += bfd_get_32 (abfd, contents + paddr - sec->vma); 875 876 /* See if this function call can be shortened. */ 877 foff = (symval 878 - (irel->r_vaddr 879 - sec->vma 880 + sec->output_section->vma 881 + sec->output_offset 882 + 4)); 883 if (foff < -0x1000 || foff >= 0x1000) 884 { 885 /* After all that work, we can't shorten this function call. */ 886 continue; 887 } 888 889 /* Shorten the function call. */ 890 891 /* For simplicity of coding, we are going to modify the section 892 contents, the section relocs, and the BFD symbol table. We 893 must tell the rest of the code not to free up this 894 information. It would be possible to instead create a table 895 of changes which have to be made, as is done in coff-mips.c; 896 that would be more work, but would require less memory when 897 the linker is run. */ 898 899 coff_section_data (abfd, sec)->relocs = internal_relocs; 900 coff_section_data (abfd, sec)->keep_relocs = TRUE; 901 902 coff_section_data (abfd, sec)->contents = contents; 903 coff_section_data (abfd, sec)->keep_contents = TRUE; 904 905 obj_coff_keep_syms (abfd) = TRUE; 906 907 /* Replace the jsr with a bsr. */ 908 909 /* Change the R_SH_USES reloc into an R_SH_PCDISP reloc, and 910 replace the jsr with a bsr. */ 911 irel->r_type = R_SH_PCDISP; 912 irel->r_symndx = irelfn->r_symndx; 913 if (sym.n_sclass != C_EXT) 914 { 915 /* If this needs to be changed because of future relaxing, 916 it will be handled here like other internal PCDISP 917 relocs. */ 918 bfd_put_16 (abfd, 919 (bfd_vma) 0xb000 | ((foff >> 1) & 0xfff), 920 contents + irel->r_vaddr - sec->vma); 921 } 922 else 923 { 924 /* We can't fully resolve this yet, because the external 925 symbol value may be changed by future relaxing. We let 926 the final link phase handle it. */ 927 bfd_put_16 (abfd, (bfd_vma) 0xb000, 928 contents + irel->r_vaddr - sec->vma); 929 } 930 931 /* See if there is another R_SH_USES reloc referring to the same 932 register load. */ 933 for (irelscan = internal_relocs; irelscan < irelend; irelscan++) 934 if (irelscan->r_type == R_SH_USES 935 && laddr == irelscan->r_vaddr - sec->vma + 4 + irelscan->r_offset) 936 break; 937 if (irelscan < irelend) 938 { 939 /* Some other function call depends upon this register load, 940 and we have not yet converted that function call. 941 Indeed, we may never be able to convert it. There is 942 nothing else we can do at this point. */ 943 continue; 944 } 945 946 /* Look for a R_SH_COUNT reloc on the location where the 947 function address is stored. Do this before deleting any 948 bytes, to avoid confusion about the address. */ 949 for (irelcount = internal_relocs; irelcount < irelend; irelcount++) 950 if (irelcount->r_vaddr == paddr 951 && irelcount->r_type == R_SH_COUNT) 952 break; 953 954 /* Delete the register load. */ 955 if (! sh_relax_delete_bytes (abfd, sec, laddr, 2)) 956 goto error_return; 957 958 /* That will change things, so, just in case it permits some 959 other function call to come within range, we should relax 960 again. Note that this is not required, and it may be slow. */ 961 *again = TRUE; 962 963 /* Now check whether we got a COUNT reloc. */ 964 if (irelcount >= irelend) 965 { 966 ((*_bfd_error_handler) 967 ("%B: 0x%lx: warning: could not find expected COUNT reloc", 968 abfd, (unsigned long) paddr)); 969 continue; 970 } 971 972 /* The number of uses is stored in the r_offset field. We've 973 just deleted one. */ 974 if (irelcount->r_offset == 0) 975 { 976 ((*_bfd_error_handler) ("%B: 0x%lx: warning: bad count", 977 abfd, (unsigned long) paddr)); 978 continue; 979 } 980 981 --irelcount->r_offset; 982 983 /* If there are no more uses, we can delete the address. Reload 984 the address from irelfn, in case it was changed by the 985 previous call to sh_relax_delete_bytes. */ 986 if (irelcount->r_offset == 0) 987 { 988 if (! sh_relax_delete_bytes (abfd, sec, 989 irelfn->r_vaddr - sec->vma, 4)) 990 goto error_return; 991 } 992 993 /* We've done all we can with that function call. */ 994 } 995 996 /* Look for load and store instructions that we can align on four 997 byte boundaries. */ 998 if (have_code) 999 { 1000 bfd_boolean swapped; 1001 1002 /* Get the section contents. */ 1003 if (contents == NULL) 1004 { 1005 if (coff_section_data (abfd, sec)->contents != NULL) 1006 contents = coff_section_data (abfd, sec)->contents; 1007 else 1008 { 1009 if (!bfd_malloc_and_get_section (abfd, sec, &contents)) 1010 goto error_return; 1011 } 1012 } 1013 1014 if (! sh_align_loads (abfd, sec, internal_relocs, contents, &swapped)) 1015 goto error_return; 1016 1017 if (swapped) 1018 { 1019 coff_section_data (abfd, sec)->relocs = internal_relocs; 1020 coff_section_data (abfd, sec)->keep_relocs = TRUE; 1021 1022 coff_section_data (abfd, sec)->contents = contents; 1023 coff_section_data (abfd, sec)->keep_contents = TRUE; 1024 1025 obj_coff_keep_syms (abfd) = TRUE; 1026 } 1027 } 1028 1029 if (internal_relocs != NULL 1030 && internal_relocs != coff_section_data (abfd, sec)->relocs) 1031 { 1032 if (! link_info->keep_memory) 1033 free (internal_relocs); 1034 else 1035 coff_section_data (abfd, sec)->relocs = internal_relocs; 1036 } 1037 1038 if (contents != NULL && contents != coff_section_data (abfd, sec)->contents) 1039 { 1040 if (! link_info->keep_memory) 1041 free (contents); 1042 else 1043 /* Cache the section contents for coff_link_input_bfd. */ 1044 coff_section_data (abfd, sec)->contents = contents; 1045 } 1046 1047 return TRUE; 1048 1049 error_return: 1050 if (internal_relocs != NULL 1051 && internal_relocs != coff_section_data (abfd, sec)->relocs) 1052 free (internal_relocs); 1053 if (contents != NULL && contents != coff_section_data (abfd, sec)->contents) 1054 free (contents); 1055 return FALSE; 1056 } 1057 1058 /* Delete some bytes from a section while relaxing. */ 1059 1060 static bfd_boolean 1061 sh_relax_delete_bytes (bfd *abfd, 1062 asection *sec, 1063 bfd_vma addr, 1064 int count) 1065 { 1066 bfd_byte *contents; 1067 struct internal_reloc *irel, *irelend; 1068 struct internal_reloc *irelalign; 1069 bfd_vma toaddr; 1070 bfd_byte *esym, *esymend; 1071 bfd_size_type symesz; 1072 struct coff_link_hash_entry **sym_hash; 1073 asection *o; 1074 1075 contents = coff_section_data (abfd, sec)->contents; 1076 1077 /* The deletion must stop at the next ALIGN reloc for an aligment 1078 power larger than the number of bytes we are deleting. */ 1079 1080 irelalign = NULL; 1081 toaddr = sec->size; 1082 1083 irel = coff_section_data (abfd, sec)->relocs; 1084 irelend = irel + sec->reloc_count; 1085 for (; irel < irelend; irel++) 1086 { 1087 if (irel->r_type == R_SH_ALIGN 1088 && irel->r_vaddr - sec->vma > addr 1089 && count < (1 << irel->r_offset)) 1090 { 1091 irelalign = irel; 1092 toaddr = irel->r_vaddr - sec->vma; 1093 break; 1094 } 1095 } 1096 1097 /* Actually delete the bytes. */ 1098 memmove (contents + addr, contents + addr + count, 1099 (size_t) (toaddr - addr - count)); 1100 if (irelalign == NULL) 1101 sec->size -= count; 1102 else 1103 { 1104 int i; 1105 1106 #define NOP_OPCODE (0x0009) 1107 1108 BFD_ASSERT ((count & 1) == 0); 1109 for (i = 0; i < count; i += 2) 1110 bfd_put_16 (abfd, (bfd_vma) NOP_OPCODE, contents + toaddr - count + i); 1111 } 1112 1113 /* Adjust all the relocs. */ 1114 for (irel = coff_section_data (abfd, sec)->relocs; irel < irelend; irel++) 1115 { 1116 bfd_vma nraddr, stop; 1117 bfd_vma start = 0; 1118 int insn = 0; 1119 struct internal_syment sym; 1120 int off, adjust, oinsn; 1121 bfd_signed_vma voff = 0; 1122 bfd_boolean overflow; 1123 1124 /* Get the new reloc address. */ 1125 nraddr = irel->r_vaddr - sec->vma; 1126 if ((irel->r_vaddr - sec->vma > addr 1127 && irel->r_vaddr - sec->vma < toaddr) 1128 || (irel->r_type == R_SH_ALIGN 1129 && irel->r_vaddr - sec->vma == toaddr)) 1130 nraddr -= count; 1131 1132 /* See if this reloc was for the bytes we have deleted, in which 1133 case we no longer care about it. Don't delete relocs which 1134 represent addresses, though. */ 1135 if (irel->r_vaddr - sec->vma >= addr 1136 && irel->r_vaddr - sec->vma < addr + count 1137 && irel->r_type != R_SH_ALIGN 1138 && irel->r_type != R_SH_CODE 1139 && irel->r_type != R_SH_DATA 1140 && irel->r_type != R_SH_LABEL) 1141 irel->r_type = R_SH_UNUSED; 1142 1143 /* If this is a PC relative reloc, see if the range it covers 1144 includes the bytes we have deleted. */ 1145 switch (irel->r_type) 1146 { 1147 default: 1148 break; 1149 1150 case R_SH_PCDISP8BY2: 1151 case R_SH_PCDISP: 1152 case R_SH_PCRELIMM8BY2: 1153 case R_SH_PCRELIMM8BY4: 1154 start = irel->r_vaddr - sec->vma; 1155 insn = bfd_get_16 (abfd, contents + nraddr); 1156 break; 1157 } 1158 1159 switch (irel->r_type) 1160 { 1161 default: 1162 start = stop = addr; 1163 break; 1164 1165 case R_SH_IMM32: 1166 #ifdef COFF_WITH_PE 1167 case R_SH_IMM32CE: 1168 case R_SH_IMAGEBASE: 1169 #endif 1170 /* If this reloc is against a symbol defined in this 1171 section, and the symbol will not be adjusted below, we 1172 must check the addend to see it will put the value in 1173 range to be adjusted, and hence must be changed. */ 1174 bfd_coff_swap_sym_in (abfd, 1175 ((bfd_byte *) obj_coff_external_syms (abfd) 1176 + (irel->r_symndx 1177 * bfd_coff_symesz (abfd))), 1178 &sym); 1179 if (sym.n_sclass != C_EXT 1180 && sym.n_scnum == sec->target_index 1181 && ((bfd_vma) sym.n_value <= addr 1182 || (bfd_vma) sym.n_value >= toaddr)) 1183 { 1184 bfd_vma val; 1185 1186 val = bfd_get_32 (abfd, contents + nraddr); 1187 val += sym.n_value; 1188 if (val > addr && val < toaddr) 1189 bfd_put_32 (abfd, val - count, contents + nraddr); 1190 } 1191 start = stop = addr; 1192 break; 1193 1194 case R_SH_PCDISP8BY2: 1195 off = insn & 0xff; 1196 if (off & 0x80) 1197 off -= 0x100; 1198 stop = (bfd_vma) ((bfd_signed_vma) start + 4 + off * 2); 1199 break; 1200 1201 case R_SH_PCDISP: 1202 bfd_coff_swap_sym_in (abfd, 1203 ((bfd_byte *) obj_coff_external_syms (abfd) 1204 + (irel->r_symndx 1205 * bfd_coff_symesz (abfd))), 1206 &sym); 1207 if (sym.n_sclass == C_EXT) 1208 start = stop = addr; 1209 else 1210 { 1211 off = insn & 0xfff; 1212 if (off & 0x800) 1213 off -= 0x1000; 1214 stop = (bfd_vma) ((bfd_signed_vma) start + 4 + off * 2); 1215 } 1216 break; 1217 1218 case R_SH_PCRELIMM8BY2: 1219 off = insn & 0xff; 1220 stop = start + 4 + off * 2; 1221 break; 1222 1223 case R_SH_PCRELIMM8BY4: 1224 off = insn & 0xff; 1225 stop = (start &~ (bfd_vma) 3) + 4 + off * 4; 1226 break; 1227 1228 case R_SH_SWITCH8: 1229 case R_SH_SWITCH16: 1230 case R_SH_SWITCH32: 1231 /* These relocs types represent 1232 .word L2-L1 1233 The r_offset field holds the difference between the reloc 1234 address and L1. That is the start of the reloc, and 1235 adding in the contents gives us the top. We must adjust 1236 both the r_offset field and the section contents. */ 1237 1238 start = irel->r_vaddr - sec->vma; 1239 stop = (bfd_vma) ((bfd_signed_vma) start - (long) irel->r_offset); 1240 1241 if (start > addr 1242 && start < toaddr 1243 && (stop <= addr || stop >= toaddr)) 1244 irel->r_offset += count; 1245 else if (stop > addr 1246 && stop < toaddr 1247 && (start <= addr || start >= toaddr)) 1248 irel->r_offset -= count; 1249 1250 start = stop; 1251 1252 if (irel->r_type == R_SH_SWITCH16) 1253 voff = bfd_get_signed_16 (abfd, contents + nraddr); 1254 else if (irel->r_type == R_SH_SWITCH8) 1255 voff = bfd_get_8 (abfd, contents + nraddr); 1256 else 1257 voff = bfd_get_signed_32 (abfd, contents + nraddr); 1258 stop = (bfd_vma) ((bfd_signed_vma) start + voff); 1259 1260 break; 1261 1262 case R_SH_USES: 1263 start = irel->r_vaddr - sec->vma; 1264 stop = (bfd_vma) ((bfd_signed_vma) start 1265 + (long) irel->r_offset 1266 + 4); 1267 break; 1268 } 1269 1270 if (start > addr 1271 && start < toaddr 1272 && (stop <= addr || stop >= toaddr)) 1273 adjust = count; 1274 else if (stop > addr 1275 && stop < toaddr 1276 && (start <= addr || start >= toaddr)) 1277 adjust = - count; 1278 else 1279 adjust = 0; 1280 1281 if (adjust != 0) 1282 { 1283 oinsn = insn; 1284 overflow = FALSE; 1285 switch (irel->r_type) 1286 { 1287 default: 1288 abort (); 1289 break; 1290 1291 case R_SH_PCDISP8BY2: 1292 case R_SH_PCRELIMM8BY2: 1293 insn += adjust / 2; 1294 if ((oinsn & 0xff00) != (insn & 0xff00)) 1295 overflow = TRUE; 1296 bfd_put_16 (abfd, (bfd_vma) insn, contents + nraddr); 1297 break; 1298 1299 case R_SH_PCDISP: 1300 insn += adjust / 2; 1301 if ((oinsn & 0xf000) != (insn & 0xf000)) 1302 overflow = TRUE; 1303 bfd_put_16 (abfd, (bfd_vma) insn, contents + nraddr); 1304 break; 1305 1306 case R_SH_PCRELIMM8BY4: 1307 BFD_ASSERT (adjust == count || count >= 4); 1308 if (count >= 4) 1309 insn += adjust / 4; 1310 else 1311 { 1312 if ((irel->r_vaddr & 3) == 0) 1313 ++insn; 1314 } 1315 if ((oinsn & 0xff00) != (insn & 0xff00)) 1316 overflow = TRUE; 1317 bfd_put_16 (abfd, (bfd_vma) insn, contents + nraddr); 1318 break; 1319 1320 case R_SH_SWITCH8: 1321 voff += adjust; 1322 if (voff < 0 || voff >= 0xff) 1323 overflow = TRUE; 1324 bfd_put_8 (abfd, (bfd_vma) voff, contents + nraddr); 1325 break; 1326 1327 case R_SH_SWITCH16: 1328 voff += adjust; 1329 if (voff < - 0x8000 || voff >= 0x8000) 1330 overflow = TRUE; 1331 bfd_put_signed_16 (abfd, (bfd_vma) voff, contents + nraddr); 1332 break; 1333 1334 case R_SH_SWITCH32: 1335 voff += adjust; 1336 bfd_put_signed_32 (abfd, (bfd_vma) voff, contents + nraddr); 1337 break; 1338 1339 case R_SH_USES: 1340 irel->r_offset += adjust; 1341 break; 1342 } 1343 1344 if (overflow) 1345 { 1346 ((*_bfd_error_handler) 1347 ("%B: 0x%lx: fatal: reloc overflow while relaxing", 1348 abfd, (unsigned long) irel->r_vaddr)); 1349 bfd_set_error (bfd_error_bad_value); 1350 return FALSE; 1351 } 1352 } 1353 1354 irel->r_vaddr = nraddr + sec->vma; 1355 } 1356 1357 /* Look through all the other sections. If there contain any IMM32 1358 relocs against internal symbols which we are not going to adjust 1359 below, we may need to adjust the addends. */ 1360 for (o = abfd->sections; o != NULL; o = o->next) 1361 { 1362 struct internal_reloc *internal_relocs; 1363 struct internal_reloc *irelscan, *irelscanend; 1364 bfd_byte *ocontents; 1365 1366 if (o == sec 1367 || (o->flags & SEC_RELOC) == 0 1368 || o->reloc_count == 0) 1369 continue; 1370 1371 /* We always cache the relocs. Perhaps, if info->keep_memory is 1372 FALSE, we should free them, if we are permitted to, when we 1373 leave sh_coff_relax_section. */ 1374 internal_relocs = (_bfd_coff_read_internal_relocs 1375 (abfd, o, TRUE, (bfd_byte *) NULL, FALSE, 1376 (struct internal_reloc *) NULL)); 1377 if (internal_relocs == NULL) 1378 return FALSE; 1379 1380 ocontents = NULL; 1381 irelscanend = internal_relocs + o->reloc_count; 1382 for (irelscan = internal_relocs; irelscan < irelscanend; irelscan++) 1383 { 1384 struct internal_syment sym; 1385 1386 #ifdef COFF_WITH_PE 1387 if (irelscan->r_type != R_SH_IMM32 1388 && irelscan->r_type != R_SH_IMAGEBASE 1389 && irelscan->r_type != R_SH_IMM32CE) 1390 #else 1391 if (irelscan->r_type != R_SH_IMM32) 1392 #endif 1393 continue; 1394 1395 bfd_coff_swap_sym_in (abfd, 1396 ((bfd_byte *) obj_coff_external_syms (abfd) 1397 + (irelscan->r_symndx 1398 * bfd_coff_symesz (abfd))), 1399 &sym); 1400 if (sym.n_sclass != C_EXT 1401 && sym.n_scnum == sec->target_index 1402 && ((bfd_vma) sym.n_value <= addr 1403 || (bfd_vma) sym.n_value >= toaddr)) 1404 { 1405 bfd_vma val; 1406 1407 if (ocontents == NULL) 1408 { 1409 if (coff_section_data (abfd, o)->contents != NULL) 1410 ocontents = coff_section_data (abfd, o)->contents; 1411 else 1412 { 1413 if (!bfd_malloc_and_get_section (abfd, o, &ocontents)) 1414 return FALSE; 1415 /* We always cache the section contents. 1416 Perhaps, if info->keep_memory is FALSE, we 1417 should free them, if we are permitted to, 1418 when we leave sh_coff_relax_section. */ 1419 coff_section_data (abfd, o)->contents = ocontents; 1420 } 1421 } 1422 1423 val = bfd_get_32 (abfd, ocontents + irelscan->r_vaddr - o->vma); 1424 val += sym.n_value; 1425 if (val > addr && val < toaddr) 1426 bfd_put_32 (abfd, val - count, 1427 ocontents + irelscan->r_vaddr - o->vma); 1428 1429 coff_section_data (abfd, o)->keep_contents = TRUE; 1430 } 1431 } 1432 } 1433 1434 /* Adjusting the internal symbols will not work if something has 1435 already retrieved the generic symbols. It would be possible to 1436 make this work by adjusting the generic symbols at the same time. 1437 However, this case should not arise in normal usage. */ 1438 if (obj_symbols (abfd) != NULL 1439 || obj_raw_syments (abfd) != NULL) 1440 { 1441 ((*_bfd_error_handler) 1442 ("%B: fatal: generic symbols retrieved before relaxing", abfd)); 1443 bfd_set_error (bfd_error_invalid_operation); 1444 return FALSE; 1445 } 1446 1447 /* Adjust all the symbols. */ 1448 sym_hash = obj_coff_sym_hashes (abfd); 1449 symesz = bfd_coff_symesz (abfd); 1450 esym = (bfd_byte *) obj_coff_external_syms (abfd); 1451 esymend = esym + obj_raw_syment_count (abfd) * symesz; 1452 while (esym < esymend) 1453 { 1454 struct internal_syment isym; 1455 1456 bfd_coff_swap_sym_in (abfd, esym, &isym); 1457 1458 if (isym.n_scnum == sec->target_index 1459 && (bfd_vma) isym.n_value > addr 1460 && (bfd_vma) isym.n_value < toaddr) 1461 { 1462 isym.n_value -= count; 1463 1464 bfd_coff_swap_sym_out (abfd, &isym, esym); 1465 1466 if (*sym_hash != NULL) 1467 { 1468 BFD_ASSERT ((*sym_hash)->root.type == bfd_link_hash_defined 1469 || (*sym_hash)->root.type == bfd_link_hash_defweak); 1470 BFD_ASSERT ((*sym_hash)->root.u.def.value >= addr 1471 && (*sym_hash)->root.u.def.value < toaddr); 1472 (*sym_hash)->root.u.def.value -= count; 1473 } 1474 } 1475 1476 esym += (isym.n_numaux + 1) * symesz; 1477 sym_hash += isym.n_numaux + 1; 1478 } 1479 1480 /* See if we can move the ALIGN reloc forward. We have adjusted 1481 r_vaddr for it already. */ 1482 if (irelalign != NULL) 1483 { 1484 bfd_vma alignto, alignaddr; 1485 1486 alignto = BFD_ALIGN (toaddr, 1 << irelalign->r_offset); 1487 alignaddr = BFD_ALIGN (irelalign->r_vaddr - sec->vma, 1488 1 << irelalign->r_offset); 1489 if (alignto != alignaddr) 1490 { 1491 /* Tail recursion. */ 1492 return sh_relax_delete_bytes (abfd, sec, alignaddr, 1493 (int) (alignto - alignaddr)); 1494 } 1495 } 1496 1497 return TRUE; 1498 } 1499 1500 /* This is yet another version of the SH opcode table, used to rapidly 1502 get information about a particular instruction. */ 1503 1504 /* The opcode map is represented by an array of these structures. The 1505 array is indexed by the high order four bits in the instruction. */ 1506 1507 struct sh_major_opcode 1508 { 1509 /* A pointer to the instruction list. This is an array which 1510 contains all the instructions with this major opcode. */ 1511 const struct sh_minor_opcode *minor_opcodes; 1512 /* The number of elements in minor_opcodes. */ 1513 unsigned short count; 1514 }; 1515 1516 /* This structure holds information for a set of SH opcodes. The 1517 instruction code is anded with the mask value, and the resulting 1518 value is used to search the order opcode list. */ 1519 1520 struct sh_minor_opcode 1521 { 1522 /* The sorted opcode list. */ 1523 const struct sh_opcode *opcodes; 1524 /* The number of elements in opcodes. */ 1525 unsigned short count; 1526 /* The mask value to use when searching the opcode list. */ 1527 unsigned short mask; 1528 }; 1529 1530 /* This structure holds information for an SH instruction. An array 1531 of these structures is sorted in order by opcode. */ 1532 1533 struct sh_opcode 1534 { 1535 /* The code for this instruction, after it has been anded with the 1536 mask value in the sh_major_opcode structure. */ 1537 unsigned short opcode; 1538 /* Flags for this instruction. */ 1539 unsigned long flags; 1540 }; 1541 1542 /* Flag which appear in the sh_opcode structure. */ 1543 1544 /* This instruction loads a value from memory. */ 1545 #define LOAD (0x1) 1546 1547 /* This instruction stores a value to memory. */ 1548 #define STORE (0x2) 1549 1550 /* This instruction is a branch. */ 1551 #define BRANCH (0x4) 1552 1553 /* This instruction has a delay slot. */ 1554 #define DELAY (0x8) 1555 1556 /* This instruction uses the value in the register in the field at 1557 mask 0x0f00 of the instruction. */ 1558 #define USES1 (0x10) 1559 #define USES1_REG(x) ((x & 0x0f00) >> 8) 1560 1561 /* This instruction uses the value in the register in the field at 1562 mask 0x00f0 of the instruction. */ 1563 #define USES2 (0x20) 1564 #define USES2_REG(x) ((x & 0x00f0) >> 4) 1565 1566 /* This instruction uses the value in register 0. */ 1567 #define USESR0 (0x40) 1568 1569 /* This instruction sets the value in the register in the field at 1570 mask 0x0f00 of the instruction. */ 1571 #define SETS1 (0x80) 1572 #define SETS1_REG(x) ((x & 0x0f00) >> 8) 1573 1574 /* This instruction sets the value in the register in the field at 1575 mask 0x00f0 of the instruction. */ 1576 #define SETS2 (0x100) 1577 #define SETS2_REG(x) ((x & 0x00f0) >> 4) 1578 1579 /* This instruction sets register 0. */ 1580 #define SETSR0 (0x200) 1581 1582 /* This instruction sets a special register. */ 1583 #define SETSSP (0x400) 1584 1585 /* This instruction uses a special register. */ 1586 #define USESSP (0x800) 1587 1588 /* This instruction uses the floating point register in the field at 1589 mask 0x0f00 of the instruction. */ 1590 #define USESF1 (0x1000) 1591 #define USESF1_REG(x) ((x & 0x0f00) >> 8) 1592 1593 /* This instruction uses the floating point register in the field at 1594 mask 0x00f0 of the instruction. */ 1595 #define USESF2 (0x2000) 1596 #define USESF2_REG(x) ((x & 0x00f0) >> 4) 1597 1598 /* This instruction uses floating point register 0. */ 1599 #define USESF0 (0x4000) 1600 1601 /* This instruction sets the floating point register in the field at 1602 mask 0x0f00 of the instruction. */ 1603 #define SETSF1 (0x8000) 1604 #define SETSF1_REG(x) ((x & 0x0f00) >> 8) 1605 1606 #define USESAS (0x10000) 1607 #define USESAS_REG(x) (((((x) >> 8) - 2) & 3) + 2) 1608 #define USESR8 (0x20000) 1609 #define SETSAS (0x40000) 1610 #define SETSAS_REG(x) USESAS_REG (x) 1611 1612 #define MAP(a) a, sizeof a / sizeof a[0] 1613 1614 #ifndef COFF_IMAGE_WITH_PE 1615 1616 /* The opcode maps. */ 1617 1618 static const struct sh_opcode sh_opcode00[] = 1619 { 1620 { 0x0008, SETSSP }, /* clrt */ 1621 { 0x0009, 0 }, /* nop */ 1622 { 0x000b, BRANCH | DELAY | USESSP }, /* rts */ 1623 { 0x0018, SETSSP }, /* sett */ 1624 { 0x0019, SETSSP }, /* div0u */ 1625 { 0x001b, 0 }, /* sleep */ 1626 { 0x0028, SETSSP }, /* clrmac */ 1627 { 0x002b, BRANCH | DELAY | SETSSP }, /* rte */ 1628 { 0x0038, USESSP | SETSSP }, /* ldtlb */ 1629 { 0x0048, SETSSP }, /* clrs */ 1630 { 0x0058, SETSSP } /* sets */ 1631 }; 1632 1633 static const struct sh_opcode sh_opcode01[] = 1634 { 1635 { 0x0003, BRANCH | DELAY | USES1 | SETSSP }, /* bsrf rn */ 1636 { 0x000a, SETS1 | USESSP }, /* sts mach,rn */ 1637 { 0x001a, SETS1 | USESSP }, /* sts macl,rn */ 1638 { 0x0023, BRANCH | DELAY | USES1 }, /* braf rn */ 1639 { 0x0029, SETS1 | USESSP }, /* movt rn */ 1640 { 0x002a, SETS1 | USESSP }, /* sts pr,rn */ 1641 { 0x005a, SETS1 | USESSP }, /* sts fpul,rn */ 1642 { 0x006a, SETS1 | USESSP }, /* sts fpscr,rn / sts dsr,rn */ 1643 { 0x0083, LOAD | USES1 }, /* pref @rn */ 1644 { 0x007a, SETS1 | USESSP }, /* sts a0,rn */ 1645 { 0x008a, SETS1 | USESSP }, /* sts x0,rn */ 1646 { 0x009a, SETS1 | USESSP }, /* sts x1,rn */ 1647 { 0x00aa, SETS1 | USESSP }, /* sts y0,rn */ 1648 { 0x00ba, SETS1 | USESSP } /* sts y1,rn */ 1649 }; 1650 1651 static const struct sh_opcode sh_opcode02[] = 1652 { 1653 { 0x0002, SETS1 | USESSP }, /* stc <special_reg>,rn */ 1654 { 0x0004, STORE | USES1 | USES2 | USESR0 }, /* mov.b rm,@(r0,rn) */ 1655 { 0x0005, STORE | USES1 | USES2 | USESR0 }, /* mov.w rm,@(r0,rn) */ 1656 { 0x0006, STORE | USES1 | USES2 | USESR0 }, /* mov.l rm,@(r0,rn) */ 1657 { 0x0007, SETSSP | USES1 | USES2 }, /* mul.l rm,rn */ 1658 { 0x000c, LOAD | SETS1 | USES2 | USESR0 }, /* mov.b @(r0,rm),rn */ 1659 { 0x000d, LOAD | SETS1 | USES2 | USESR0 }, /* mov.w @(r0,rm),rn */ 1660 { 0x000e, LOAD | SETS1 | USES2 | USESR0 }, /* mov.l @(r0,rm),rn */ 1661 { 0x000f, LOAD|SETS1|SETS2|SETSSP|USES1|USES2|USESSP }, /* mac.l @rm+,@rn+ */ 1662 }; 1663 1664 static const struct sh_minor_opcode sh_opcode0[] = 1665 { 1666 { MAP (sh_opcode00), 0xffff }, 1667 { MAP (sh_opcode01), 0xf0ff }, 1668 { MAP (sh_opcode02), 0xf00f } 1669 }; 1670 1671 static const struct sh_opcode sh_opcode10[] = 1672 { 1673 { 0x1000, STORE | USES1 | USES2 } /* mov.l rm,@(disp,rn) */ 1674 }; 1675 1676 static const struct sh_minor_opcode sh_opcode1[] = 1677 { 1678 { MAP (sh_opcode10), 0xf000 } 1679 }; 1680 1681 static const struct sh_opcode sh_opcode20[] = 1682 { 1683 { 0x2000, STORE | USES1 | USES2 }, /* mov.b rm,@rn */ 1684 { 0x2001, STORE | USES1 | USES2 }, /* mov.w rm,@rn */ 1685 { 0x2002, STORE | USES1 | USES2 }, /* mov.l rm,@rn */ 1686 { 0x2004, STORE | SETS1 | USES1 | USES2 }, /* mov.b rm,@-rn */ 1687 { 0x2005, STORE | SETS1 | USES1 | USES2 }, /* mov.w rm,@-rn */ 1688 { 0x2006, STORE | SETS1 | USES1 | USES2 }, /* mov.l rm,@-rn */ 1689 { 0x2007, SETSSP | USES1 | USES2 | USESSP }, /* div0s */ 1690 { 0x2008, SETSSP | USES1 | USES2 }, /* tst rm,rn */ 1691 { 0x2009, SETS1 | USES1 | USES2 }, /* and rm,rn */ 1692 { 0x200a, SETS1 | USES1 | USES2 }, /* xor rm,rn */ 1693 { 0x200b, SETS1 | USES1 | USES2 }, /* or rm,rn */ 1694 { 0x200c, SETSSP | USES1 | USES2 }, /* cmp/str rm,rn */ 1695 { 0x200d, SETS1 | USES1 | USES2 }, /* xtrct rm,rn */ 1696 { 0x200e, SETSSP | USES1 | USES2 }, /* mulu.w rm,rn */ 1697 { 0x200f, SETSSP | USES1 | USES2 } /* muls.w rm,rn */ 1698 }; 1699 1700 static const struct sh_minor_opcode sh_opcode2[] = 1701 { 1702 { MAP (sh_opcode20), 0xf00f } 1703 }; 1704 1705 static const struct sh_opcode sh_opcode30[] = 1706 { 1707 { 0x3000, SETSSP | USES1 | USES2 }, /* cmp/eq rm,rn */ 1708 { 0x3002, SETSSP | USES1 | USES2 }, /* cmp/hs rm,rn */ 1709 { 0x3003, SETSSP | USES1 | USES2 }, /* cmp/ge rm,rn */ 1710 { 0x3004, SETSSP | USESSP | USES1 | USES2 }, /* div1 rm,rn */ 1711 { 0x3005, SETSSP | USES1 | USES2 }, /* dmulu.l rm,rn */ 1712 { 0x3006, SETSSP | USES1 | USES2 }, /* cmp/hi rm,rn */ 1713 { 0x3007, SETSSP | USES1 | USES2 }, /* cmp/gt rm,rn */ 1714 { 0x3008, SETS1 | USES1 | USES2 }, /* sub rm,rn */ 1715 { 0x300a, SETS1 | SETSSP | USES1 | USES2 | USESSP }, /* subc rm,rn */ 1716 { 0x300b, SETS1 | SETSSP | USES1 | USES2 }, /* subv rm,rn */ 1717 { 0x300c, SETS1 | USES1 | USES2 }, /* add rm,rn */ 1718 { 0x300d, SETSSP | USES1 | USES2 }, /* dmuls.l rm,rn */ 1719 { 0x300e, SETS1 | SETSSP | USES1 | USES2 | USESSP }, /* addc rm,rn */ 1720 { 0x300f, SETS1 | SETSSP | USES1 | USES2 } /* addv rm,rn */ 1721 }; 1722 1723 static const struct sh_minor_opcode sh_opcode3[] = 1724 { 1725 { MAP (sh_opcode30), 0xf00f } 1726 }; 1727 1728 static const struct sh_opcode sh_opcode40[] = 1729 { 1730 { 0x4000, SETS1 | SETSSP | USES1 }, /* shll rn */ 1731 { 0x4001, SETS1 | SETSSP | USES1 }, /* shlr rn */ 1732 { 0x4002, STORE | SETS1 | USES1 | USESSP }, /* sts.l mach,@-rn */ 1733 { 0x4004, SETS1 | SETSSP | USES1 }, /* rotl rn */ 1734 { 0x4005, SETS1 | SETSSP | USES1 }, /* rotr rn */ 1735 { 0x4006, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,mach */ 1736 { 0x4008, SETS1 | USES1 }, /* shll2 rn */ 1737 { 0x4009, SETS1 | USES1 }, /* shlr2 rn */ 1738 { 0x400a, SETSSP | USES1 }, /* lds rm,mach */ 1739 { 0x400b, BRANCH | DELAY | USES1 }, /* jsr @rn */ 1740 { 0x4010, SETS1 | SETSSP | USES1 }, /* dt rn */ 1741 { 0x4011, SETSSP | USES1 }, /* cmp/pz rn */ 1742 { 0x4012, STORE | SETS1 | USES1 | USESSP }, /* sts.l macl,@-rn */ 1743 { 0x4014, SETSSP | USES1 }, /* setrc rm */ 1744 { 0x4015, SETSSP | USES1 }, /* cmp/pl rn */ 1745 { 0x4016, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,macl */ 1746 { 0x4018, SETS1 | USES1 }, /* shll8 rn */ 1747 { 0x4019, SETS1 | USES1 }, /* shlr8 rn */ 1748 { 0x401a, SETSSP | USES1 }, /* lds rm,macl */ 1749 { 0x401b, LOAD | SETSSP | USES1 }, /* tas.b @rn */ 1750 { 0x4020, SETS1 | SETSSP | USES1 }, /* shal rn */ 1751 { 0x4021, SETS1 | SETSSP | USES1 }, /* shar rn */ 1752 { 0x4022, STORE | SETS1 | USES1 | USESSP }, /* sts.l pr,@-rn */ 1753 { 0x4024, SETS1 | SETSSP | USES1 | USESSP }, /* rotcl rn */ 1754 { 0x4025, SETS1 | SETSSP | USES1 | USESSP }, /* rotcr rn */ 1755 { 0x4026, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,pr */ 1756 { 0x4028, SETS1 | USES1 }, /* shll16 rn */ 1757 { 0x4029, SETS1 | USES1 }, /* shlr16 rn */ 1758 { 0x402a, SETSSP | USES1 }, /* lds rm,pr */ 1759 { 0x402b, BRANCH | DELAY | USES1 }, /* jmp @rn */ 1760 { 0x4052, STORE | SETS1 | USES1 | USESSP }, /* sts.l fpul,@-rn */ 1761 { 0x4056, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,fpul */ 1762 { 0x405a, SETSSP | USES1 }, /* lds.l rm,fpul */ 1763 { 0x4062, STORE | SETS1 | USES1 | USESSP }, /* sts.l fpscr / dsr,@-rn */ 1764 { 0x4066, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,fpscr / dsr */ 1765 { 0x406a, SETSSP | USES1 }, /* lds rm,fpscr / lds rm,dsr */ 1766 { 0x4072, STORE | SETS1 | USES1 | USESSP }, /* sts.l a0,@-rn */ 1767 { 0x4076, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,a0 */ 1768 { 0x407a, SETSSP | USES1 }, /* lds.l rm,a0 */ 1769 { 0x4082, STORE | SETS1 | USES1 | USESSP }, /* sts.l x0,@-rn */ 1770 { 0x4086, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,x0 */ 1771 { 0x408a, SETSSP | USES1 }, /* lds.l rm,x0 */ 1772 { 0x4092, STORE | SETS1 | USES1 | USESSP }, /* sts.l x1,@-rn */ 1773 { 0x4096, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,x1 */ 1774 { 0x409a, SETSSP | USES1 }, /* lds.l rm,x1 */ 1775 { 0x40a2, STORE | SETS1 | USES1 | USESSP }, /* sts.l y0,@-rn */ 1776 { 0x40a6, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,y0 */ 1777 { 0x40aa, SETSSP | USES1 }, /* lds.l rm,y0 */ 1778 { 0x40b2, STORE | SETS1 | USES1 | USESSP }, /* sts.l y1,@-rn */ 1779 { 0x40b6, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,y1 */ 1780 { 0x40ba, SETSSP | USES1 } /* lds.l rm,y1 */ 1781 }; 1782 1783 static const struct sh_opcode sh_opcode41[] = 1784 { 1785 { 0x4003, STORE | SETS1 | USES1 | USESSP }, /* stc.l <special_reg>,@-rn */ 1786 { 0x4007, LOAD | SETS1 | SETSSP | USES1 }, /* ldc.l @rm+,<special_reg> */ 1787 { 0x400c, SETS1 | USES1 | USES2 }, /* shad rm,rn */ 1788 { 0x400d, SETS1 | USES1 | USES2 }, /* shld rm,rn */ 1789 { 0x400e, SETSSP | USES1 }, /* ldc rm,<special_reg> */ 1790 { 0x400f, LOAD|SETS1|SETS2|SETSSP|USES1|USES2|USESSP }, /* mac.w @rm+,@rn+ */ 1791 }; 1792 1793 static const struct sh_minor_opcode sh_opcode4[] = 1794 { 1795 { MAP (sh_opcode40), 0xf0ff }, 1796 { MAP (sh_opcode41), 0xf00f } 1797 }; 1798 1799 static const struct sh_opcode sh_opcode50[] = 1800 { 1801 { 0x5000, LOAD | SETS1 | USES2 } /* mov.l @(disp,rm),rn */ 1802 }; 1803 1804 static const struct sh_minor_opcode sh_opcode5[] = 1805 { 1806 { MAP (sh_opcode50), 0xf000 } 1807 }; 1808 1809 static const struct sh_opcode sh_opcode60[] = 1810 { 1811 { 0x6000, LOAD | SETS1 | USES2 }, /* mov.b @rm,rn */ 1812 { 0x6001, LOAD | SETS1 | USES2 }, /* mov.w @rm,rn */ 1813 { 0x6002, LOAD | SETS1 | USES2 }, /* mov.l @rm,rn */ 1814 { 0x6003, SETS1 | USES2 }, /* mov rm,rn */ 1815 { 0x6004, LOAD | SETS1 | SETS2 | USES2 }, /* mov.b @rm+,rn */ 1816 { 0x6005, LOAD | SETS1 | SETS2 | USES2 }, /* mov.w @rm+,rn */ 1817 { 0x6006, LOAD | SETS1 | SETS2 | USES2 }, /* mov.l @rm+,rn */ 1818 { 0x6007, SETS1 | USES2 }, /* not rm,rn */ 1819 { 0x6008, SETS1 | USES2 }, /* swap.b rm,rn */ 1820 { 0x6009, SETS1 | USES2 }, /* swap.w rm,rn */ 1821 { 0x600a, SETS1 | SETSSP | USES2 | USESSP }, /* negc rm,rn */ 1822 { 0x600b, SETS1 | USES2 }, /* neg rm,rn */ 1823 { 0x600c, SETS1 | USES2 }, /* extu.b rm,rn */ 1824 { 0x600d, SETS1 | USES2 }, /* extu.w rm,rn */ 1825 { 0x600e, SETS1 | USES2 }, /* exts.b rm,rn */ 1826 { 0x600f, SETS1 | USES2 } /* exts.w rm,rn */ 1827 }; 1828 1829 static const struct sh_minor_opcode sh_opcode6[] = 1830 { 1831 { MAP (sh_opcode60), 0xf00f } 1832 }; 1833 1834 static const struct sh_opcode sh_opcode70[] = 1835 { 1836 { 0x7000, SETS1 | USES1 } /* add #imm,rn */ 1837 }; 1838 1839 static const struct sh_minor_opcode sh_opcode7[] = 1840 { 1841 { MAP (sh_opcode70), 0xf000 } 1842 }; 1843 1844 static const struct sh_opcode sh_opcode80[] = 1845 { 1846 { 0x8000, STORE | USES2 | USESR0 }, /* mov.b r0,@(disp,rn) */ 1847 { 0x8100, STORE | USES2 | USESR0 }, /* mov.w r0,@(disp,rn) */ 1848 { 0x8200, SETSSP }, /* setrc #imm */ 1849 { 0x8400, LOAD | SETSR0 | USES2 }, /* mov.b @(disp,rm),r0 */ 1850 { 0x8500, LOAD | SETSR0 | USES2 }, /* mov.w @(disp,rn),r0 */ 1851 { 0x8800, SETSSP | USESR0 }, /* cmp/eq #imm,r0 */ 1852 { 0x8900, BRANCH | USESSP }, /* bt label */ 1853 { 0x8b00, BRANCH | USESSP }, /* bf label */ 1854 { 0x8c00, SETSSP }, /* ldrs @(disp,pc) */ 1855 { 0x8d00, BRANCH | DELAY | USESSP }, /* bt/s label */ 1856 { 0x8e00, SETSSP }, /* ldre @(disp,pc) */ 1857 { 0x8f00, BRANCH | DELAY | USESSP } /* bf/s label */ 1858 }; 1859 1860 static const struct sh_minor_opcode sh_opcode8[] = 1861 { 1862 { MAP (sh_opcode80), 0xff00 } 1863 }; 1864 1865 static const struct sh_opcode sh_opcode90[] = 1866 { 1867 { 0x9000, LOAD | SETS1 } /* mov.w @(disp,pc),rn */ 1868 }; 1869 1870 static const struct sh_minor_opcode sh_opcode9[] = 1871 { 1872 { MAP (sh_opcode90), 0xf000 } 1873 }; 1874 1875 static const struct sh_opcode sh_opcodea0[] = 1876 { 1877 { 0xa000, BRANCH | DELAY } /* bra label */ 1878 }; 1879 1880 static const struct sh_minor_opcode sh_opcodea[] = 1881 { 1882 { MAP (sh_opcodea0), 0xf000 } 1883 }; 1884 1885 static const struct sh_opcode sh_opcodeb0[] = 1886 { 1887 { 0xb000, BRANCH | DELAY } /* bsr label */ 1888 }; 1889 1890 static const struct sh_minor_opcode sh_opcodeb[] = 1891 { 1892 { MAP (sh_opcodeb0), 0xf000 } 1893 }; 1894 1895 static const struct sh_opcode sh_opcodec0[] = 1896 { 1897 { 0xc000, STORE | USESR0 | USESSP }, /* mov.b r0,@(disp,gbr) */ 1898 { 0xc100, STORE | USESR0 | USESSP }, /* mov.w r0,@(disp,gbr) */ 1899 { 0xc200, STORE | USESR0 | USESSP }, /* mov.l r0,@(disp,gbr) */ 1900 { 0xc300, BRANCH | USESSP }, /* trapa #imm */ 1901 { 0xc400, LOAD | SETSR0 | USESSP }, /* mov.b @(disp,gbr),r0 */ 1902 { 0xc500, LOAD | SETSR0 | USESSP }, /* mov.w @(disp,gbr),r0 */ 1903 { 0xc600, LOAD | SETSR0 | USESSP }, /* mov.l @(disp,gbr),r0 */ 1904 { 0xc700, SETSR0 }, /* mova @(disp,pc),r0 */ 1905 { 0xc800, SETSSP | USESR0 }, /* tst #imm,r0 */ 1906 { 0xc900, SETSR0 | USESR0 }, /* and #imm,r0 */ 1907 { 0xca00, SETSR0 | USESR0 }, /* xor #imm,r0 */ 1908 { 0xcb00, SETSR0 | USESR0 }, /* or #imm,r0 */ 1909 { 0xcc00, LOAD | SETSSP | USESR0 | USESSP }, /* tst.b #imm,@(r0,gbr) */ 1910 { 0xcd00, LOAD | STORE | USESR0 | USESSP }, /* and.b #imm,@(r0,gbr) */ 1911 { 0xce00, LOAD | STORE | USESR0 | USESSP }, /* xor.b #imm,@(r0,gbr) */ 1912 { 0xcf00, LOAD | STORE | USESR0 | USESSP } /* or.b #imm,@(r0,gbr) */ 1913 }; 1914 1915 static const struct sh_minor_opcode sh_opcodec[] = 1916 { 1917 { MAP (sh_opcodec0), 0xff00 } 1918 }; 1919 1920 static const struct sh_opcode sh_opcoded0[] = 1921 { 1922 { 0xd000, LOAD | SETS1 } /* mov.l @(disp,pc),rn */ 1923 }; 1924 1925 static const struct sh_minor_opcode sh_opcoded[] = 1926 { 1927 { MAP (sh_opcoded0), 0xf000 } 1928 }; 1929 1930 static const struct sh_opcode sh_opcodee0[] = 1931 { 1932 { 0xe000, SETS1 } /* mov #imm,rn */ 1933 }; 1934 1935 static const struct sh_minor_opcode sh_opcodee[] = 1936 { 1937 { MAP (sh_opcodee0), 0xf000 } 1938 }; 1939 1940 static const struct sh_opcode sh_opcodef0[] = 1941 { 1942 { 0xf000, SETSF1 | USESF1 | USESF2 }, /* fadd fm,fn */ 1943 { 0xf001, SETSF1 | USESF1 | USESF2 }, /* fsub fm,fn */ 1944 { 0xf002, SETSF1 | USESF1 | USESF2 }, /* fmul fm,fn */ 1945 { 0xf003, SETSF1 | USESF1 | USESF2 }, /* fdiv fm,fn */ 1946 { 0xf004, SETSSP | USESF1 | USESF2 }, /* fcmp/eq fm,fn */ 1947 { 0xf005, SETSSP | USESF1 | USESF2 }, /* fcmp/gt fm,fn */ 1948 { 0xf006, LOAD | SETSF1 | USES2 | USESR0 }, /* fmov.s @(r0,rm),fn */ 1949 { 0xf007, STORE | USES1 | USESF2 | USESR0 }, /* fmov.s fm,@(r0,rn) */ 1950 { 0xf008, LOAD | SETSF1 | USES2 }, /* fmov.s @rm,fn */ 1951 { 0xf009, LOAD | SETS2 | SETSF1 | USES2 }, /* fmov.s @rm+,fn */ 1952 { 0xf00a, STORE | USES1 | USESF2 }, /* fmov.s fm,@rn */ 1953 { 0xf00b, STORE | SETS1 | USES1 | USESF2 }, /* fmov.s fm,@-rn */ 1954 { 0xf00c, SETSF1 | USESF2 }, /* fmov fm,fn */ 1955 { 0xf00e, SETSF1 | USESF1 | USESF2 | USESF0 } /* fmac f0,fm,fn */ 1956 }; 1957 1958 static const struct sh_opcode sh_opcodef1[] = 1959 { 1960 { 0xf00d, SETSF1 | USESSP }, /* fsts fpul,fn */ 1961 { 0xf01d, SETSSP | USESF1 }, /* flds fn,fpul */ 1962 { 0xf02d, SETSF1 | USESSP }, /* float fpul,fn */ 1963 { 0xf03d, SETSSP | USESF1 }, /* ftrc fn,fpul */ 1964 { 0xf04d, SETSF1 | USESF1 }, /* fneg fn */ 1965 { 0xf05d, SETSF1 | USESF1 }, /* fabs fn */ 1966 { 0xf06d, SETSF1 | USESF1 }, /* fsqrt fn */ 1967 { 0xf07d, SETSSP | USESF1 }, /* ftst/nan fn */ 1968 { 0xf08d, SETSF1 }, /* fldi0 fn */ 1969 { 0xf09d, SETSF1 } /* fldi1 fn */ 1970 }; 1971 1972 static const struct sh_minor_opcode sh_opcodef[] = 1973 { 1974 { MAP (sh_opcodef0), 0xf00f }, 1975 { MAP (sh_opcodef1), 0xf0ff } 1976 }; 1977 1978 static struct sh_major_opcode sh_opcodes[] = 1979 { 1980 { MAP (sh_opcode0) }, 1981 { MAP (sh_opcode1) }, 1982 { MAP (sh_opcode2) }, 1983 { MAP (sh_opcode3) }, 1984 { MAP (sh_opcode4) }, 1985 { MAP (sh_opcode5) }, 1986 { MAP (sh_opcode6) }, 1987 { MAP (sh_opcode7) }, 1988 { MAP (sh_opcode8) }, 1989 { MAP (sh_opcode9) }, 1990 { MAP (sh_opcodea) }, 1991 { MAP (sh_opcodeb) }, 1992 { MAP (sh_opcodec) }, 1993 { MAP (sh_opcoded) }, 1994 { MAP (sh_opcodee) }, 1995 { MAP (sh_opcodef) } 1996 }; 1997 1998 /* The double data transfer / parallel processing insns are not 1999 described here. This will cause sh_align_load_span to leave them alone. */ 2000 2001 static const struct sh_opcode sh_dsp_opcodef0[] = 2002 { 2003 { 0xf400, USESAS | SETSAS | LOAD | SETSSP }, /* movs.x @-as,ds */ 2004 { 0xf401, USESAS | SETSAS | STORE | USESSP }, /* movs.x ds,@-as */ 2005 { 0xf404, USESAS | LOAD | SETSSP }, /* movs.x @as,ds */ 2006 { 0xf405, USESAS | STORE | USESSP }, /* movs.x ds,@as */ 2007 { 0xf408, USESAS | SETSAS | LOAD | SETSSP }, /* movs.x @as+,ds */ 2008 { 0xf409, USESAS | SETSAS | STORE | USESSP }, /* movs.x ds,@as+ */ 2009 { 0xf40c, USESAS | SETSAS | LOAD | SETSSP | USESR8 }, /* movs.x @as+r8,ds */ 2010 { 0xf40d, USESAS | SETSAS | STORE | USESSP | USESR8 } /* movs.x ds,@as+r8 */ 2011 }; 2012 2013 static const struct sh_minor_opcode sh_dsp_opcodef[] = 2014 { 2015 { MAP (sh_dsp_opcodef0), 0xfc0d } 2016 }; 2017 2018 /* Given an instruction, return a pointer to the corresponding 2019 sh_opcode structure. Return NULL if the instruction is not 2020 recognized. */ 2021 2022 static const struct sh_opcode * 2023 sh_insn_info (unsigned int insn) 2024 { 2025 const struct sh_major_opcode *maj; 2026 const struct sh_minor_opcode *min, *minend; 2027 2028 maj = &sh_opcodes[(insn & 0xf000) >> 12]; 2029 min = maj->minor_opcodes; 2030 minend = min + maj->count; 2031 for (; min < minend; min++) 2032 { 2033 unsigned int l; 2034 const struct sh_opcode *op, *opend; 2035 2036 l = insn & min->mask; 2037 op = min->opcodes; 2038 opend = op + min->count; 2039 2040 /* Since the opcodes tables are sorted, we could use a binary 2041 search here if the count were above some cutoff value. */ 2042 for (; op < opend; op++) 2043 if (op->opcode == l) 2044 return op; 2045 } 2046 2047 return NULL; 2048 } 2049 2050 /* See whether an instruction uses a general purpose register. */ 2051 2052 static bfd_boolean 2053 sh_insn_uses_reg (unsigned int insn, 2054 const struct sh_opcode *op, 2055 unsigned int reg) 2056 { 2057 unsigned int f; 2058 2059 f = op->flags; 2060 2061 if ((f & USES1) != 0 2062 && USES1_REG (insn) == reg) 2063 return TRUE; 2064 if ((f & USES2) != 0 2065 && USES2_REG (insn) == reg) 2066 return TRUE; 2067 if ((f & USESR0) != 0 2068 && reg == 0) 2069 return TRUE; 2070 if ((f & USESAS) && reg == USESAS_REG (insn)) 2071 return TRUE; 2072 if ((f & USESR8) && reg == 8) 2073 return TRUE; 2074 2075 return FALSE; 2076 } 2077 2078 /* See whether an instruction sets a general purpose register. */ 2079 2080 static bfd_boolean 2081 sh_insn_sets_reg (unsigned int insn, 2082 const struct sh_opcode *op, 2083 unsigned int reg) 2084 { 2085 unsigned int f; 2086 2087 f = op->flags; 2088 2089 if ((f & SETS1) != 0 2090 && SETS1_REG (insn) == reg) 2091 return TRUE; 2092 if ((f & SETS2) != 0 2093 && SETS2_REG (insn) == reg) 2094 return TRUE; 2095 if ((f & SETSR0) != 0 2096 && reg == 0) 2097 return TRUE; 2098 if ((f & SETSAS) && reg == SETSAS_REG (insn)) 2099 return TRUE; 2100 2101 return FALSE; 2102 } 2103 2104 /* See whether an instruction uses or sets a general purpose register */ 2105 2106 static bfd_boolean 2107 sh_insn_uses_or_sets_reg (unsigned int insn, 2108 const struct sh_opcode *op, 2109 unsigned int reg) 2110 { 2111 if (sh_insn_uses_reg (insn, op, reg)) 2112 return TRUE; 2113 2114 return sh_insn_sets_reg (insn, op, reg); 2115 } 2116 2117 /* See whether an instruction uses a floating point register. */ 2118 2119 static bfd_boolean 2120 sh_insn_uses_freg (unsigned int insn, 2121 const struct sh_opcode *op, 2122 unsigned int freg) 2123 { 2124 unsigned int f; 2125 2126 f = op->flags; 2127 2128 /* We can't tell if this is a double-precision insn, so just play safe 2129 and assume that it might be. So not only have we test FREG against 2130 itself, but also even FREG against FREG+1 - if the using insn uses 2131 just the low part of a double precision value - but also an odd 2132 FREG against FREG-1 - if the setting insn sets just the low part 2133 of a double precision value. 2134 So what this all boils down to is that we have to ignore the lowest 2135 bit of the register number. */ 2136 2137 if ((f & USESF1) != 0 2138 && (USESF1_REG (insn) & 0xe) == (freg & 0xe)) 2139 return TRUE; 2140 if ((f & USESF2) != 0 2141 && (USESF2_REG (insn) & 0xe) == (freg & 0xe)) 2142 return TRUE; 2143 if ((f & USESF0) != 0 2144 && freg == 0) 2145 return TRUE; 2146 2147 return FALSE; 2148 } 2149 2150 /* See whether an instruction sets a floating point register. */ 2151 2152 static bfd_boolean 2153 sh_insn_sets_freg (unsigned int insn, 2154 const struct sh_opcode *op, 2155 unsigned int freg) 2156 { 2157 unsigned int f; 2158 2159 f = op->flags; 2160 2161 /* We can't tell if this is a double-precision insn, so just play safe 2162 and assume that it might be. So not only have we test FREG against 2163 itself, but also even FREG against FREG+1 - if the using insn uses 2164 just the low part of a double precision value - but also an odd 2165 FREG against FREG-1 - if the setting insn sets just the low part 2166 of a double precision value. 2167 So what this all boils down to is that we have to ignore the lowest 2168 bit of the register number. */ 2169 2170 if ((f & SETSF1) != 0 2171 && (SETSF1_REG (insn) & 0xe) == (freg & 0xe)) 2172 return TRUE; 2173 2174 return FALSE; 2175 } 2176 2177 /* See whether an instruction uses or sets a floating point register */ 2178 2179 static bfd_boolean 2180 sh_insn_uses_or_sets_freg (unsigned int insn, 2181 const struct sh_opcode *op, 2182 unsigned int reg) 2183 { 2184 if (sh_insn_uses_freg (insn, op, reg)) 2185 return TRUE; 2186 2187 return sh_insn_sets_freg (insn, op, reg); 2188 } 2189 2190 /* See whether instructions I1 and I2 conflict, assuming I1 comes 2191 before I2. OP1 and OP2 are the corresponding sh_opcode structures. 2192 This should return TRUE if there is a conflict, or FALSE if the 2193 instructions can be swapped safely. */ 2194 2195 static bfd_boolean 2196 sh_insns_conflict (unsigned int i1, 2197 const struct sh_opcode *op1, 2198 unsigned int i2, 2199 const struct sh_opcode *op2) 2200 { 2201 unsigned int f1, f2; 2202 2203 f1 = op1->flags; 2204 f2 = op2->flags; 2205 2206 /* Load of fpscr conflicts with floating point operations. 2207 FIXME: shouldn't test raw opcodes here. */ 2208 if (((i1 & 0xf0ff) == 0x4066 && (i2 & 0xf000) == 0xf000) 2209 || ((i2 & 0xf0ff) == 0x4066 && (i1 & 0xf000) == 0xf000)) 2210 return TRUE; 2211 2212 if ((f1 & (BRANCH | DELAY)) != 0 2213 || (f2 & (BRANCH | DELAY)) != 0) 2214 return TRUE; 2215 2216 if (((f1 | f2) & SETSSP) 2217 && (f1 & (SETSSP | USESSP)) 2218 && (f2 & (SETSSP | USESSP))) 2219 return TRUE; 2220 2221 if ((f1 & SETS1) != 0 2222 && sh_insn_uses_or_sets_reg (i2, op2, SETS1_REG (i1))) 2223 return TRUE; 2224 if ((f1 & SETS2) != 0 2225 && sh_insn_uses_or_sets_reg (i2, op2, SETS2_REG (i1))) 2226 return TRUE; 2227 if ((f1 & SETSR0) != 0 2228 && sh_insn_uses_or_sets_reg (i2, op2, 0)) 2229 return TRUE; 2230 if ((f1 & SETSAS) 2231 && sh_insn_uses_or_sets_reg (i2, op2, SETSAS_REG (i1))) 2232 return TRUE; 2233 if ((f1 & SETSF1) != 0 2234 && sh_insn_uses_or_sets_freg (i2, op2, SETSF1_REG (i1))) 2235 return TRUE; 2236 2237 if ((f2 & SETS1) != 0 2238 && sh_insn_uses_or_sets_reg (i1, op1, SETS1_REG (i2))) 2239 return TRUE; 2240 if ((f2 & SETS2) != 0 2241 && sh_insn_uses_or_sets_reg (i1, op1, SETS2_REG (i2))) 2242 return TRUE; 2243 if ((f2 & SETSR0) != 0 2244 && sh_insn_uses_or_sets_reg (i1, op1, 0)) 2245 return TRUE; 2246 if ((f2 & SETSAS) 2247 && sh_insn_uses_or_sets_reg (i1, op1, SETSAS_REG (i2))) 2248 return TRUE; 2249 if ((f2 & SETSF1) != 0 2250 && sh_insn_uses_or_sets_freg (i1, op1, SETSF1_REG (i2))) 2251 return TRUE; 2252 2253 /* The instructions do not conflict. */ 2254 return FALSE; 2255 } 2256 2257 /* I1 is a load instruction, and I2 is some other instruction. Return 2258 TRUE if I1 loads a register which I2 uses. */ 2259 2260 static bfd_boolean 2261 sh_load_use (unsigned int i1, 2262 const struct sh_opcode *op1, 2263 unsigned int i2, 2264 const struct sh_opcode *op2) 2265 { 2266 unsigned int f1; 2267 2268 f1 = op1->flags; 2269 2270 if ((f1 & LOAD) == 0) 2271 return FALSE; 2272 2273 /* If both SETS1 and SETSSP are set, that means a load to a special 2274 register using postincrement addressing mode, which we don't care 2275 about here. */ 2276 if ((f1 & SETS1) != 0 2277 && (f1 & SETSSP) == 0 2278 && sh_insn_uses_reg (i2, op2, (i1 & 0x0f00) >> 8)) 2279 return TRUE; 2280 2281 if ((f1 & SETSR0) != 0 2282 && sh_insn_uses_reg (i2, op2, 0)) 2283 return TRUE; 2284 2285 if ((f1 & SETSF1) != 0 2286 && sh_insn_uses_freg (i2, op2, (i1 & 0x0f00) >> 8)) 2287 return TRUE; 2288 2289 return FALSE; 2290 } 2291 2292 /* Try to align loads and stores within a span of memory. This is 2293 called by both the ELF and the COFF sh targets. ABFD and SEC are 2294 the BFD and section we are examining. CONTENTS is the contents of 2295 the section. SWAP is the routine to call to swap two instructions. 2296 RELOCS is a pointer to the internal relocation information, to be 2297 passed to SWAP. PLABEL is a pointer to the current label in a 2298 sorted list of labels; LABEL_END is the end of the list. START and 2299 STOP are the range of memory to examine. If a swap is made, 2300 *PSWAPPED is set to TRUE. */ 2301 2302 #ifdef COFF_WITH_PE 2303 static 2304 #endif 2305 bfd_boolean 2306 _bfd_sh_align_load_span (bfd *abfd, 2307 asection *sec, 2308 bfd_byte *contents, 2309 bfd_boolean (*swap) (bfd *, asection *, void *, bfd_byte *, bfd_vma), 2310 void * relocs, 2311 bfd_vma **plabel, 2312 bfd_vma *label_end, 2313 bfd_vma start, 2314 bfd_vma stop, 2315 bfd_boolean *pswapped) 2316 { 2317 int dsp = (abfd->arch_info->mach == bfd_mach_sh_dsp 2318 || abfd->arch_info->mach == bfd_mach_sh3_dsp); 2319 bfd_vma i; 2320 2321 /* The SH4 has a Harvard architecture, hence aligning loads is not 2322 desirable. In fact, it is counter-productive, since it interferes 2323 with the schedules generated by the compiler. */ 2324 if (abfd->arch_info->mach == bfd_mach_sh4) 2325 return TRUE; 2326 2327 /* If we are linking sh[3]-dsp code, swap the FPU instructions for DSP 2328 instructions. */ 2329 if (dsp) 2330 { 2331 sh_opcodes[0xf].minor_opcodes = sh_dsp_opcodef; 2332 sh_opcodes[0xf].count = sizeof sh_dsp_opcodef / sizeof sh_dsp_opcodef [0]; 2333 } 2334 2335 /* Instructions should be aligned on 2 byte boundaries. */ 2336 if ((start & 1) == 1) 2337 ++start; 2338 2339 /* Now look through the unaligned addresses. */ 2340 i = start; 2341 if ((i & 2) == 0) 2342 i += 2; 2343 for (; i < stop; i += 4) 2344 { 2345 unsigned int insn; 2346 const struct sh_opcode *op; 2347 unsigned int prev_insn = 0; 2348 const struct sh_opcode *prev_op = NULL; 2349 2350 insn = bfd_get_16 (abfd, contents + i); 2351 op = sh_insn_info (insn); 2352 if (op == NULL 2353 || (op->flags & (LOAD | STORE)) == 0) 2354 continue; 2355 2356 /* This is a load or store which is not on a four byte boundary. */ 2357 2358 while (*plabel < label_end && **plabel < i) 2359 ++*plabel; 2360 2361 if (i > start) 2362 { 2363 prev_insn = bfd_get_16 (abfd, contents + i - 2); 2364 /* If INSN is the field b of a parallel processing insn, it is not 2365 a load / store after all. Note that the test here might mistake 2366 the field_b of a pcopy insn for the starting code of a parallel 2367 processing insn; this might miss a swapping opportunity, but at 2368 least we're on the safe side. */ 2369 if (dsp && (prev_insn & 0xfc00) == 0xf800) 2370 continue; 2371 2372 /* Check if prev_insn is actually the field b of a parallel 2373 processing insn. Again, this can give a spurious match 2374 after a pcopy. */ 2375 if (dsp && i - 2 > start) 2376 { 2377 unsigned pprev_insn = bfd_get_16 (abfd, contents + i - 4); 2378 2379 if ((pprev_insn & 0xfc00) == 0xf800) 2380 prev_op = NULL; 2381 else 2382 prev_op = sh_insn_info (prev_insn); 2383 } 2384 else 2385 prev_op = sh_insn_info (prev_insn); 2386 2387 /* If the load/store instruction is in a delay slot, we 2388 can't swap. */ 2389 if (prev_op == NULL 2390 || (prev_op->flags & DELAY) != 0) 2391 continue; 2392 } 2393 if (i > start 2394 && (*plabel >= label_end || **plabel != i) 2395 && prev_op != NULL 2396 && (prev_op->flags & (LOAD | STORE)) == 0 2397 && ! sh_insns_conflict (prev_insn, prev_op, insn, op)) 2398 { 2399 bfd_boolean ok; 2400 2401 /* The load/store instruction does not have a label, and 2402 there is a previous instruction; PREV_INSN is not 2403 itself a load/store instruction, and PREV_INSN and 2404 INSN do not conflict. */ 2405 2406 ok = TRUE; 2407 2408 if (i >= start + 4) 2409 { 2410 unsigned int prev2_insn; 2411 const struct sh_opcode *prev2_op; 2412 2413 prev2_insn = bfd_get_16 (abfd, contents + i - 4); 2414 prev2_op = sh_insn_info (prev2_insn); 2415 2416 /* If the instruction before PREV_INSN has a delay 2417 slot--that is, PREV_INSN is in a delay slot--we 2418 can not swap. */ 2419 if (prev2_op == NULL 2420 || (prev2_op->flags & DELAY) != 0) 2421 ok = FALSE; 2422 2423 /* If the instruction before PREV_INSN is a load, 2424 and it sets a register which INSN uses, then 2425 putting INSN immediately after PREV_INSN will 2426 cause a pipeline bubble, so there is no point to 2427 making the swap. */ 2428 if (ok 2429 && (prev2_op->flags & LOAD) != 0 2430 && sh_load_use (prev2_insn, prev2_op, insn, op)) 2431 ok = FALSE; 2432 } 2433 2434 if (ok) 2435 { 2436 if (! (*swap) (abfd, sec, relocs, contents, i - 2)) 2437 return FALSE; 2438 *pswapped = TRUE; 2439 continue; 2440 } 2441 } 2442 2443 while (*plabel < label_end && **plabel < i + 2) 2444 ++*plabel; 2445 2446 if (i + 2 < stop 2447 && (*plabel >= label_end || **plabel != i + 2)) 2448 { 2449 unsigned int next_insn; 2450 const struct sh_opcode *next_op; 2451 2452 /* There is an instruction after the load/store 2453 instruction, and it does not have a label. */ 2454 next_insn = bfd_get_16 (abfd, contents + i + 2); 2455 next_op = sh_insn_info (next_insn); 2456 if (next_op != NULL 2457 && (next_op->flags & (LOAD | STORE)) == 0 2458 && ! sh_insns_conflict (insn, op, next_insn, next_op)) 2459 { 2460 bfd_boolean ok; 2461 2462 /* NEXT_INSN is not itself a load/store instruction, 2463 and it does not conflict with INSN. */ 2464 2465 ok = TRUE; 2466 2467 /* If PREV_INSN is a load, and it sets a register 2468 which NEXT_INSN uses, then putting NEXT_INSN 2469 immediately after PREV_INSN will cause a pipeline 2470 bubble, so there is no reason to make this swap. */ 2471 if (prev_op != NULL 2472 && (prev_op->flags & LOAD) != 0 2473 && sh_load_use (prev_insn, prev_op, next_insn, next_op)) 2474 ok = FALSE; 2475 2476 /* If INSN is a load, and it sets a register which 2477 the insn after NEXT_INSN uses, then doing the 2478 swap will cause a pipeline bubble, so there is no 2479 reason to make the swap. However, if the insn 2480 after NEXT_INSN is itself a load or store 2481 instruction, then it is misaligned, so 2482 optimistically hope that it will be swapped 2483 itself, and just live with the pipeline bubble if 2484 it isn't. */ 2485 if (ok 2486 && i + 4 < stop 2487 && (op->flags & LOAD) != 0) 2488 { 2489 unsigned int next2_insn; 2490 const struct sh_opcode *next2_op; 2491 2492 next2_insn = bfd_get_16 (abfd, contents + i + 4); 2493 next2_op = sh_insn_info (next2_insn); 2494 if (next2_op == NULL 2495 || ((next2_op->flags & (LOAD | STORE)) == 0 2496 && sh_load_use (insn, op, next2_insn, next2_op))) 2497 ok = FALSE; 2498 } 2499 2500 if (ok) 2501 { 2502 if (! (*swap) (abfd, sec, relocs, contents, i)) 2503 return FALSE; 2504 *pswapped = TRUE; 2505 continue; 2506 } 2507 } 2508 } 2509 } 2510 2511 return TRUE; 2512 } 2513 #endif /* not COFF_IMAGE_WITH_PE */ 2514 2515 /* Swap two SH instructions. */ 2516 2517 static bfd_boolean 2518 sh_swap_insns (bfd * abfd, 2519 asection * sec, 2520 void * relocs, 2521 bfd_byte * contents, 2522 bfd_vma addr) 2523 { 2524 struct internal_reloc *internal_relocs = (struct internal_reloc *) relocs; 2525 unsigned short i1, i2; 2526 struct internal_reloc *irel, *irelend; 2527 2528 /* Swap the instructions themselves. */ 2529 i1 = bfd_get_16 (abfd, contents + addr); 2530 i2 = bfd_get_16 (abfd, contents + addr + 2); 2531 bfd_put_16 (abfd, (bfd_vma) i2, contents + addr); 2532 bfd_put_16 (abfd, (bfd_vma) i1, contents + addr + 2); 2533 2534 /* Adjust all reloc addresses. */ 2535 irelend = internal_relocs + sec->reloc_count; 2536 for (irel = internal_relocs; irel < irelend; irel++) 2537 { 2538 int type, add; 2539 2540 /* There are a few special types of relocs that we don't want to 2541 adjust. These relocs do not apply to the instruction itself, 2542 but are only associated with the address. */ 2543 type = irel->r_type; 2544 if (type == R_SH_ALIGN 2545 || type == R_SH_CODE 2546 || type == R_SH_DATA 2547 || type == R_SH_LABEL) 2548 continue; 2549 2550 /* If an R_SH_USES reloc points to one of the addresses being 2551 swapped, we must adjust it. It would be incorrect to do this 2552 for a jump, though, since we want to execute both 2553 instructions after the jump. (We have avoided swapping 2554 around a label, so the jump will not wind up executing an 2555 instruction it shouldn't). */ 2556 if (type == R_SH_USES) 2557 { 2558 bfd_vma off; 2559 2560 off = irel->r_vaddr - sec->vma + 4 + irel->r_offset; 2561 if (off == addr) 2562 irel->r_offset += 2; 2563 else if (off == addr + 2) 2564 irel->r_offset -= 2; 2565 } 2566 2567 if (irel->r_vaddr - sec->vma == addr) 2568 { 2569 irel->r_vaddr += 2; 2570 add = -2; 2571 } 2572 else if (irel->r_vaddr - sec->vma == addr + 2) 2573 { 2574 irel->r_vaddr -= 2; 2575 add = 2; 2576 } 2577 else 2578 add = 0; 2579 2580 if (add != 0) 2581 { 2582 bfd_byte *loc; 2583 unsigned short insn, oinsn; 2584 bfd_boolean overflow; 2585 2586 loc = contents + irel->r_vaddr - sec->vma; 2587 overflow = FALSE; 2588 switch (type) 2589 { 2590 default: 2591 break; 2592 2593 case R_SH_PCDISP8BY2: 2594 case R_SH_PCRELIMM8BY2: 2595 insn = bfd_get_16 (abfd, loc); 2596 oinsn = insn; 2597 insn += add / 2; 2598 if ((oinsn & 0xff00) != (insn & 0xff00)) 2599 overflow = TRUE; 2600 bfd_put_16 (abfd, (bfd_vma) insn, loc); 2601 break; 2602 2603 case R_SH_PCDISP: 2604 insn = bfd_get_16 (abfd, loc); 2605 oinsn = insn; 2606 insn += add / 2; 2607 if ((oinsn & 0xf000) != (insn & 0xf000)) 2608 overflow = TRUE; 2609 bfd_put_16 (abfd, (bfd_vma) insn, loc); 2610 break; 2611 2612 case R_SH_PCRELIMM8BY4: 2613 /* This reloc ignores the least significant 3 bits of 2614 the program counter before adding in the offset. 2615 This means that if ADDR is at an even address, the 2616 swap will not affect the offset. If ADDR is an at an 2617 odd address, then the instruction will be crossing a 2618 four byte boundary, and must be adjusted. */ 2619 if ((addr & 3) != 0) 2620 { 2621 insn = bfd_get_16 (abfd, loc); 2622 oinsn = insn; 2623 insn += add / 2; 2624 if ((oinsn & 0xff00) != (insn & 0xff00)) 2625 overflow = TRUE; 2626 bfd_put_16 (abfd, (bfd_vma) insn, loc); 2627 } 2628 2629 break; 2630 } 2631 2632 if (overflow) 2633 { 2634 ((*_bfd_error_handler) 2635 ("%B: 0x%lx: fatal: reloc overflow while relaxing", 2636 abfd, (unsigned long) irel->r_vaddr)); 2637 bfd_set_error (bfd_error_bad_value); 2638 return FALSE; 2639 } 2640 } 2641 } 2642 2643 return TRUE; 2644 } 2645 2646 /* Look for loads and stores which we can align to four byte 2647 boundaries. See the longer comment above sh_relax_section for why 2648 this is desirable. This sets *PSWAPPED if some instruction was 2649 swapped. */ 2650 2651 static bfd_boolean 2652 sh_align_loads (bfd *abfd, 2653 asection *sec, 2654 struct internal_reloc *internal_relocs, 2655 bfd_byte *contents, 2656 bfd_boolean *pswapped) 2657 { 2658 struct internal_reloc *irel, *irelend; 2659 bfd_vma *labels = NULL; 2660 bfd_vma *label, *label_end; 2661 bfd_size_type amt; 2662 2663 *pswapped = FALSE; 2664 2665 irelend = internal_relocs + sec->reloc_count; 2666 2667 /* Get all the addresses with labels on them. */ 2668 amt = (bfd_size_type) sec->reloc_count * sizeof (bfd_vma); 2669 labels = (bfd_vma *) bfd_malloc (amt); 2670 if (labels == NULL) 2671 goto error_return; 2672 label_end = labels; 2673 for (irel = internal_relocs; irel < irelend; irel++) 2674 { 2675 if (irel->r_type == R_SH_LABEL) 2676 { 2677 *label_end = irel->r_vaddr - sec->vma; 2678 ++label_end; 2679 } 2680 } 2681 2682 /* Note that the assembler currently always outputs relocs in 2683 address order. If that ever changes, this code will need to sort 2684 the label values and the relocs. */ 2685 2686 label = labels; 2687 2688 for (irel = internal_relocs; irel < irelend; irel++) 2689 { 2690 bfd_vma start, stop; 2691 2692 if (irel->r_type != R_SH_CODE) 2693 continue; 2694 2695 start = irel->r_vaddr - sec->vma; 2696 2697 for (irel++; irel < irelend; irel++) 2698 if (irel->r_type == R_SH_DATA) 2699 break; 2700 if (irel < irelend) 2701 stop = irel->r_vaddr - sec->vma; 2702 else 2703 stop = sec->size; 2704 2705 if (! _bfd_sh_align_load_span (abfd, sec, contents, sh_swap_insns, 2706 internal_relocs, &label, 2707 label_end, start, stop, pswapped)) 2708 goto error_return; 2709 } 2710 2711 free (labels); 2712 2713 return TRUE; 2714 2715 error_return: 2716 if (labels != NULL) 2717 free (labels); 2718 return FALSE; 2719 } 2720 2721 /* This is a modification of _bfd_coff_generic_relocate_section, which 2723 will handle SH relaxing. */ 2724 2725 static bfd_boolean 2726 sh_relocate_section (bfd *output_bfd ATTRIBUTE_UNUSED, 2727 struct bfd_link_info *info, 2728 bfd *input_bfd, 2729 asection *input_section, 2730 bfd_byte *contents, 2731 struct internal_reloc *relocs, 2732 struct internal_syment *syms, 2733 asection **sections) 2734 { 2735 struct internal_reloc *rel; 2736 struct internal_reloc *relend; 2737 2738 rel = relocs; 2739 relend = rel + input_section->reloc_count; 2740 for (; rel < relend; rel++) 2741 { 2742 long symndx; 2743 struct coff_link_hash_entry *h; 2744 struct internal_syment *sym; 2745 bfd_vma addend; 2746 bfd_vma val; 2747 reloc_howto_type *howto; 2748 bfd_reloc_status_type rstat; 2749 2750 /* Almost all relocs have to do with relaxing. If any work must 2751 be done for them, it has been done in sh_relax_section. */ 2752 if (rel->r_type != R_SH_IMM32 2753 #ifdef COFF_WITH_PE 2754 && rel->r_type != R_SH_IMM32CE 2755 && rel->r_type != R_SH_IMAGEBASE 2756 #endif 2757 && rel->r_type != R_SH_PCDISP) 2758 continue; 2759 2760 symndx = rel->r_symndx; 2761 2762 if (symndx == -1) 2763 { 2764 h = NULL; 2765 sym = NULL; 2766 } 2767 else 2768 { 2769 if (symndx < 0 2770 || (unsigned long) symndx >= obj_raw_syment_count (input_bfd)) 2771 { 2772 (*_bfd_error_handler) 2773 ("%B: illegal symbol index %ld in relocs", 2774 input_bfd, symndx); 2775 bfd_set_error (bfd_error_bad_value); 2776 return FALSE; 2777 } 2778 h = obj_coff_sym_hashes (input_bfd)[symndx]; 2779 sym = syms + symndx; 2780 } 2781 2782 if (sym != NULL && sym->n_scnum != 0) 2783 addend = - sym->n_value; 2784 else 2785 addend = 0; 2786 2787 if (rel->r_type == R_SH_PCDISP) 2788 addend -= 4; 2789 2790 if (rel->r_type >= SH_COFF_HOWTO_COUNT) 2791 howto = NULL; 2792 else 2793 howto = &sh_coff_howtos[rel->r_type]; 2794 2795 if (howto == NULL) 2796 { 2797 bfd_set_error (bfd_error_bad_value); 2798 return FALSE; 2799 } 2800 2801 #ifdef COFF_WITH_PE 2802 if (rel->r_type == R_SH_IMAGEBASE) 2803 addend -= pe_data (input_section->output_section->owner)->pe_opthdr.ImageBase; 2804 #endif 2805 2806 val = 0; 2807 2808 if (h == NULL) 2809 { 2810 asection *sec; 2811 2812 /* There is nothing to do for an internal PCDISP reloc. */ 2813 if (rel->r_type == R_SH_PCDISP) 2814 continue; 2815 2816 if (symndx == -1) 2817 { 2818 sec = bfd_abs_section_ptr; 2819 val = 0; 2820 } 2821 else 2822 { 2823 sec = sections[symndx]; 2824 val = (sec->output_section->vma 2825 + sec->output_offset 2826 + sym->n_value 2827 - sec->vma); 2828 } 2829 } 2830 else 2831 { 2832 if (h->root.type == bfd_link_hash_defined 2833 || h->root.type == bfd_link_hash_defweak) 2834 { 2835 asection *sec; 2836 2837 sec = h->root.u.def.section; 2838 val = (h->root.u.def.value 2839 + sec->output_section->vma 2840 + sec->output_offset); 2841 } 2842 else if (! bfd_link_relocatable (info)) 2843 (*info->callbacks->undefined_symbol) 2844 (info, h->root.root.string, input_bfd, input_section, 2845 rel->r_vaddr - input_section->vma, TRUE); 2846 } 2847 2848 rstat = _bfd_final_link_relocate (howto, input_bfd, input_section, 2849 contents, 2850 rel->r_vaddr - input_section->vma, 2851 val, addend); 2852 2853 switch (rstat) 2854 { 2855 default: 2856 abort (); 2857 case bfd_reloc_ok: 2858 break; 2859 case bfd_reloc_overflow: 2860 { 2861 const char *name; 2862 char buf[SYMNMLEN + 1]; 2863 2864 if (symndx == -1) 2865 name = "*ABS*"; 2866 else if (h != NULL) 2867 name = NULL; 2868 else if (sym->_n._n_n._n_zeroes == 0 2869 && sym->_n._n_n._n_offset != 0) 2870 name = obj_coff_strings (input_bfd) + sym->_n._n_n._n_offset; 2871 else 2872 { 2873 strncpy (buf, sym->_n._n_name, SYMNMLEN); 2874 buf[SYMNMLEN] = '\0'; 2875 name = buf; 2876 } 2877 2878 (*info->callbacks->reloc_overflow) 2879 (info, (h ? &h->root : NULL), name, howto->name, 2880 (bfd_vma) 0, input_bfd, input_section, 2881 rel->r_vaddr - input_section->vma); 2882 } 2883 } 2884 } 2885 2886 return TRUE; 2887 } 2888 2889 /* This is a version of bfd_generic_get_relocated_section_contents 2890 which uses sh_relocate_section. */ 2891 2892 static bfd_byte * 2893 sh_coff_get_relocated_section_contents (bfd *output_bfd, 2894 struct bfd_link_info *link_info, 2895 struct bfd_link_order *link_order, 2896 bfd_byte *data, 2897 bfd_boolean relocatable, 2898 asymbol **symbols) 2899 { 2900 asection *input_section = link_order->u.indirect.section; 2901 bfd *input_bfd = input_section->owner; 2902 asection **sections = NULL; 2903 struct internal_reloc *internal_relocs = NULL; 2904 struct internal_syment *internal_syms = NULL; 2905 2906 /* We only need to handle the case of relaxing, or of having a 2907 particular set of section contents, specially. */ 2908 if (relocatable 2909 || coff_section_data (input_bfd, input_section) == NULL 2910 || coff_section_data (input_bfd, input_section)->contents == NULL) 2911 return bfd_generic_get_relocated_section_contents (output_bfd, link_info, 2912 link_order, data, 2913 relocatable, 2914 symbols); 2915 2916 memcpy (data, coff_section_data (input_bfd, input_section)->contents, 2917 (size_t) input_section->size); 2918 2919 if ((input_section->flags & SEC_RELOC) != 0 2920 && input_section->reloc_count > 0) 2921 { 2922 bfd_size_type symesz = bfd_coff_symesz (input_bfd); 2923 bfd_byte *esym, *esymend; 2924 struct internal_syment *isymp; 2925 asection **secpp; 2926 bfd_size_type amt; 2927 2928 if (! _bfd_coff_get_external_symbols (input_bfd)) 2929 goto error_return; 2930 2931 internal_relocs = (_bfd_coff_read_internal_relocs 2932 (input_bfd, input_section, FALSE, (bfd_byte *) NULL, 2933 FALSE, (struct internal_reloc *) NULL)); 2934 if (internal_relocs == NULL) 2935 goto error_return; 2936 2937 amt = obj_raw_syment_count (input_bfd); 2938 amt *= sizeof (struct internal_syment); 2939 internal_syms = (struct internal_syment *) bfd_malloc (amt); 2940 if (internal_syms == NULL) 2941 goto error_return; 2942 2943 amt = obj_raw_syment_count (input_bfd); 2944 amt *= sizeof (asection *); 2945 sections = (asection **) bfd_malloc (amt); 2946 if (sections == NULL) 2947 goto error_return; 2948 2949 isymp = internal_syms; 2950 secpp = sections; 2951 esym = (bfd_byte *) obj_coff_external_syms (input_bfd); 2952 esymend = esym + obj_raw_syment_count (input_bfd) * symesz; 2953 while (esym < esymend) 2954 { 2955 bfd_coff_swap_sym_in (input_bfd, esym, isymp); 2956 2957 if (isymp->n_scnum != 0) 2958 *secpp = coff_section_from_bfd_index (input_bfd, isymp->n_scnum); 2959 else 2960 { 2961 if (isymp->n_value == 0) 2962 *secpp = bfd_und_section_ptr; 2963 else 2964 *secpp = bfd_com_section_ptr; 2965 } 2966 2967 esym += (isymp->n_numaux + 1) * symesz; 2968 secpp += isymp->n_numaux + 1; 2969 isymp += isymp->n_numaux + 1; 2970 } 2971 2972 if (! sh_relocate_section (output_bfd, link_info, input_bfd, 2973 input_section, data, internal_relocs, 2974 internal_syms, sections)) 2975 goto error_return; 2976 2977 free (sections); 2978 sections = NULL; 2979 free (internal_syms); 2980 internal_syms = NULL; 2981 free (internal_relocs); 2982 internal_relocs = NULL; 2983 } 2984 2985 return data; 2986 2987 error_return: 2988 if (internal_relocs != NULL) 2989 free (internal_relocs); 2990 if (internal_syms != NULL) 2991 free (internal_syms); 2992 if (sections != NULL) 2993 free (sections); 2994 return NULL; 2995 } 2996 2997 /* The target vectors. */ 2998 2999 #ifndef TARGET_SHL_SYM 3000 CREATE_BIG_COFF_TARGET_VEC (sh_coff_vec, "coff-sh", BFD_IS_RELAXABLE, 0, '_', NULL, COFF_SWAP_TABLE) 3001 #endif 3002 3003 #ifdef TARGET_SHL_SYM 3004 #define TARGET_SYM TARGET_SHL_SYM 3005 #else 3006 #define TARGET_SYM sh_coff_le_vec 3007 #endif 3008 3009 #ifndef TARGET_SHL_NAME 3010 #define TARGET_SHL_NAME "coff-shl" 3011 #endif 3012 3013 #ifdef COFF_WITH_PE 3014 CREATE_LITTLE_COFF_TARGET_VEC (TARGET_SYM, TARGET_SHL_NAME, BFD_IS_RELAXABLE, 3015 SEC_CODE | SEC_DATA, '_', NULL, COFF_SWAP_TABLE); 3016 #else 3017 CREATE_LITTLE_COFF_TARGET_VEC (TARGET_SYM, TARGET_SHL_NAME, BFD_IS_RELAXABLE, 3018 0, '_', NULL, COFF_SWAP_TABLE) 3019 #endif 3020 3021 #ifndef TARGET_SHL_SYM 3022 3023 /* Some people want versions of the SH COFF target which do not align 3024 to 16 byte boundaries. We implement that by adding a couple of new 3025 target vectors. These are just like the ones above, but they 3026 change the default section alignment. To generate them in the 3027 assembler, use -small. To use them in the linker, use -b 3028 coff-sh{l}-small and -oformat coff-sh{l}-small. 3029 3030 Yes, this is a horrible hack. A general solution for setting 3031 section alignment in COFF is rather complex. ELF handles this 3032 correctly. */ 3033 3034 /* Only recognize the small versions if the target was not defaulted. 3035 Otherwise we won't recognize the non default endianness. */ 3036 3037 static const bfd_target * 3038 coff_small_object_p (bfd *abfd) 3039 { 3040 if (abfd->target_defaulted) 3041 { 3042 bfd_set_error (bfd_error_wrong_format); 3043 return NULL; 3044 } 3045 return coff_object_p (abfd); 3046 } 3047 3048 /* Set the section alignment for the small versions. */ 3049 3050 static bfd_boolean 3051 coff_small_new_section_hook (bfd *abfd, asection *section) 3052 { 3053 if (! coff_new_section_hook (abfd, section)) 3054 return FALSE; 3055 3056 /* We must align to at least a four byte boundary, because longword 3057 accesses must be on a four byte boundary. */ 3058 if (section->alignment_power == COFF_DEFAULT_SECTION_ALIGNMENT_POWER) 3059 section->alignment_power = 2; 3060 3061 return TRUE; 3062 } 3063 3064 /* This is copied from bfd_coff_std_swap_table so that we can change 3065 the default section alignment power. */ 3066 3067 static bfd_coff_backend_data bfd_coff_small_swap_table = 3068 { 3069 coff_swap_aux_in, coff_swap_sym_in, coff_swap_lineno_in, 3070 coff_swap_aux_out, coff_swap_sym_out, 3071 coff_swap_lineno_out, coff_swap_reloc_out, 3072 coff_swap_filehdr_out, coff_swap_aouthdr_out, 3073 coff_swap_scnhdr_out, 3074 FILHSZ, AOUTSZ, SCNHSZ, SYMESZ, AUXESZ, RELSZ, LINESZ, FILNMLEN, 3075 #ifdef COFF_LONG_FILENAMES 3076 TRUE, 3077 #else 3078 FALSE, 3079 #endif 3080 COFF_DEFAULT_LONG_SECTION_NAMES, 3081 2, 3082 #ifdef COFF_FORCE_SYMBOLS_IN_STRINGS 3083 TRUE, 3084 #else 3085 FALSE, 3086 #endif 3087 #ifdef COFF_DEBUG_STRING_WIDE_PREFIX 3088 4, 3089 #else 3090 2, 3091 #endif 3092 32768, 3093 coff_swap_filehdr_in, coff_swap_aouthdr_in, coff_swap_scnhdr_in, 3094 coff_swap_reloc_in, coff_bad_format_hook, coff_set_arch_mach_hook, 3095 coff_mkobject_hook, styp_to_sec_flags, coff_set_alignment_hook, 3096 coff_slurp_symbol_table, symname_in_debug_hook, coff_pointerize_aux_hook, 3097 coff_print_aux, coff_reloc16_extra_cases, coff_reloc16_estimate, 3098 coff_classify_symbol, coff_compute_section_file_positions, 3099 coff_start_final_link, coff_relocate_section, coff_rtype_to_howto, 3100 coff_adjust_symndx, coff_link_add_one_symbol, 3101 coff_link_output_has_begun, coff_final_link_postscript, 3102 bfd_pe_print_pdata 3103 }; 3104 3105 #define coff_small_close_and_cleanup \ 3106 coff_close_and_cleanup 3107 #define coff_small_bfd_free_cached_info \ 3108 coff_bfd_free_cached_info 3109 #define coff_small_get_section_contents \ 3110 coff_get_section_contents 3111 #define coff_small_get_section_contents_in_window \ 3112 coff_get_section_contents_in_window 3113 3114 extern const bfd_target sh_coff_small_le_vec; 3115 3116 const bfd_target sh_coff_small_vec = 3117 { 3118 "coff-sh-small", /* name */ 3119 bfd_target_coff_flavour, 3120 BFD_ENDIAN_BIG, /* data byte order is big */ 3121 BFD_ENDIAN_BIG, /* header byte order is big */ 3122 3123 (HAS_RELOC | EXEC_P | /* object flags */ 3124 HAS_LINENO | HAS_DEBUG | 3125 HAS_SYMS | HAS_LOCALS | WP_TEXT | BFD_IS_RELAXABLE), 3126 3127 (SEC_HAS_CONTENTS | SEC_ALLOC | SEC_LOAD | SEC_RELOC), 3128 '_', /* leading symbol underscore */ 3129 '/', /* ar_pad_char */ 3130 15, /* ar_max_namelen */ 3131 0, /* match priority. */ 3132 bfd_getb64, bfd_getb_signed_64, bfd_putb64, 3133 bfd_getb32, bfd_getb_signed_32, bfd_putb32, 3134 bfd_getb16, bfd_getb_signed_16, bfd_putb16, /* data */ 3135 bfd_getb64, bfd_getb_signed_64, bfd_putb64, 3136 bfd_getb32, bfd_getb_signed_32, bfd_putb32, 3137 bfd_getb16, bfd_getb_signed_16, bfd_putb16, /* hdrs */ 3138 3139 {_bfd_dummy_target, coff_small_object_p, /* bfd_check_format */ 3140 bfd_generic_archive_p, _bfd_dummy_target}, 3141 {bfd_false, coff_mkobject, _bfd_generic_mkarchive, /* bfd_set_format */ 3142 bfd_false}, 3143 {bfd_false, coff_write_object_contents, /* bfd_write_contents */ 3144 _bfd_write_archive_contents, bfd_false}, 3145 3146 BFD_JUMP_TABLE_GENERIC (coff_small), 3147 BFD_JUMP_TABLE_COPY (coff), 3148 BFD_JUMP_TABLE_CORE (_bfd_nocore), 3149 BFD_JUMP_TABLE_ARCHIVE (_bfd_archive_coff), 3150 BFD_JUMP_TABLE_SYMBOLS (coff), 3151 BFD_JUMP_TABLE_RELOCS (coff), 3152 BFD_JUMP_TABLE_WRITE (coff), 3153 BFD_JUMP_TABLE_LINK (coff), 3154 BFD_JUMP_TABLE_DYNAMIC (_bfd_nodynamic), 3155 3156 & sh_coff_small_le_vec, 3157 3158 & bfd_coff_small_swap_table 3159 }; 3160 3161 const bfd_target sh_coff_small_le_vec = 3162 { 3163 "coff-shl-small", /* name */ 3164 bfd_target_coff_flavour, 3165 BFD_ENDIAN_LITTLE, /* data byte order is little */ 3166 BFD_ENDIAN_LITTLE, /* header byte order is little endian too*/ 3167 3168 (HAS_RELOC | EXEC_P | /* object flags */ 3169 HAS_LINENO | HAS_DEBUG | 3170 HAS_SYMS | HAS_LOCALS | WP_TEXT | BFD_IS_RELAXABLE), 3171 3172 (SEC_HAS_CONTENTS | SEC_ALLOC | SEC_LOAD | SEC_RELOC), 3173 '_', /* leading symbol underscore */ 3174 '/', /* ar_pad_char */ 3175 15, /* ar_max_namelen */ 3176 0, /* match priority. */ 3177 bfd_getl64, bfd_getl_signed_64, bfd_putl64, 3178 bfd_getl32, bfd_getl_signed_32, bfd_putl32, 3179 bfd_getl16, bfd_getl_signed_16, bfd_putl16, /* data */ 3180 bfd_getl64, bfd_getl_signed_64, bfd_putl64, 3181 bfd_getl32, bfd_getl_signed_32, bfd_putl32, 3182 bfd_getl16, bfd_getl_signed_16, bfd_putl16, /* hdrs */ 3183 3184 {_bfd_dummy_target, coff_small_object_p, /* bfd_check_format */ 3185 bfd_generic_archive_p, _bfd_dummy_target}, 3186 {bfd_false, coff_mkobject, _bfd_generic_mkarchive, /* bfd_set_format */ 3187 bfd_false}, 3188 {bfd_false, coff_write_object_contents, /* bfd_write_contents */ 3189 _bfd_write_archive_contents, bfd_false}, 3190 3191 BFD_JUMP_TABLE_GENERIC (coff_small), 3192 BFD_JUMP_TABLE_COPY (coff), 3193 BFD_JUMP_TABLE_CORE (_bfd_nocore), 3194 BFD_JUMP_TABLE_ARCHIVE (_bfd_archive_coff), 3195 BFD_JUMP_TABLE_SYMBOLS (coff), 3196 BFD_JUMP_TABLE_RELOCS (coff), 3197 BFD_JUMP_TABLE_WRITE (coff), 3198 BFD_JUMP_TABLE_LINK (coff), 3199 BFD_JUMP_TABLE_DYNAMIC (_bfd_nodynamic), 3200 3201 & sh_coff_small_vec, 3202 3203 & bfd_coff_small_swap_table 3204 }; 3205 #endif 3206
