1 /* 2 * Copyright 2010 Jerome Glisse <glisse (at) freedesktop.org> 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * on the rights to use, copy, modify, merge, publish, distribute, sub 8 * license, and/or sell copies of the Software, and to permit persons to whom 9 * the Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 21 * USE OR OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Jerome Glisse 25 */ 26 #ifndef SI_PIPE_H 27 #define SI_PIPE_H 28 29 #include "si_shader.h" 30 31 #ifdef PIPE_ARCH_BIG_ENDIAN 32 #define SI_BIG_ENDIAN 1 33 #else 34 #define SI_BIG_ENDIAN 0 35 #endif 36 37 /* The base vertex and primitive restart can be any number, but we must pick 38 * one which will mean "unknown" for the purpose of state tracking and 39 * the number shouldn't be a commonly-used one. */ 40 #define SI_BASE_VERTEX_UNKNOWN INT_MIN 41 #define SI_RESTART_INDEX_UNKNOWN INT_MIN 42 #define SI_NUM_SMOOTH_AA_SAMPLES 8 43 #define SI_GS_PER_ES 128 44 45 /* Instruction cache. */ 46 #define SI_CONTEXT_INV_ICACHE (R600_CONTEXT_PRIVATE_FLAG << 0) 47 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */ 48 #define SI_CONTEXT_INV_SMEM_L1 (R600_CONTEXT_PRIVATE_FLAG << 1) 49 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */ 50 #define SI_CONTEXT_INV_VMEM_L1 (R600_CONTEXT_PRIVATE_FLAG << 2) 51 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */ 52 #define SI_CONTEXT_INV_GLOBAL_L2 (R600_CONTEXT_PRIVATE_FLAG << 3) 53 /* Write dirty L2 lines back to memory (shader and CP DMA stores), but don't 54 * invalidate L2. SI-CIK can't do it, so they will do complete invalidation. */ 55 #define SI_CONTEXT_WRITEBACK_GLOBAL_L2 (R600_CONTEXT_PRIVATE_FLAG << 4) 56 /* Framebuffer caches. */ 57 #define SI_CONTEXT_FLUSH_AND_INV_CB_META (R600_CONTEXT_PRIVATE_FLAG << 5) 58 #define SI_CONTEXT_FLUSH_AND_INV_DB_META (R600_CONTEXT_PRIVATE_FLAG << 6) 59 #define SI_CONTEXT_FLUSH_AND_INV_DB (R600_CONTEXT_PRIVATE_FLAG << 7) 60 #define SI_CONTEXT_FLUSH_AND_INV_CB (R600_CONTEXT_PRIVATE_FLAG << 8) 61 /* Engine synchronization. */ 62 #define SI_CONTEXT_VS_PARTIAL_FLUSH (R600_CONTEXT_PRIVATE_FLAG << 9) 63 #define SI_CONTEXT_PS_PARTIAL_FLUSH (R600_CONTEXT_PRIVATE_FLAG << 10) 64 #define SI_CONTEXT_CS_PARTIAL_FLUSH (R600_CONTEXT_PRIVATE_FLAG << 11) 65 #define SI_CONTEXT_VGT_FLUSH (R600_CONTEXT_PRIVATE_FLAG << 12) 66 #define SI_CONTEXT_VGT_STREAMOUT_SYNC (R600_CONTEXT_PRIVATE_FLAG << 13) 67 68 #define SI_CONTEXT_FLUSH_AND_INV_FRAMEBUFFER (SI_CONTEXT_FLUSH_AND_INV_CB | \ 69 SI_CONTEXT_FLUSH_AND_INV_CB_META | \ 70 SI_CONTEXT_FLUSH_AND_INV_DB | \ 71 SI_CONTEXT_FLUSH_AND_INV_DB_META) 72 73 #define SI_MAX_BORDER_COLORS 4096 74 75 struct si_compute; 76 struct hash_table; 77 struct u_suballocator; 78 79 struct si_screen { 80 struct r600_common_screen b; 81 unsigned gs_table_depth; 82 unsigned tess_offchip_block_dw_size; 83 bool has_distributed_tess; 84 bool has_draw_indirect_multi; 85 bool has_ds_bpermute; 86 87 /* Whether shaders are monolithic (1-part) or separate (3-part). */ 88 bool use_monolithic_shaders; 89 bool record_llvm_ir; 90 91 pipe_mutex shader_parts_mutex; 92 struct si_shader_part *vs_prologs; 93 struct si_shader_part *vs_epilogs; 94 struct si_shader_part *tcs_epilogs; 95 struct si_shader_part *gs_prologs; 96 struct si_shader_part *ps_prologs; 97 struct si_shader_part *ps_epilogs; 98 99 /* Shader cache in memory. 100 * 101 * Design & limitations: 102 * - The shader cache is per screen (= per process), never saved to 103 * disk, and skips redundant shader compilations from TGSI to bytecode. 104 * - It can only be used with one-variant-per-shader support, in which 105 * case only the main (typically middle) part of shaders is cached. 106 * - Only VS, TCS, TES, PS are cached, out of which only the hw VS 107 * variants of VS and TES are cached, so LS and ES aren't. 108 * - GS and CS aren't cached, but it's certainly possible to cache 109 * those as well. 110 */ 111 pipe_mutex shader_cache_mutex; 112 struct hash_table *shader_cache; 113 114 /* Shader compiler queue for multithreaded compilation. */ 115 struct util_queue shader_compiler_queue; 116 LLVMTargetMachineRef tm[4]; /* used by the queue only */ 117 }; 118 119 struct si_blend_color { 120 struct r600_atom atom; 121 struct pipe_blend_color state; 122 }; 123 124 struct si_sampler_view { 125 struct pipe_sampler_view base; 126 /* [0..7] = image descriptor 127 * [4..7] = buffer descriptor */ 128 uint32_t state[8]; 129 uint32_t fmask_state[8]; 130 const struct radeon_surf_level *base_level_info; 131 unsigned base_level; 132 unsigned block_width; 133 bool is_stencil_sampler; 134 }; 135 136 #define SI_SAMPLER_STATE_MAGIC 0x34f1c35a 137 138 struct si_sampler_state { 139 #ifdef DEBUG 140 unsigned magic; 141 #endif 142 uint32_t val[4]; 143 }; 144 145 struct si_cs_shader_state { 146 struct si_compute *program; 147 struct si_compute *emitted_program; 148 unsigned offset; 149 bool initialized; 150 bool uses_scratch; 151 }; 152 153 struct si_textures_info { 154 struct si_sampler_views views; 155 uint32_t depth_texture_mask; /* which textures are depth */ 156 uint32_t compressed_colortex_mask; 157 }; 158 159 struct si_images_info { 160 struct pipe_image_view views[SI_NUM_IMAGES]; 161 uint32_t compressed_colortex_mask; 162 unsigned enabled_mask; 163 }; 164 165 struct si_framebuffer { 166 struct r600_atom atom; 167 struct pipe_framebuffer_state state; 168 unsigned nr_samples; 169 unsigned log_samples; 170 unsigned compressed_cb_mask; 171 unsigned colorbuf_enabled_4bit; 172 unsigned spi_shader_col_format; 173 unsigned spi_shader_col_format_alpha; 174 unsigned spi_shader_col_format_blend; 175 unsigned spi_shader_col_format_blend_alpha; 176 unsigned color_is_int8; 177 unsigned color_is_int10; 178 unsigned dirty_cbufs; 179 bool dirty_zsbuf; 180 bool any_dst_linear; 181 }; 182 183 struct si_clip_state { 184 struct r600_atom atom; 185 struct pipe_clip_state state; 186 }; 187 188 struct si_sample_locs { 189 struct r600_atom atom; 190 unsigned nr_samples; 191 }; 192 193 struct si_sample_mask { 194 struct r600_atom atom; 195 uint16_t sample_mask; 196 }; 197 198 /* A shader state consists of the shader selector, which is a constant state 199 * object shared by multiple contexts and shouldn't be modified, and 200 * the current shader variant selected for this context. 201 */ 202 struct si_shader_ctx_state { 203 struct si_shader_selector *cso; 204 struct si_shader *current; 205 }; 206 207 struct si_context { 208 struct r600_common_context b; 209 struct blitter_context *blitter; 210 void *custom_dsa_flush; 211 void *custom_blend_resolve; 212 void *custom_blend_decompress; 213 void *custom_blend_fastclear; 214 void *custom_blend_dcc_decompress; 215 struct si_screen *screen; 216 217 struct radeon_winsys_cs *ce_ib; 218 struct radeon_winsys_cs *ce_preamble_ib; 219 bool ce_need_synchronization; 220 struct u_suballocator *ce_suballocator; 221 222 struct si_shader_ctx_state fixed_func_tcs_shader; 223 LLVMTargetMachineRef tm; /* only non-threaded compilation */ 224 bool gfx_flush_in_progress; 225 bool compute_is_busy; 226 227 /* Atoms (direct states). */ 228 union si_state_atoms atoms; 229 unsigned dirty_atoms; /* mask */ 230 /* PM4 states (precomputed immutable states) */ 231 union si_state queued; 232 union si_state emitted; 233 234 /* Atom declarations. */ 235 struct si_framebuffer framebuffer; 236 struct si_sample_locs msaa_sample_locs; 237 struct r600_atom db_render_state; 238 struct r600_atom msaa_config; 239 struct si_sample_mask sample_mask; 240 struct r600_atom cb_render_state; 241 struct si_blend_color blend_color; 242 struct r600_atom clip_regs; 243 struct si_clip_state clip_state; 244 struct si_shader_data shader_userdata; 245 struct si_stencil_ref stencil_ref; 246 struct r600_atom spi_map; 247 248 /* Precomputed states. */ 249 struct si_pm4_state *init_config; 250 struct si_pm4_state *init_config_gs_rings; 251 bool init_config_has_vgt_flush; 252 struct si_pm4_state *vgt_shader_config[4]; 253 254 /* shaders */ 255 struct si_shader_ctx_state ps_shader; 256 struct si_shader_ctx_state gs_shader; 257 struct si_shader_ctx_state vs_shader; 258 struct si_shader_ctx_state tcs_shader; 259 struct si_shader_ctx_state tes_shader; 260 struct si_cs_shader_state cs_shader_state; 261 262 /* shader information */ 263 struct si_vertex_element *vertex_elements; 264 unsigned sprite_coord_enable; 265 bool flatshade; 266 bool do_update_shaders; 267 268 /* shader descriptors */ 269 struct si_descriptors vertex_buffers; 270 struct si_descriptors descriptors[SI_NUM_DESCS]; 271 unsigned descriptors_dirty; 272 unsigned shader_pointers_dirty; 273 unsigned compressed_tex_shader_mask; 274 struct si_buffer_resources rw_buffers; 275 struct si_buffer_resources const_buffers[SI_NUM_SHADERS]; 276 struct si_buffer_resources shader_buffers[SI_NUM_SHADERS]; 277 struct si_textures_info samplers[SI_NUM_SHADERS]; 278 struct si_images_info images[SI_NUM_SHADERS]; 279 280 /* other shader resources */ 281 struct pipe_constant_buffer null_const_buf; /* used for set_constant_buffer(NULL) on CIK */ 282 struct pipe_resource *esgs_ring; 283 struct pipe_resource *gsvs_ring; 284 struct pipe_resource *tf_ring; 285 struct pipe_resource *tess_offchip_ring; 286 union pipe_color_union *border_color_table; /* in CPU memory, any endian */ 287 struct r600_resource *border_color_buffer; 288 union pipe_color_union *border_color_map; /* in VRAM (slow access), little endian */ 289 unsigned border_color_count; 290 291 /* Vertex and index buffers. */ 292 bool vertex_buffers_dirty; 293 bool vertex_buffer_pointer_dirty; 294 struct pipe_index_buffer index_buffer; 295 struct pipe_vertex_buffer vertex_buffer[SI_NUM_VERTEX_BUFFERS]; 296 297 /* MSAA config state. */ 298 int ps_iter_samples; 299 bool smoothing_enabled; 300 301 /* DB render state. */ 302 bool dbcb_depth_copy_enabled; 303 bool dbcb_stencil_copy_enabled; 304 unsigned dbcb_copy_sample; 305 bool db_flush_depth_inplace; 306 bool db_flush_stencil_inplace; 307 bool db_depth_clear; 308 bool db_depth_disable_expclear; 309 bool db_stencil_clear; 310 bool db_stencil_disable_expclear; 311 unsigned ps_db_shader_control; 312 bool occlusion_queries_disabled; 313 314 /* Emitted draw state. */ 315 int last_index_size; 316 int last_base_vertex; 317 int last_start_instance; 318 int last_drawid; 319 int last_sh_base_reg; 320 int last_primitive_restart_en; 321 int last_restart_index; 322 int last_gs_out_prim; 323 int last_prim; 324 int last_multi_vgt_param; 325 int last_rast_prim; 326 unsigned last_sc_line_stipple; 327 int last_vtx_reuse_depth; 328 int current_rast_prim; /* primitive type after TES, GS */ 329 bool gs_tri_strip_adj_fix; 330 331 /* Scratch buffer */ 332 struct r600_resource *scratch_buffer; 333 bool emit_scratch_reloc; 334 unsigned scratch_waves; 335 unsigned spi_tmpring_size; 336 337 struct r600_resource *compute_scratch_buffer; 338 339 /* Emitted derived tessellation state. */ 340 struct si_shader *last_ls; /* local shader (VS) */ 341 struct si_shader_selector *last_tcs; 342 int last_num_tcs_input_cp; 343 int last_tes_sh_base; 344 unsigned last_num_patches; 345 346 /* Debug state. */ 347 bool is_debug; 348 struct radeon_saved_cs last_gfx; 349 struct r600_resource *last_trace_buf; 350 struct r600_resource *trace_buf; 351 unsigned trace_id; 352 uint64_t dmesg_timestamp; 353 unsigned apitrace_call_number; 354 355 /* Other state */ 356 bool need_check_render_feedback; 357 }; 358 359 /* cik_sdma.c */ 360 void cik_init_sdma_functions(struct si_context *sctx); 361 362 /* si_blit.c */ 363 void si_init_blit_functions(struct si_context *sctx); 364 void si_decompress_graphics_textures(struct si_context *sctx); 365 void si_decompress_compute_textures(struct si_context *sctx); 366 void si_resource_copy_region(struct pipe_context *ctx, 367 struct pipe_resource *dst, 368 unsigned dst_level, 369 unsigned dstx, unsigned dsty, unsigned dstz, 370 struct pipe_resource *src, 371 unsigned src_level, 372 const struct pipe_box *src_box); 373 374 /* si_cp_dma.c */ 375 #define SI_CPDMA_SKIP_CHECK_CS_SPACE (1 << 0) /* don't call need_cs_space */ 376 #define SI_CPDMA_SKIP_SYNC_AFTER (1 << 1) /* don't wait for DMA after the copy */ 377 #define SI_CPDMA_SKIP_SYNC_BEFORE (1 << 2) /* don't wait for DMA before the copy (RAW hazards) */ 378 #define SI_CPDMA_SKIP_GFX_SYNC (1 << 3) /* don't flush caches and don't wait for PS/CS */ 379 #define SI_CPDMA_SKIP_BO_LIST_UPDATE (1 << 4) /* don't update the BO list */ 380 #define SI_CPDMA_SKIP_ALL (SI_CPDMA_SKIP_CHECK_CS_SPACE | \ 381 SI_CPDMA_SKIP_SYNC_AFTER | \ 382 SI_CPDMA_SKIP_SYNC_BEFORE | \ 383 SI_CPDMA_SKIP_GFX_SYNC | \ 384 SI_CPDMA_SKIP_BO_LIST_UPDATE) 385 386 void si_copy_buffer(struct si_context *sctx, 387 struct pipe_resource *dst, struct pipe_resource *src, 388 uint64_t dst_offset, uint64_t src_offset, unsigned size, 389 unsigned user_flags); 390 void cik_prefetch_TC_L2_async(struct si_context *sctx, struct pipe_resource *buf, 391 uint64_t offset, unsigned size); 392 void si_init_cp_dma_functions(struct si_context *sctx); 393 394 /* si_debug.c */ 395 void si_init_debug_functions(struct si_context *sctx); 396 void si_check_vm_faults(struct r600_common_context *ctx, 397 struct radeon_saved_cs *saved, enum ring_type ring); 398 bool si_replace_shader(unsigned num, struct radeon_shader_binary *binary); 399 400 /* si_dma.c */ 401 void si_init_dma_functions(struct si_context *sctx); 402 403 /* si_hw_context.c */ 404 void si_context_gfx_flush(void *context, unsigned flags, 405 struct pipe_fence_handle **fence); 406 void si_begin_new_cs(struct si_context *ctx); 407 void si_need_cs_space(struct si_context *ctx); 408 409 /* si_compute.c */ 410 void si_init_compute_functions(struct si_context *sctx); 411 412 /* si_perfcounters.c */ 413 void si_init_perfcounters(struct si_screen *screen); 414 415 /* si_uvd.c */ 416 struct pipe_video_codec *si_uvd_create_decoder(struct pipe_context *context, 417 const struct pipe_video_codec *templ); 418 419 struct pipe_video_buffer *si_video_buffer_create(struct pipe_context *pipe, 420 const struct pipe_video_buffer *tmpl); 421 422 /* 423 * common helpers 424 */ 425 426 static inline void 427 si_invalidate_draw_sh_constants(struct si_context *sctx) 428 { 429 sctx->last_base_vertex = SI_BASE_VERTEX_UNKNOWN; 430 } 431 432 static inline void 433 si_set_atom_dirty(struct si_context *sctx, 434 struct r600_atom *atom, bool dirty) 435 { 436 unsigned bit = 1 << (atom->id - 1); 437 438 if (dirty) 439 sctx->dirty_atoms |= bit; 440 else 441 sctx->dirty_atoms &= ~bit; 442 } 443 444 static inline bool 445 si_is_atom_dirty(struct si_context *sctx, 446 struct r600_atom *atom) 447 { 448 unsigned bit = 1 << (atom->id - 1); 449 450 return sctx->dirty_atoms & bit; 451 } 452 453 static inline void 454 si_mark_atom_dirty(struct si_context *sctx, 455 struct r600_atom *atom) 456 { 457 si_set_atom_dirty(sctx, atom, true); 458 } 459 460 static inline struct tgsi_shader_info *si_get_vs_info(struct si_context *sctx) 461 { 462 if (sctx->gs_shader.cso) 463 return &sctx->gs_shader.cso->info; 464 else if (sctx->tes_shader.cso) 465 return &sctx->tes_shader.cso->info; 466 else if (sctx->vs_shader.cso) 467 return &sctx->vs_shader.cso->info; 468 else 469 return NULL; 470 } 471 472 static inline struct si_shader* si_get_vs_state(struct si_context *sctx) 473 { 474 if (sctx->gs_shader.current) 475 return sctx->gs_shader.cso->gs_copy_shader; 476 else if (sctx->tes_shader.current) 477 return sctx->tes_shader.current; 478 else 479 return sctx->vs_shader.current; 480 } 481 482 static inline bool si_vs_exports_prim_id(struct si_shader *shader) 483 { 484 if (shader->selector->type == PIPE_SHADER_VERTEX) 485 return shader->key.part.vs.epilog.export_prim_id; 486 else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) 487 return shader->key.part.tes.epilog.export_prim_id; 488 else 489 return false; 490 } 491 492 #endif 493
