1 /* 2 * Copyright 2014, 2015 Red Hat. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * on the rights to use, copy, modify, merge, publish, distribute, sub 8 * license, and/or sell copies of the Software, and to permit persons to whom 9 * the Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 21 * USE OR OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 #include <stdint.h> 24 #include <assert.h> 25 #include <string.h> 26 27 #include "util/u_format.h" 28 #include "util/u_memory.h" 29 #include "util/u_math.h" 30 #include "pipe/p_state.h" 31 #include "tgsi/tgsi_dump.h" 32 #include "tgsi/tgsi_parse.h" 33 34 #include "virgl_context.h" 35 #include "virgl_encode.h" 36 #include "virgl_protocol.h" 37 #include "virgl_resource.h" 38 #include "virgl_screen.h" 39 40 static int virgl_encoder_write_cmd_dword(struct virgl_context *ctx, 41 uint32_t dword) 42 { 43 int len = (dword >> 16); 44 45 if ((ctx->cbuf->cdw + len + 1) > VIRGL_MAX_CMDBUF_DWORDS) 46 ctx->base.flush(&ctx->base, NULL, 0); 47 48 virgl_encoder_write_dword(ctx->cbuf, dword); 49 return 0; 50 } 51 52 static void virgl_encoder_write_res(struct virgl_context *ctx, 53 struct virgl_resource *res) 54 { 55 struct virgl_winsys *vws = virgl_screen(ctx->base.screen)->vws; 56 57 if (res && res->hw_res) 58 vws->emit_res(vws, ctx->cbuf, res->hw_res, TRUE); 59 else { 60 virgl_encoder_write_dword(ctx->cbuf, 0); 61 } 62 } 63 64 int virgl_encode_bind_object(struct virgl_context *ctx, 65 uint32_t handle, uint32_t object) 66 { 67 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_BIND_OBJECT, object, 1)); 68 virgl_encoder_write_dword(ctx->cbuf, handle); 69 return 0; 70 } 71 72 int virgl_encode_delete_object(struct virgl_context *ctx, 73 uint32_t handle, uint32_t object) 74 { 75 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_DESTROY_OBJECT, object, 1)); 76 virgl_encoder_write_dword(ctx->cbuf, handle); 77 return 0; 78 } 79 80 int virgl_encode_blend_state(struct virgl_context *ctx, 81 uint32_t handle, 82 const struct pipe_blend_state *blend_state) 83 { 84 uint32_t tmp; 85 int i; 86 87 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_CREATE_OBJECT, VIRGL_OBJECT_BLEND, VIRGL_OBJ_BLEND_SIZE)); 88 virgl_encoder_write_dword(ctx->cbuf, handle); 89 90 tmp = 91 VIRGL_OBJ_BLEND_S0_INDEPENDENT_BLEND_ENABLE(blend_state->independent_blend_enable) | 92 VIRGL_OBJ_BLEND_S0_LOGICOP_ENABLE(blend_state->logicop_enable) | 93 VIRGL_OBJ_BLEND_S0_DITHER(blend_state->dither) | 94 VIRGL_OBJ_BLEND_S0_ALPHA_TO_COVERAGE(blend_state->alpha_to_coverage) | 95 VIRGL_OBJ_BLEND_S0_ALPHA_TO_ONE(blend_state->alpha_to_one); 96 97 virgl_encoder_write_dword(ctx->cbuf, tmp); 98 99 tmp = VIRGL_OBJ_BLEND_S1_LOGICOP_FUNC(blend_state->logicop_func); 100 virgl_encoder_write_dword(ctx->cbuf, tmp); 101 102 for (i = 0; i < VIRGL_MAX_COLOR_BUFS; i++) { 103 tmp = 104 VIRGL_OBJ_BLEND_S2_RT_BLEND_ENABLE(blend_state->rt[i].blend_enable) | 105 VIRGL_OBJ_BLEND_S2_RT_RGB_FUNC(blend_state->rt[i].rgb_func) | 106 VIRGL_OBJ_BLEND_S2_RT_RGB_SRC_FACTOR(blend_state->rt[i].rgb_src_factor) | 107 VIRGL_OBJ_BLEND_S2_RT_RGB_DST_FACTOR(blend_state->rt[i].rgb_dst_factor)| 108 VIRGL_OBJ_BLEND_S2_RT_ALPHA_FUNC(blend_state->rt[i].alpha_func) | 109 VIRGL_OBJ_BLEND_S2_RT_ALPHA_SRC_FACTOR(blend_state->rt[i].alpha_src_factor) | 110 VIRGL_OBJ_BLEND_S2_RT_ALPHA_DST_FACTOR(blend_state->rt[i].alpha_dst_factor) | 111 VIRGL_OBJ_BLEND_S2_RT_COLORMASK(blend_state->rt[i].colormask); 112 virgl_encoder_write_dword(ctx->cbuf, tmp); 113 } 114 return 0; 115 } 116 117 int virgl_encode_dsa_state(struct virgl_context *ctx, 118 uint32_t handle, 119 const struct pipe_depth_stencil_alpha_state *dsa_state) 120 { 121 uint32_t tmp; 122 int i; 123 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_CREATE_OBJECT, VIRGL_OBJECT_DSA, VIRGL_OBJ_DSA_SIZE)); 124 virgl_encoder_write_dword(ctx->cbuf, handle); 125 126 tmp = VIRGL_OBJ_DSA_S0_DEPTH_ENABLE(dsa_state->depth.enabled) | 127 VIRGL_OBJ_DSA_S0_DEPTH_WRITEMASK(dsa_state->depth.writemask) | 128 VIRGL_OBJ_DSA_S0_DEPTH_FUNC(dsa_state->depth.func) | 129 VIRGL_OBJ_DSA_S0_ALPHA_ENABLED(dsa_state->alpha.enabled) | 130 VIRGL_OBJ_DSA_S0_ALPHA_FUNC(dsa_state->alpha.func); 131 virgl_encoder_write_dword(ctx->cbuf, tmp); 132 133 for (i = 0; i < 2; i++) { 134 tmp = VIRGL_OBJ_DSA_S1_STENCIL_ENABLED(dsa_state->stencil[i].enabled) | 135 VIRGL_OBJ_DSA_S1_STENCIL_FUNC(dsa_state->stencil[i].func) | 136 VIRGL_OBJ_DSA_S1_STENCIL_FAIL_OP(dsa_state->stencil[i].fail_op) | 137 VIRGL_OBJ_DSA_S1_STENCIL_ZPASS_OP(dsa_state->stencil[i].zpass_op) | 138 VIRGL_OBJ_DSA_S1_STENCIL_ZFAIL_OP(dsa_state->stencil[i].zfail_op) | 139 VIRGL_OBJ_DSA_S1_STENCIL_VALUEMASK(dsa_state->stencil[i].valuemask) | 140 VIRGL_OBJ_DSA_S1_STENCIL_WRITEMASK(dsa_state->stencil[i].writemask); 141 virgl_encoder_write_dword(ctx->cbuf, tmp); 142 } 143 144 virgl_encoder_write_dword(ctx->cbuf, fui(dsa_state->alpha.ref_value)); 145 return 0; 146 } 147 int virgl_encode_rasterizer_state(struct virgl_context *ctx, 148 uint32_t handle, 149 const struct pipe_rasterizer_state *state) 150 { 151 uint32_t tmp; 152 153 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_CREATE_OBJECT, VIRGL_OBJECT_RASTERIZER, VIRGL_OBJ_RS_SIZE)); 154 virgl_encoder_write_dword(ctx->cbuf, handle); 155 156 tmp = VIRGL_OBJ_RS_S0_FLATSHADE(state->flatshade) | 157 VIRGL_OBJ_RS_S0_DEPTH_CLIP(state->depth_clip) | 158 VIRGL_OBJ_RS_S0_CLIP_HALFZ(state->clip_halfz) | 159 VIRGL_OBJ_RS_S0_RASTERIZER_DISCARD(state->rasterizer_discard) | 160 VIRGL_OBJ_RS_S0_FLATSHADE_FIRST(state->flatshade_first) | 161 VIRGL_OBJ_RS_S0_LIGHT_TWOSIZE(state->light_twoside) | 162 VIRGL_OBJ_RS_S0_SPRITE_COORD_MODE(state->sprite_coord_mode) | 163 VIRGL_OBJ_RS_S0_POINT_QUAD_RASTERIZATION(state->point_quad_rasterization) | 164 VIRGL_OBJ_RS_S0_CULL_FACE(state->cull_face) | 165 VIRGL_OBJ_RS_S0_FILL_FRONT(state->fill_front) | 166 VIRGL_OBJ_RS_S0_FILL_BACK(state->fill_back) | 167 VIRGL_OBJ_RS_S0_SCISSOR(state->scissor) | 168 VIRGL_OBJ_RS_S0_FRONT_CCW(state->front_ccw) | 169 VIRGL_OBJ_RS_S0_CLAMP_VERTEX_COLOR(state->clamp_vertex_color) | 170 VIRGL_OBJ_RS_S0_CLAMP_FRAGMENT_COLOR(state->clamp_fragment_color) | 171 VIRGL_OBJ_RS_S0_OFFSET_LINE(state->offset_line) | 172 VIRGL_OBJ_RS_S0_OFFSET_POINT(state->offset_point) | 173 VIRGL_OBJ_RS_S0_OFFSET_TRI(state->offset_tri) | 174 VIRGL_OBJ_RS_S0_POLY_SMOOTH(state->poly_smooth) | 175 VIRGL_OBJ_RS_S0_POLY_STIPPLE_ENABLE(state->poly_stipple_enable) | 176 VIRGL_OBJ_RS_S0_POINT_SMOOTH(state->point_smooth) | 177 VIRGL_OBJ_RS_S0_POINT_SIZE_PER_VERTEX(state->point_size_per_vertex) | 178 VIRGL_OBJ_RS_S0_MULTISAMPLE(state->multisample) | 179 VIRGL_OBJ_RS_S0_LINE_SMOOTH(state->line_smooth) | 180 VIRGL_OBJ_RS_S0_LINE_STIPPLE_ENABLE(state->line_stipple_enable) | 181 VIRGL_OBJ_RS_S0_LINE_LAST_PIXEL(state->line_last_pixel) | 182 VIRGL_OBJ_RS_S0_HALF_PIXEL_CENTER(state->half_pixel_center) | 183 VIRGL_OBJ_RS_S0_BOTTOM_EDGE_RULE(state->bottom_edge_rule); 184 185 virgl_encoder_write_dword(ctx->cbuf, tmp); /* S0 */ 186 virgl_encoder_write_dword(ctx->cbuf, fui(state->point_size)); /* S1 */ 187 virgl_encoder_write_dword(ctx->cbuf, state->sprite_coord_enable); /* S2 */ 188 tmp = VIRGL_OBJ_RS_S3_LINE_STIPPLE_PATTERN(state->line_stipple_pattern) | 189 VIRGL_OBJ_RS_S3_LINE_STIPPLE_FACTOR(state->line_stipple_factor) | 190 VIRGL_OBJ_RS_S3_CLIP_PLANE_ENABLE(state->clip_plane_enable); 191 virgl_encoder_write_dword(ctx->cbuf, tmp); /* S3 */ 192 virgl_encoder_write_dword(ctx->cbuf, fui(state->line_width)); /* S4 */ 193 virgl_encoder_write_dword(ctx->cbuf, fui(state->offset_units)); /* S5 */ 194 virgl_encoder_write_dword(ctx->cbuf, fui(state->offset_scale)); /* S6 */ 195 virgl_encoder_write_dword(ctx->cbuf, fui(state->offset_clamp)); /* S7 */ 196 return 0; 197 } 198 199 static void virgl_emit_shader_header(struct virgl_context *ctx, 200 uint32_t handle, uint32_t len, 201 uint32_t type, uint32_t offlen, 202 uint32_t num_tokens) 203 { 204 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_CREATE_OBJECT, VIRGL_OBJECT_SHADER, len)); 205 virgl_encoder_write_dword(ctx->cbuf, handle); 206 virgl_encoder_write_dword(ctx->cbuf, type); 207 virgl_encoder_write_dword(ctx->cbuf, offlen); 208 virgl_encoder_write_dword(ctx->cbuf, num_tokens); 209 } 210 211 static void virgl_emit_shader_streamout(struct virgl_context *ctx, 212 const struct pipe_stream_output_info *so_info) 213 { 214 int num_outputs = 0; 215 int i; 216 uint32_t tmp; 217 218 if (so_info) 219 num_outputs = so_info->num_outputs; 220 221 virgl_encoder_write_dword(ctx->cbuf, num_outputs); 222 if (num_outputs) { 223 for (i = 0; i < 4; i++) 224 virgl_encoder_write_dword(ctx->cbuf, so_info->stride[i]); 225 226 for (i = 0; i < so_info->num_outputs; i++) { 227 tmp = 228 VIRGL_OBJ_SHADER_SO_OUTPUT_REGISTER_INDEX(so_info->output[i].register_index) | 229 VIRGL_OBJ_SHADER_SO_OUTPUT_START_COMPONENT(so_info->output[i].start_component) | 230 VIRGL_OBJ_SHADER_SO_OUTPUT_NUM_COMPONENTS(so_info->output[i].num_components) | 231 VIRGL_OBJ_SHADER_SO_OUTPUT_BUFFER(so_info->output[i].output_buffer) | 232 VIRGL_OBJ_SHADER_SO_OUTPUT_DST_OFFSET(so_info->output[i].dst_offset); 233 virgl_encoder_write_dword(ctx->cbuf, tmp); 234 virgl_encoder_write_dword(ctx->cbuf, 0); 235 } 236 } 237 } 238 239 int virgl_encode_shader_state(struct virgl_context *ctx, 240 uint32_t handle, 241 uint32_t type, 242 const struct pipe_stream_output_info *so_info, 243 const struct tgsi_token *tokens) 244 { 245 char *str, *sptr; 246 uint32_t shader_len, len; 247 bool bret; 248 int num_tokens = tgsi_num_tokens(tokens); 249 int str_total_size = 65536; 250 int retry_size = 1; 251 uint32_t left_bytes, base_hdr_size, strm_hdr_size, thispass; 252 bool first_pass; 253 str = CALLOC(1, str_total_size); 254 if (!str) 255 return -1; 256 257 do { 258 int old_size; 259 260 bret = tgsi_dump_str(tokens, TGSI_DUMP_FLOAT_AS_HEX, str, str_total_size); 261 if (bret == false) { 262 fprintf(stderr, "Failed to translate shader in available space - trying again\n"); 263 old_size = str_total_size; 264 str_total_size = 65536 * ++retry_size; 265 str = REALLOC(str, old_size, str_total_size); 266 if (!str) 267 return -1; 268 } 269 } while (bret == false && retry_size < 10); 270 271 if (bret == false) 272 return -1; 273 274 shader_len = strlen(str) + 1; 275 276 left_bytes = shader_len; 277 278 base_hdr_size = 5; 279 strm_hdr_size = so_info->num_outputs ? so_info->num_outputs * 2 + 4 : 0; 280 first_pass = true; 281 sptr = str; 282 while (left_bytes) { 283 uint32_t length, offlen; 284 int hdr_len = base_hdr_size + (first_pass ? strm_hdr_size : 0); 285 if (ctx->cbuf->cdw + hdr_len + 1 > VIRGL_MAX_CMDBUF_DWORDS) 286 ctx->base.flush(&ctx->base, NULL, 0); 287 288 thispass = (VIRGL_MAX_CMDBUF_DWORDS - ctx->cbuf->cdw - hdr_len - 1) * 4; 289 290 length = MIN2(thispass, left_bytes); 291 len = ((length + 3) / 4) + hdr_len; 292 293 if (first_pass) 294 offlen = VIRGL_OBJ_SHADER_OFFSET_VAL(shader_len); 295 else 296 offlen = VIRGL_OBJ_SHADER_OFFSET_VAL((uintptr_t)sptr - (uintptr_t)str) | VIRGL_OBJ_SHADER_OFFSET_CONT; 297 298 virgl_emit_shader_header(ctx, handle, len, type, offlen, num_tokens); 299 300 virgl_emit_shader_streamout(ctx, first_pass ? so_info : NULL); 301 302 virgl_encoder_write_block(ctx->cbuf, (uint8_t *)sptr, length); 303 304 sptr += length; 305 first_pass = false; 306 left_bytes -= length; 307 } 308 309 FREE(str); 310 return 0; 311 } 312 313 314 int virgl_encode_clear(struct virgl_context *ctx, 315 unsigned buffers, 316 const union pipe_color_union *color, 317 double depth, unsigned stencil) 318 { 319 int i; 320 uint64_t qword; 321 322 STATIC_ASSERT(sizeof(qword) == sizeof(depth)); 323 memcpy(&qword, &depth, sizeof(qword)); 324 325 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_CLEAR, 0, VIRGL_OBJ_CLEAR_SIZE)); 326 virgl_encoder_write_dword(ctx->cbuf, buffers); 327 for (i = 0; i < 4; i++) 328 virgl_encoder_write_dword(ctx->cbuf, color->ui[i]); 329 virgl_encoder_write_qword(ctx->cbuf, qword); 330 virgl_encoder_write_dword(ctx->cbuf, stencil); 331 return 0; 332 } 333 334 int virgl_encoder_set_framebuffer_state(struct virgl_context *ctx, 335 const struct pipe_framebuffer_state *state) 336 { 337 struct virgl_surface *zsurf = virgl_surface(state->zsbuf); 338 int i; 339 340 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_FRAMEBUFFER_STATE, 0, VIRGL_SET_FRAMEBUFFER_STATE_SIZE(state->nr_cbufs))); 341 virgl_encoder_write_dword(ctx->cbuf, state->nr_cbufs); 342 virgl_encoder_write_dword(ctx->cbuf, zsurf ? zsurf->handle : 0); 343 for (i = 0; i < state->nr_cbufs; i++) { 344 struct virgl_surface *surf = virgl_surface(state->cbufs[i]); 345 virgl_encoder_write_dword(ctx->cbuf, surf ? surf->handle : 0); 346 } 347 348 return 0; 349 } 350 351 int virgl_encoder_set_viewport_states(struct virgl_context *ctx, 352 int start_slot, 353 int num_viewports, 354 const struct pipe_viewport_state *states) 355 { 356 int i,v; 357 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_VIEWPORT_STATE, 0, VIRGL_SET_VIEWPORT_STATE_SIZE(num_viewports))); 358 virgl_encoder_write_dword(ctx->cbuf, start_slot); 359 for (v = 0; v < num_viewports; v++) { 360 for (i = 0; i < 3; i++) 361 virgl_encoder_write_dword(ctx->cbuf, fui(states[v].scale[i])); 362 for (i = 0; i < 3; i++) 363 virgl_encoder_write_dword(ctx->cbuf, fui(states[v].translate[i])); 364 } 365 return 0; 366 } 367 368 int virgl_encoder_create_vertex_elements(struct virgl_context *ctx, 369 uint32_t handle, 370 unsigned num_elements, 371 const struct pipe_vertex_element *element) 372 { 373 int i; 374 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_CREATE_OBJECT, VIRGL_OBJECT_VERTEX_ELEMENTS, VIRGL_OBJ_VERTEX_ELEMENTS_SIZE(num_elements))); 375 virgl_encoder_write_dword(ctx->cbuf, handle); 376 for (i = 0; i < num_elements; i++) { 377 virgl_encoder_write_dword(ctx->cbuf, element[i].src_offset); 378 virgl_encoder_write_dword(ctx->cbuf, element[i].instance_divisor); 379 virgl_encoder_write_dword(ctx->cbuf, element[i].vertex_buffer_index); 380 virgl_encoder_write_dword(ctx->cbuf, element[i].src_format); 381 } 382 return 0; 383 } 384 385 int virgl_encoder_set_vertex_buffers(struct virgl_context *ctx, 386 unsigned num_buffers, 387 const struct pipe_vertex_buffer *buffers) 388 { 389 int i; 390 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_VERTEX_BUFFERS, 0, VIRGL_SET_VERTEX_BUFFERS_SIZE(num_buffers))); 391 for (i = 0; i < num_buffers; i++) { 392 struct virgl_resource *res = virgl_resource(buffers[i].buffer); 393 virgl_encoder_write_dword(ctx->cbuf, buffers[i].stride); 394 virgl_encoder_write_dword(ctx->cbuf, buffers[i].buffer_offset); 395 virgl_encoder_write_res(ctx, res); 396 } 397 return 0; 398 } 399 400 int virgl_encoder_set_index_buffer(struct virgl_context *ctx, 401 const struct pipe_index_buffer *ib) 402 { 403 int length = VIRGL_SET_INDEX_BUFFER_SIZE(ib); 404 struct virgl_resource *res = NULL; 405 if (ib) 406 res = virgl_resource(ib->buffer); 407 408 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_INDEX_BUFFER, 0, length)); 409 virgl_encoder_write_res(ctx, res); 410 if (ib) { 411 virgl_encoder_write_dword(ctx->cbuf, ib->index_size); 412 virgl_encoder_write_dword(ctx->cbuf, ib->offset); 413 } 414 return 0; 415 } 416 417 int virgl_encoder_draw_vbo(struct virgl_context *ctx, 418 const struct pipe_draw_info *info) 419 { 420 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_DRAW_VBO, 0, VIRGL_DRAW_VBO_SIZE)); 421 virgl_encoder_write_dword(ctx->cbuf, info->start); 422 virgl_encoder_write_dword(ctx->cbuf, info->count); 423 virgl_encoder_write_dword(ctx->cbuf, info->mode); 424 virgl_encoder_write_dword(ctx->cbuf, info->indexed); 425 virgl_encoder_write_dword(ctx->cbuf, info->instance_count); 426 virgl_encoder_write_dword(ctx->cbuf, info->index_bias); 427 virgl_encoder_write_dword(ctx->cbuf, info->start_instance); 428 virgl_encoder_write_dword(ctx->cbuf, info->primitive_restart); 429 virgl_encoder_write_dword(ctx->cbuf, info->restart_index); 430 virgl_encoder_write_dword(ctx->cbuf, info->min_index); 431 virgl_encoder_write_dword(ctx->cbuf, info->max_index); 432 if (info->count_from_stream_output) 433 virgl_encoder_write_dword(ctx->cbuf, info->count_from_stream_output->buffer_size); 434 else 435 virgl_encoder_write_dword(ctx->cbuf, 0); 436 return 0; 437 } 438 439 int virgl_encoder_create_surface(struct virgl_context *ctx, 440 uint32_t handle, 441 struct virgl_resource *res, 442 const struct pipe_surface *templat) 443 { 444 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_CREATE_OBJECT, VIRGL_OBJECT_SURFACE, VIRGL_OBJ_SURFACE_SIZE)); 445 virgl_encoder_write_dword(ctx->cbuf, handle); 446 virgl_encoder_write_res(ctx, res); 447 virgl_encoder_write_dword(ctx->cbuf, templat->format); 448 if (templat->texture->target == PIPE_BUFFER) { 449 virgl_encoder_write_dword(ctx->cbuf, templat->u.buf.first_element); 450 virgl_encoder_write_dword(ctx->cbuf, templat->u.buf.last_element); 451 452 } else { 453 virgl_encoder_write_dword(ctx->cbuf, templat->u.tex.level); 454 virgl_encoder_write_dword(ctx->cbuf, templat->u.tex.first_layer | (templat->u.tex.last_layer << 16)); 455 } 456 return 0; 457 } 458 459 int virgl_encoder_create_so_target(struct virgl_context *ctx, 460 uint32_t handle, 461 struct virgl_resource *res, 462 unsigned buffer_offset, 463 unsigned buffer_size) 464 { 465 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_CREATE_OBJECT, VIRGL_OBJECT_STREAMOUT_TARGET, VIRGL_OBJ_STREAMOUT_SIZE)); 466 virgl_encoder_write_dword(ctx->cbuf, handle); 467 virgl_encoder_write_res(ctx, res); 468 virgl_encoder_write_dword(ctx->cbuf, buffer_offset); 469 virgl_encoder_write_dword(ctx->cbuf, buffer_size); 470 return 0; 471 } 472 473 static void virgl_encoder_iw_emit_header_1d(struct virgl_context *ctx, 474 struct virgl_resource *res, 475 unsigned level, unsigned usage, 476 const struct pipe_box *box, 477 unsigned stride, unsigned layer_stride) 478 { 479 virgl_encoder_write_res(ctx, res); 480 virgl_encoder_write_dword(ctx->cbuf, level); 481 virgl_encoder_write_dword(ctx->cbuf, usage); 482 virgl_encoder_write_dword(ctx->cbuf, stride); 483 virgl_encoder_write_dword(ctx->cbuf, layer_stride); 484 virgl_encoder_write_dword(ctx->cbuf, box->x); 485 virgl_encoder_write_dword(ctx->cbuf, box->y); 486 virgl_encoder_write_dword(ctx->cbuf, box->z); 487 virgl_encoder_write_dword(ctx->cbuf, box->width); 488 virgl_encoder_write_dword(ctx->cbuf, box->height); 489 virgl_encoder_write_dword(ctx->cbuf, box->depth); 490 } 491 492 int virgl_encoder_inline_write(struct virgl_context *ctx, 493 struct virgl_resource *res, 494 unsigned level, unsigned usage, 495 const struct pipe_box *box, 496 const void *data, unsigned stride, 497 unsigned layer_stride) 498 { 499 uint32_t size = (stride ? stride : box->width) * box->height; 500 uint32_t length, thispass, left_bytes; 501 struct pipe_box mybox = *box; 502 503 length = 11 + (size + 3) / 4; 504 if ((ctx->cbuf->cdw + length + 1) > VIRGL_MAX_CMDBUF_DWORDS) { 505 if (box->height > 1 || box->depth > 1) { 506 debug_printf("inline transfer failed due to multi dimensions and too large\n"); 507 assert(0); 508 } 509 } 510 511 left_bytes = size; 512 while (left_bytes) { 513 if (ctx->cbuf->cdw + 12 > VIRGL_MAX_CMDBUF_DWORDS) 514 ctx->base.flush(&ctx->base, NULL, 0); 515 516 thispass = (VIRGL_MAX_CMDBUF_DWORDS - ctx->cbuf->cdw - 12) * 4; 517 518 length = MIN2(thispass, left_bytes); 519 520 mybox.width = length; 521 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_RESOURCE_INLINE_WRITE, 0, ((length + 3) / 4) + 11)); 522 virgl_encoder_iw_emit_header_1d(ctx, res, level, usage, &mybox, stride, layer_stride); 523 virgl_encoder_write_block(ctx->cbuf, data, length); 524 left_bytes -= length; 525 mybox.x += length; 526 data += length; 527 } 528 return 0; 529 } 530 531 int virgl_encoder_flush_frontbuffer(struct virgl_context *ctx, 532 struct virgl_resource *res) 533 { 534 // virgl_encoder_write_dword(ctx->cbuf, VIRGL_CMD0(VIRGL_CCMD_FLUSH_FRONTUBFFER, 0, 1)); 535 // virgl_encoder_write_dword(ctx->cbuf, res_handle); 536 return 0; 537 } 538 539 int virgl_encode_sampler_state(struct virgl_context *ctx, 540 uint32_t handle, 541 const struct pipe_sampler_state *state) 542 { 543 uint32_t tmp; 544 int i; 545 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_CREATE_OBJECT, VIRGL_OBJECT_SAMPLER_STATE, VIRGL_OBJ_SAMPLER_STATE_SIZE)); 546 virgl_encoder_write_dword(ctx->cbuf, handle); 547 548 tmp = VIRGL_OBJ_SAMPLE_STATE_S0_WRAP_S(state->wrap_s) | 549 VIRGL_OBJ_SAMPLE_STATE_S0_WRAP_T(state->wrap_t) | 550 VIRGL_OBJ_SAMPLE_STATE_S0_WRAP_R(state->wrap_r) | 551 VIRGL_OBJ_SAMPLE_STATE_S0_MIN_IMG_FILTER(state->min_img_filter) | 552 VIRGL_OBJ_SAMPLE_STATE_S0_MIN_MIP_FILTER(state->min_mip_filter) | 553 VIRGL_OBJ_SAMPLE_STATE_S0_MAG_IMG_FILTER(state->mag_img_filter) | 554 VIRGL_OBJ_SAMPLE_STATE_S0_COMPARE_MODE(state->compare_mode) | 555 VIRGL_OBJ_SAMPLE_STATE_S0_COMPARE_FUNC(state->compare_func); 556 557 virgl_encoder_write_dword(ctx->cbuf, tmp); 558 virgl_encoder_write_dword(ctx->cbuf, fui(state->lod_bias)); 559 virgl_encoder_write_dword(ctx->cbuf, fui(state->min_lod)); 560 virgl_encoder_write_dword(ctx->cbuf, fui(state->max_lod)); 561 for (i = 0; i < 4; i++) 562 virgl_encoder_write_dword(ctx->cbuf, state->border_color.ui[i]); 563 return 0; 564 } 565 566 567 int virgl_encode_sampler_view(struct virgl_context *ctx, 568 uint32_t handle, 569 struct virgl_resource *res, 570 const struct pipe_sampler_view *state) 571 { 572 unsigned elem_size = util_format_get_blocksize(state->format); 573 574 uint32_t tmp; 575 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_CREATE_OBJECT, VIRGL_OBJECT_SAMPLER_VIEW, VIRGL_OBJ_SAMPLER_VIEW_SIZE)); 576 virgl_encoder_write_dword(ctx->cbuf, handle); 577 virgl_encoder_write_res(ctx, res); 578 virgl_encoder_write_dword(ctx->cbuf, state->format); 579 if (res->u.b.target == PIPE_BUFFER) { 580 virgl_encoder_write_dword(ctx->cbuf, state->u.buf.offset / elem_size); 581 virgl_encoder_write_dword(ctx->cbuf, (state->u.buf.offset + state->u.buf.size) / elem_size - 1); 582 } else { 583 virgl_encoder_write_dword(ctx->cbuf, state->u.tex.first_layer | state->u.tex.last_layer << 16); 584 virgl_encoder_write_dword(ctx->cbuf, state->u.tex.first_level | state->u.tex.last_level << 8); 585 } 586 tmp = VIRGL_OBJ_SAMPLER_VIEW_SWIZZLE_R(state->swizzle_r) | 587 VIRGL_OBJ_SAMPLER_VIEW_SWIZZLE_G(state->swizzle_g) | 588 VIRGL_OBJ_SAMPLER_VIEW_SWIZZLE_B(state->swizzle_b) | 589 VIRGL_OBJ_SAMPLER_VIEW_SWIZZLE_A(state->swizzle_a); 590 virgl_encoder_write_dword(ctx->cbuf, tmp); 591 return 0; 592 } 593 594 int virgl_encode_set_sampler_views(struct virgl_context *ctx, 595 uint32_t shader_type, 596 uint32_t start_slot, 597 uint32_t num_views, 598 struct virgl_sampler_view **views) 599 { 600 int i; 601 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_SAMPLER_VIEWS, 0, VIRGL_SET_SAMPLER_VIEWS_SIZE(num_views))); 602 virgl_encoder_write_dword(ctx->cbuf, shader_type); 603 virgl_encoder_write_dword(ctx->cbuf, start_slot); 604 for (i = 0; i < num_views; i++) { 605 uint32_t handle = views[i] ? views[i]->handle : 0; 606 virgl_encoder_write_dword(ctx->cbuf, handle); 607 } 608 return 0; 609 } 610 611 int virgl_encode_bind_sampler_states(struct virgl_context *ctx, 612 uint32_t shader_type, 613 uint32_t start_slot, 614 uint32_t num_handles, 615 uint32_t *handles) 616 { 617 int i; 618 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_BIND_SAMPLER_STATES, 0, VIRGL_BIND_SAMPLER_STATES(num_handles))); 619 virgl_encoder_write_dword(ctx->cbuf, shader_type); 620 virgl_encoder_write_dword(ctx->cbuf, start_slot); 621 for (i = 0; i < num_handles; i++) 622 virgl_encoder_write_dword(ctx->cbuf, handles[i]); 623 return 0; 624 } 625 626 int virgl_encoder_write_constant_buffer(struct virgl_context *ctx, 627 uint32_t shader, 628 uint32_t index, 629 uint32_t size, 630 const void *data) 631 { 632 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_CONSTANT_BUFFER, 0, size + 2)); 633 virgl_encoder_write_dword(ctx->cbuf, shader); 634 virgl_encoder_write_dword(ctx->cbuf, index); 635 if (data) 636 virgl_encoder_write_block(ctx->cbuf, data, size * 4); 637 return 0; 638 } 639 640 int virgl_encoder_set_uniform_buffer(struct virgl_context *ctx, 641 uint32_t shader, 642 uint32_t index, 643 uint32_t offset, 644 uint32_t length, 645 struct virgl_resource *res) 646 { 647 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_UNIFORM_BUFFER, 0, VIRGL_SET_UNIFORM_BUFFER_SIZE)); 648 virgl_encoder_write_dword(ctx->cbuf, shader); 649 virgl_encoder_write_dword(ctx->cbuf, index); 650 virgl_encoder_write_dword(ctx->cbuf, offset); 651 virgl_encoder_write_dword(ctx->cbuf, length); 652 virgl_encoder_write_res(ctx, res); 653 return 0; 654 } 655 656 657 int virgl_encoder_set_stencil_ref(struct virgl_context *ctx, 658 const struct pipe_stencil_ref *ref) 659 { 660 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_STENCIL_REF, 0, VIRGL_SET_STENCIL_REF_SIZE)); 661 virgl_encoder_write_dword(ctx->cbuf, VIRGL_STENCIL_REF_VAL(ref->ref_value[0] , (ref->ref_value[1]))); 662 return 0; 663 } 664 665 int virgl_encoder_set_blend_color(struct virgl_context *ctx, 666 const struct pipe_blend_color *color) 667 { 668 int i; 669 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_BLEND_COLOR, 0, VIRGL_SET_BLEND_COLOR_SIZE)); 670 for (i = 0; i < 4; i++) 671 virgl_encoder_write_dword(ctx->cbuf, fui(color->color[i])); 672 return 0; 673 } 674 675 int virgl_encoder_set_scissor_state(struct virgl_context *ctx, 676 unsigned start_slot, 677 int num_scissors, 678 const struct pipe_scissor_state *ss) 679 { 680 int i; 681 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_SCISSOR_STATE, 0, VIRGL_SET_SCISSOR_STATE_SIZE(num_scissors))); 682 virgl_encoder_write_dword(ctx->cbuf, start_slot); 683 for (i = 0; i < num_scissors; i++) { 684 virgl_encoder_write_dword(ctx->cbuf, (ss[i].minx | ss[i].miny << 16)); 685 virgl_encoder_write_dword(ctx->cbuf, (ss[i].maxx | ss[i].maxy << 16)); 686 } 687 return 0; 688 } 689 690 void virgl_encoder_set_polygon_stipple(struct virgl_context *ctx, 691 const struct pipe_poly_stipple *ps) 692 { 693 int i; 694 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_POLYGON_STIPPLE, 0, VIRGL_POLYGON_STIPPLE_SIZE)); 695 for (i = 0; i < VIRGL_POLYGON_STIPPLE_SIZE; i++) { 696 virgl_encoder_write_dword(ctx->cbuf, ps->stipple[i]); 697 } 698 } 699 700 void virgl_encoder_set_sample_mask(struct virgl_context *ctx, 701 unsigned sample_mask) 702 { 703 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_SAMPLE_MASK, 0, VIRGL_SET_SAMPLE_MASK_SIZE)); 704 virgl_encoder_write_dword(ctx->cbuf, sample_mask); 705 } 706 707 void virgl_encoder_set_clip_state(struct virgl_context *ctx, 708 const struct pipe_clip_state *clip) 709 { 710 int i, j; 711 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_CLIP_STATE, 0, VIRGL_SET_CLIP_STATE_SIZE)); 712 for (i = 0; i < VIRGL_MAX_CLIP_PLANES; i++) { 713 for (j = 0; j < 4; j++) { 714 virgl_encoder_write_dword(ctx->cbuf, fui(clip->ucp[i][j])); 715 } 716 } 717 } 718 719 int virgl_encode_resource_copy_region(struct virgl_context *ctx, 720 struct virgl_resource *dst_res, 721 unsigned dst_level, 722 unsigned dstx, unsigned dsty, unsigned dstz, 723 struct virgl_resource *src_res, 724 unsigned src_level, 725 const struct pipe_box *src_box) 726 { 727 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_RESOURCE_COPY_REGION, 0, VIRGL_CMD_RESOURCE_COPY_REGION_SIZE)); 728 virgl_encoder_write_res(ctx, dst_res); 729 virgl_encoder_write_dword(ctx->cbuf, dst_level); 730 virgl_encoder_write_dword(ctx->cbuf, dstx); 731 virgl_encoder_write_dword(ctx->cbuf, dsty); 732 virgl_encoder_write_dword(ctx->cbuf, dstz); 733 virgl_encoder_write_res(ctx, src_res); 734 virgl_encoder_write_dword(ctx->cbuf, src_level); 735 virgl_encoder_write_dword(ctx->cbuf, src_box->x); 736 virgl_encoder_write_dword(ctx->cbuf, src_box->y); 737 virgl_encoder_write_dword(ctx->cbuf, src_box->z); 738 virgl_encoder_write_dword(ctx->cbuf, src_box->width); 739 virgl_encoder_write_dword(ctx->cbuf, src_box->height); 740 virgl_encoder_write_dword(ctx->cbuf, src_box->depth); 741 return 0; 742 } 743 744 int virgl_encode_blit(struct virgl_context *ctx, 745 struct virgl_resource *dst_res, 746 struct virgl_resource *src_res, 747 const struct pipe_blit_info *blit) 748 { 749 uint32_t tmp; 750 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_BLIT, 0, VIRGL_CMD_BLIT_SIZE)); 751 tmp = VIRGL_CMD_BLIT_S0_MASK(blit->mask) | 752 VIRGL_CMD_BLIT_S0_FILTER(blit->filter) | 753 VIRGL_CMD_BLIT_S0_SCISSOR_ENABLE(blit->scissor_enable) | 754 VIRGL_CMD_BLIT_S0_RENDER_CONDITION_ENABLE(blit->render_condition_enable) | 755 VIRGL_CMD_BLIT_S0_ALPHA_BLEND(blit->alpha_blend); 756 virgl_encoder_write_dword(ctx->cbuf, tmp); 757 virgl_encoder_write_dword(ctx->cbuf, (blit->scissor.minx | blit->scissor.miny << 16)); 758 virgl_encoder_write_dword(ctx->cbuf, (blit->scissor.maxx | blit->scissor.maxy << 16)); 759 760 virgl_encoder_write_res(ctx, dst_res); 761 virgl_encoder_write_dword(ctx->cbuf, blit->dst.level); 762 virgl_encoder_write_dword(ctx->cbuf, blit->dst.format); 763 virgl_encoder_write_dword(ctx->cbuf, blit->dst.box.x); 764 virgl_encoder_write_dword(ctx->cbuf, blit->dst.box.y); 765 virgl_encoder_write_dword(ctx->cbuf, blit->dst.box.z); 766 virgl_encoder_write_dword(ctx->cbuf, blit->dst.box.width); 767 virgl_encoder_write_dword(ctx->cbuf, blit->dst.box.height); 768 virgl_encoder_write_dword(ctx->cbuf, blit->dst.box.depth); 769 770 virgl_encoder_write_res(ctx, src_res); 771 virgl_encoder_write_dword(ctx->cbuf, blit->src.level); 772 virgl_encoder_write_dword(ctx->cbuf, blit->src.format); 773 virgl_encoder_write_dword(ctx->cbuf, blit->src.box.x); 774 virgl_encoder_write_dword(ctx->cbuf, blit->src.box.y); 775 virgl_encoder_write_dword(ctx->cbuf, blit->src.box.z); 776 virgl_encoder_write_dword(ctx->cbuf, blit->src.box.width); 777 virgl_encoder_write_dword(ctx->cbuf, blit->src.box.height); 778 virgl_encoder_write_dword(ctx->cbuf, blit->src.box.depth); 779 return 0; 780 } 781 782 int virgl_encoder_create_query(struct virgl_context *ctx, 783 uint32_t handle, 784 uint query_type, 785 uint query_index, 786 struct virgl_resource *res, 787 uint32_t offset) 788 { 789 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_CREATE_OBJECT, VIRGL_OBJECT_QUERY, VIRGL_OBJ_QUERY_SIZE)); 790 virgl_encoder_write_dword(ctx->cbuf, handle); 791 virgl_encoder_write_dword(ctx->cbuf, ((query_type & 0xffff) | (query_index << 16))); 792 virgl_encoder_write_dword(ctx->cbuf, offset); 793 virgl_encoder_write_res(ctx, res); 794 return 0; 795 } 796 797 int virgl_encoder_begin_query(struct virgl_context *ctx, 798 uint32_t handle) 799 { 800 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_BEGIN_QUERY, 0, 1)); 801 virgl_encoder_write_dword(ctx->cbuf, handle); 802 return 0; 803 } 804 805 int virgl_encoder_end_query(struct virgl_context *ctx, 806 uint32_t handle) 807 { 808 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_END_QUERY, 0, 1)); 809 virgl_encoder_write_dword(ctx->cbuf, handle); 810 return 0; 811 } 812 813 int virgl_encoder_get_query_result(struct virgl_context *ctx, 814 uint32_t handle, boolean wait) 815 { 816 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_GET_QUERY_RESULT, 0, 2)); 817 virgl_encoder_write_dword(ctx->cbuf, handle); 818 virgl_encoder_write_dword(ctx->cbuf, wait ? 1 : 0); 819 return 0; 820 } 821 822 int virgl_encoder_render_condition(struct virgl_context *ctx, 823 uint32_t handle, boolean condition, 824 uint mode) 825 { 826 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_RENDER_CONDITION, 0, VIRGL_RENDER_CONDITION_SIZE)); 827 virgl_encoder_write_dword(ctx->cbuf, handle); 828 virgl_encoder_write_dword(ctx->cbuf, condition); 829 virgl_encoder_write_dword(ctx->cbuf, mode); 830 return 0; 831 } 832 833 int virgl_encoder_set_so_targets(struct virgl_context *ctx, 834 unsigned num_targets, 835 struct pipe_stream_output_target **targets, 836 unsigned append_bitmask) 837 { 838 int i; 839 840 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_STREAMOUT_TARGETS, 0, num_targets + 1)); 841 virgl_encoder_write_dword(ctx->cbuf, append_bitmask); 842 for (i = 0; i < num_targets; i++) { 843 struct virgl_so_target *tg = virgl_so_target(targets[i]); 844 virgl_encoder_write_dword(ctx->cbuf, tg->handle); 845 } 846 return 0; 847 } 848 849 850 int virgl_encoder_set_sub_ctx(struct virgl_context *ctx, uint32_t sub_ctx_id) 851 { 852 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_SUB_CTX, 0, 1)); 853 virgl_encoder_write_dword(ctx->cbuf, sub_ctx_id); 854 return 0; 855 } 856 857 int virgl_encoder_create_sub_ctx(struct virgl_context *ctx, uint32_t sub_ctx_id) 858 { 859 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_CREATE_SUB_CTX, 0, 1)); 860 virgl_encoder_write_dword(ctx->cbuf, sub_ctx_id); 861 return 0; 862 } 863 864 int virgl_encoder_destroy_sub_ctx(struct virgl_context *ctx, uint32_t sub_ctx_id) 865 { 866 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_DESTROY_SUB_CTX, 0, 1)); 867 virgl_encoder_write_dword(ctx->cbuf, sub_ctx_id); 868 return 0; 869 } 870 871 int virgl_encode_bind_shader(struct virgl_context *ctx, 872 uint32_t handle, uint32_t type) 873 { 874 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_BIND_SHADER, 0, 2)); 875 virgl_encoder_write_dword(ctx->cbuf, handle); 876 virgl_encoder_write_dword(ctx->cbuf, type); 877 return 0; 878 } 879
