| /external/valgrind/none/tests/mips64/ |
| logical_instructions.c | 6 AND=0, ANDI, LUI, NOR,
27 case ANDI:
30 TEST2("andi $t0, $t1, 0xff", reg_val1[i], 0xff, t0, t1);
31 TEST2("andi $t2, $t3, 0xffff", reg_val1[i], 0xffff, t2, t3);
32 TEST2("andi $a0, $a1, 0x0", reg_val1[i], 0x0, a0, a1);
33 TEST2("andi $s0, $s1, 0x23", reg_val1[i], 0x23, s0, s1);
34 TEST2("andi $t0, $t1, 0xff", reg_val2[i], 0xff, t0, t1);
35 TEST2("andi $t2, $t3, 0xffff", reg_val2[i], 0xffff, t2, t3);
36 TEST2("andi $a0, $a1, 0x0", reg_val2[i], 0x0, a0, a1);
37 TEST2("andi $s0, $s1, 0x23", reg_val2[i], 0x23, s0, s1)
[all...] |
| /external/pcre/dist2/src/sljit/ |
| sljitNativeMIPS_32.c | 94 return push_inst(compiler, ANDI | S(src2) | T(dst) | IMM(0xff), DR(dst));
112 return push_inst(compiler, ANDI | S(src2) | T(dst) | IMM(0xffff), DR(dst));
316 EMIT_LOGICAL(ANDI, AND);
|
| sljitNativeMIPS_64.c | 181 return push_inst(compiler, ANDI | S(src2) | T(dst) | IMM(0xff), DR(dst));
195 return push_inst(compiler, ANDI | S(src2) | T(dst) | IMM(0xffff), DR(dst));
411 EMIT_LOGICAL(ANDI, AND);
|
| sljitNativePPC_32.c | 174 return push_inst(compiler, ANDI | S(src1) | A(dst) | compiler->imm);
|
| sljitNativeMIPS_common.c | 103 #define ANDI (HI(12))
[all...] |
| sljitNativeARM_T2_32.c | 99 #define ANDI 0xf0000000
617 return push_inst32(compiler, ANDI | (flags & SET_FLAGS) | RD4(dst) | RN4(reg) | nimm);
[all...] |
| sljitNativePPC_64.c | 301 return push_inst(compiler, ANDI | S(src1) | A(dst) | compiler->imm);
|
| sljitNativeARM_64.c | 69 #define ANDI 0x92000000
598 return push_inst(compiler, (ANDI ^ inv_bits) | RD(dst) | RN(reg) | inst_bits);
[all...] |
| sljitNativePPC_common.c | 144 #define ANDI (HI(28))
[all...] |
| /external/v8/src/mips/ |
| constants-mips.h | 356 ANDI = ((1U << 3) + 4) << kOpcodeShift,
909 OpcodeToBitNumber(ANDI) | OpcodeToBitNumber(ORI) |
[all...] |
| assembler-mips.cc | 700 return GetOpcodeField(instr) == ANDI;
1679 void Assembler::andi(Register rt, Register rs, int32_t j) { function in class:v8::Assembler
[all...] |
| simulator-mips.cc | [all...] |
| /external/v8/src/mips64/ |
| constants-mips64.h | 327 ANDI = ((1U << 3) + 4) << kOpcodeShift,
941 OpcodeToBitNumber(SLTIU) | OpcodeToBitNumber(ANDI) |
[all...] |
| assembler-mips64.cc | 672 return GetOpcodeField(instr) == ANDI;
1763 void Assembler::andi(Register rt, Register rs, int32_t j) { function in class:v8::internal::Assembler
[all...] |
| simulator-mips64.cc | [all...] |
| /system/core/libpixelflinger/codeflinger/ |
| MIPSAssembler.h | 306 void ANDI(int Rd, int Rs, uint16_t imm);
|
| MIPSAssembler.cpp | 431 mMips->ANDI(Rd, Rn, src);
[all...] |
| MIPS64Assembler.cpp | 410 mMips->ANDI(Rd, Rn, src);
[all...] |
| /toolchain/binutils/binutils-2.27/include/opcode/ |
| nios2r1.h | 271 #define MATCH_R1_ANDI MATCH_R1_OP (ANDI)
|
| nios2r2.h | [all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/MBlaze/Disassembler/ |
| MBlazeDisassembler.cpp | 53 MBlaze::ORI, MBlaze::ANDI, MBlaze::XORI, MBlaze::ANDNI, //28,29,2A,2B
|
| /external/swiftshader/third_party/LLVM/lib/Target/MBlaze/ |
| MBlazeISelLowering.cpp | 260 // andi samt, samt, 31
293 BuildMI(MBB, dl, TII->get(MBlaze::ANDI), IAMT)
440 // andi samt, samt, 31
[all...] |
| /toolchain/binutils/binutils-2.27/opcodes/ |
| nds32-asm.c | 246 {"andi", "=rt,%ra,%i15u", OP6 (ANDI), 4, ATTR_ALL, 0, NULL, 0, NULL},
[all...] |
| /toolchain/binutils/binutils-2.27/bfd/ |
| elf32-nds32.c | [all...] |
