| /external/llvm/lib/Target/Hexagon/ |
| BitTracker.h | 255 const BitValue &operator[](uint16_t BitN) const {
256 assert(BitN < Bits.size());
257 return Bits[BitN];
259 BitValue &operator[](uint16_t BitN) {
260 assert(BitN < Bits.size());
261 return Bits[BitN];
387 RegisterCell eSET(const RegisterCell &A1, uint16_t BitN) const;
388 RegisterCell eCLR(const RegisterCell &A1, uint16_t BitN) const;
|
| BitTracker.cpp | 642 uint16_t BitN) const {
643 assert(BitN < A1.width());
645 Res[BitN] = BitValue::One;
651 uint16_t BitN) const {
652 assert(BitN < A1.width());
654 Res[BitN] = BitValue::Zero;
[all...] |
| HexagonGenInsert.cpp | 292 : SelR(R), SelB(B), BitN(N), BitOrd(BO), CM(M) {}
296 const unsigned BitN;
337 uint16_t Bit1 = (VR1 == SelR) ? SelB : BitN;
338 uint16_t Bit2 = (VR2 == SelR) ? SelB : BitN;
[all...] |
| /external/v8/src/arm64/ |
| instructions-arm64.cc | 94 int32_t n = BitN();
|
| assembler-arm64-inl.h | 1067 Instr Assembler::BitN(unsigned bitn, unsigned reg_size) {
1069 DCHECK((reg_size == kXRegSizeInBits) || (bitn == 0));
1071 return bitn << BitN_offset;
[all...] |
| constants-arm64.h | 157 V_(BitN, 22, 22, Bits) \
[all...] |
| assembler-arm64.h | [all...] |
| assembler-arm64.cc | [all...] |
| /external/vixl/src/aarch64/ |
| constants-aarch64.h | 87 V_(BitN, 22, 22, ExtractBits) \
[all...] |
| assembler-aarch64.h | [all...] |
| assembler-aarch64.cc | [all...] |
