1 #ifndef CL_COMMON_DEFINES_H 2 #define CL_COMMON_DEFINES_H 3 // This file includes defines that are common to both kernel code and 4 // the NVPTX back-end. 5 6 // 7 // Common defines for Image intrinsics 8 // Channel order 9 enum { 10 CLK_R = 0x10B0, 11 CLK_A = 0x10B1, 12 CLK_RG = 0x10B2, 13 CLK_RA = 0x10B3, 14 CLK_RGB = 0x10B4, 15 CLK_RGBA = 0x10B5, 16 CLK_BGRA = 0x10B6, 17 CLK_ARGB = 0x10B7, 18 19 #if (__NV_CL_C_VERSION == __NV_CL_C_VERSION_1_0) 20 CLK_xRGB = 0x10B7, 21 #endif 22 23 CLK_INTENSITY = 0x10B8, 24 CLK_LUMINANCE = 0x10B9 25 26 #if (__NV_CL_C_VERSION >= __NV_CL_C_VERSION_1_1) 27 , 28 CLK_Rx = 0x10BA, 29 CLK_RGx = 0x10BB, 30 CLK_RGBx = 0x10BC 31 #endif 32 }; 33 34 typedef enum clk_channel_type { 35 // valid formats for float return types 36 CLK_SNORM_INT8 = 0x10D0, // four channel RGBA unorm8 37 CLK_SNORM_INT16 = 0x10D1, // four channel RGBA unorm16 38 CLK_UNORM_INT8 = 0x10D2, // four channel RGBA unorm8 39 CLK_UNORM_INT16 = 0x10D3, // four channel RGBA unorm16 40 CLK_HALF_FLOAT = 0x10DD, // four channel RGBA half 41 CLK_FLOAT = 0x10DE, // four channel RGBA float 42 43 #if (__NV_CL_C_VERSION >= __NV_CL_C_VERSION_1_1) 44 CLK_UNORM_SHORT_565 = 0x10D4, 45 CLK_UNORM_SHORT_555 = 0x10D5, 46 CLK_UNORM_INT_101010 = 0x10D6, 47 #endif 48 49 // valid only for integer return types 50 CLK_SIGNED_INT8 = 0x10D7, 51 CLK_SIGNED_INT16 = 0x10D8, 52 CLK_SIGNED_INT32 = 0x10D9, 53 CLK_UNSIGNED_INT8 = 0x10DA, 54 CLK_UNSIGNED_INT16 = 0x10DB, 55 CLK_UNSIGNED_INT32 = 0x10DC, 56 57 // CI SPI for CPU 58 __CLK_UNORM_INT8888, // four channel ARGB unorm8 59 __CLK_UNORM_INT8888R, // four channel BGRA unorm8 60 61 __CLK_VALID_IMAGE_TYPE_COUNT, 62 __CLK_INVALID_IMAGE_TYPE = __CLK_VALID_IMAGE_TYPE_COUNT, 63 __CLK_VALID_IMAGE_TYPE_MASK_BITS = 4, // number of bits required to 64 // represent any image type 65 __CLK_VALID_IMAGE_TYPE_MASK = (1 << __CLK_VALID_IMAGE_TYPE_MASK_BITS) - 1 66 } clk_channel_type; 67 68 typedef enum clk_sampler_type { 69 __CLK_ADDRESS_BASE = 0, 70 CLK_ADDRESS_NONE = 0 << __CLK_ADDRESS_BASE, 71 CLK_ADDRESS_CLAMP = 1 << __CLK_ADDRESS_BASE, 72 CLK_ADDRESS_CLAMP_TO_EDGE = 2 << __CLK_ADDRESS_BASE, 73 CLK_ADDRESS_REPEAT = 3 << __CLK_ADDRESS_BASE, 74 CLK_ADDRESS_MIRROR = 4 << __CLK_ADDRESS_BASE, 75 76 #if (__NV_CL_C_VERSION >= __NV_CL_C_VERSION_1_1) 77 CLK_ADDRESS_MIRRORED_REPEAT = CLK_ADDRESS_MIRROR, 78 #endif 79 __CLK_ADDRESS_MASK = 80 CLK_ADDRESS_NONE | CLK_ADDRESS_CLAMP | CLK_ADDRESS_CLAMP_TO_EDGE | 81 CLK_ADDRESS_REPEAT | CLK_ADDRESS_MIRROR, 82 __CLK_ADDRESS_BITS = 3, // number of bits required to 83 // represent address info 84 85 __CLK_NORMALIZED_BASE = __CLK_ADDRESS_BITS, 86 CLK_NORMALIZED_COORDS_FALSE = 0, 87 CLK_NORMALIZED_COORDS_TRUE = 1 << __CLK_NORMALIZED_BASE, 88 __CLK_NORMALIZED_MASK = 89 CLK_NORMALIZED_COORDS_FALSE | CLK_NORMALIZED_COORDS_TRUE, 90 __CLK_NORMALIZED_BITS = 1, // number of bits required to 91 // represent normalization 92 93 __CLK_FILTER_BASE = __CLK_NORMALIZED_BASE + __CLK_NORMALIZED_BITS, 94 CLK_FILTER_NEAREST = 0 << __CLK_FILTER_BASE, 95 CLK_FILTER_LINEAR = 1 << __CLK_FILTER_BASE, 96 CLK_FILTER_ANISOTROPIC = 2 << __CLK_FILTER_BASE, 97 __CLK_FILTER_MASK = 98 CLK_FILTER_NEAREST | CLK_FILTER_LINEAR | CLK_FILTER_ANISOTROPIC, 99 __CLK_FILTER_BITS = 2, // number of bits required to 100 // represent address info 101 102 __CLK_MIP_BASE = __CLK_FILTER_BASE + __CLK_FILTER_BITS, 103 CLK_MIP_NEAREST = 0 << __CLK_MIP_BASE, 104 CLK_MIP_LINEAR = 1 << __CLK_MIP_BASE, 105 CLK_MIP_ANISOTROPIC = 2 << __CLK_MIP_BASE, 106 __CLK_MIP_MASK = CLK_MIP_NEAREST | CLK_MIP_LINEAR | CLK_MIP_ANISOTROPIC, 107 __CLK_MIP_BITS = 2, 108 109 __CLK_SAMPLER_BITS = __CLK_MIP_BASE + __CLK_MIP_BITS, 110 __CLK_SAMPLER_MASK = __CLK_MIP_MASK | __CLK_FILTER_MASK | 111 __CLK_NORMALIZED_MASK | __CLK_ADDRESS_MASK, 112 113 __CLK_ANISOTROPIC_RATIO_BITS = 5, 114 __CLK_ANISOTROPIC_RATIO_MASK = 115 (int) 0x80000000 >> (__CLK_ANISOTROPIC_RATIO_BITS - 1) 116 } clk_sampler_type; 117 118 // Memory synchronization 119 #define CLK_LOCAL_MEM_FENCE (1 << 0) 120 #define CLK_GLOBAL_MEM_FENCE (1 << 1) 121 122 #endif // CL_COMMON_DEFINES_H 123
