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Searched
refs:CMD0
(Results
1 - 6
of
6
) sorted by null
/external/syslinux/gpxe/src/drivers/net/
amd8111e.c
142
writel(RUN, mmio +
CMD0
);
153
/* Clear
CMD0
*/
154
writel(CMD0_CLEAR, mmio +
CMD0
);
224
writel(RUN, mmio +
CMD0
);
261
writel(VAL2 | RDMD0 | VAL0 | RUN, mmio +
CMD0
);
264
readl(mmio +
CMD0
);
356
writel(INTREN, mmio +
CMD0
);
368
writel(VAL0 | INTREN, mmio +
CMD0
);
369
readl(mmio +
CMD0
);
376
writel(VAL0 | UINTCMD, mmio +
CMD0
);
[
all
...]
amd8111e.h
45
Registers
CMD0
, CMD2, CMD3,CMD7 and INTEN0 uses a write access technique called command style access. It allows the write to selected bits of this register without altering the bits that are not selected. Command style registers are divided into 4 bytes that can be written independently. Higher order bit of each byte is the value bit that specifies the value that will be written into the selected bits of register.
61
#define
CMD0
0x48 /* Command0 register */
/device/linaro/bootloader/edk2/QuarkSocPkg/QuarkSouthCluster/Include/
MMC.h
25
#define
CMD0
0
64
#define GO_IDLE_STATE
CMD0
/device/linaro/bootloader/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/IndustryStandard/
Mmc.h
37
#define
CMD0
0
76
#define GO_IDLE_STATE
CMD0
/device/linaro/bootloader/edk2/Omap35xxPkg/Include/Omap3530/
Omap3530MMCHS.h
161
#define
CMD0
INDX(0)
/device/linaro/bootloader/edk2/Omap35xxPkg/MMCHSDxe/
MMCHS.c
422
//Send
CMD0
command.
423
Status = SendCmd (
CMD0
, CMD0_INT_EN, CmdArgument);
425
DEBUG ((EFI_D_ERROR, "
Cmd0
fails.\n"));
429
DEBUG ((EFI_D_INFO, "
CMD0
response: %x\n", MmioRead32 (MMCHS_RSP10)));
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Completed in 104 milliseconds