1 /*++ 2 3 Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved 4 5 This program and the accompanying materials are licensed and made available under 6 the terms and conditions of the BSD License that accompanies this distribution. 7 The full text of the license may be found at 8 http://opensource.org/licenses/bsd-license.php. 9 10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 12 13 14 --*/ 15 16 17 /*++ 18 19 Module Name: 20 21 MMC.h 22 23 Abstract: 24 25 Header file for Industry MMC 4.2 spec. 26 27 --*/ 28 29 #ifndef _MMC_H 30 #define _MMC_H 31 32 #pragma pack(1) 33 // 34 //Command definition 35 // 36 37 #define CMD0 0 38 #define CMD1 1 39 #define CMD2 2 40 #define CMD3 3 41 #define CMD4 4 42 #define CMD6 6 43 #define CMD7 7 44 #define CMD8 8 45 #define CMD9 9 46 #define CMD10 10 47 #define CMD11 11 48 #define CMD12 12 49 #define CMD13 13 50 #define CMD14 14 51 #define CMD15 15 52 #define CMD16 16 53 #define CMD17 17 54 #define CMD18 18 55 #define CMD19 19 56 #define CMD20 20 57 #define CMD23 23 58 #define CMD24 24 59 #define CMD25 25 60 #define CMD26 26 61 #define CMD27 27 62 #define CMD28 28 63 #define CMD29 29 64 #define CMD30 30 65 #define CMD35 35 66 #define CMD36 36 67 #define CMD38 38 68 #define CMD39 39 69 #define CMD40 40 70 #define CMD42 42 71 #define CMD55 55 72 #define CMD56 56 73 74 75 76 #define GO_IDLE_STATE CMD0 77 #define SEND_OP_COND CMD1 78 #define ALL_SEND_CID CMD2 79 #define SET_RELATIVE_ADDR CMD3 80 #define SET_DSR CMD4 81 #define SWITCH CMD6 82 #define SELECT_DESELECT_CARD CMD7 83 #define SEND_EXT_CSD CMD8 84 #define SEND_CSD CMD9 85 #define SEND_CID CMD10 86 #define READ_DAT_UNTIL_STOP CMD11 87 #define STOP_TRANSMISSION CMD12 88 #define SEND_STATUS CMD13 89 #define BUSTEST_R CMD14 90 #define GO_INACTIVE_STATE CMD15 91 #define SET_BLOCKLEN CMD16 92 #define READ_SINGLE_BLOCK CMD17 93 #define READ_MULTIPLE_BLOCK CMD18 94 #define BUSTEST_W CMD19 95 #define WRITE_DAT_UNTIL_STOP CMD20 96 #define SET_BLOCK_COUNT CMD23 97 #define WRITE_BLOCK CMD24 98 #define WRITE_MULTIPLE_BLOCK CMD25 99 #define PROGRAM_CID CMD26 100 #define PROGRAM_CSD CMD27 101 #define SET_WRITE_PROT CMD28 102 #define CLR_WRITE_PROT CMD29 103 #define SEND_WRITE_PROT CMD30 104 #define ERASE_GROUP_START CMD35 105 #define ERASE_GROUP_END CMD36 106 #define ERASE CMD38 107 #define FAST_IO CMD39 108 #define GO_IRQ_STATE CMD40 109 #define LOCK_UNLOCK CMD42 110 #define APP_CMD CMD55 111 #define GEN_CMD CMD56 112 113 #define B_PERM_WP_DIS 0x10 114 #define B_PWR_WP_EN 0x01 115 #define US_PERM_WP_DIS 0x10 116 #define US_PWR_WP_EN 0x01 117 118 #define FREQUENCY_OD (400 * 1000) 119 #define FREQUENCY_MMC_PP (26 * 1000 * 1000) 120 #define FREQUENCY_MMC_PP_HIGH (52 * 1000 * 1000) 121 122 #define DEFAULT_DSR_VALUE 0x404 123 124 // 125 //Registers definition 126 // 127 128 typedef struct { 129 UINT32 Reserved0: 7; // 0 130 UINT32 V170_V195: 1; // 1.70V - 1.95V 131 UINT32 V200_V260: 7; // 2.00V - 2.60V 132 UINT32 V270_V360: 9; // 2.70V - 3.60V 133 UINT32 Reserved1: 5; // 0 134 UINT32 AccessMode: 2; // 00b (byte mode), 10b (sector mode) 135 UINT32 Busy: 1; // This bit is set to LOW if the card has not finished the power up routine 136 } OCR; 137 138 139 typedef struct { 140 UINT8 NotUsed: 1; // 1 141 UINT8 CRC: 7; // CRC7 checksum 142 UINT8 MDT; // Manufacturing date 143 UINT32 PSN; // Product serial number 144 UINT8 PRV; // Product revision 145 UINT8 PNM[6]; // Product name 146 UINT16 OID; // OEM/Application ID 147 UINT8 MID; // Manufacturer ID 148 } CID; 149 150 151 typedef struct { 152 UINT8 NotUsed: 1; // 1 [0:0] 153 UINT8 CRC: 7; // CRC [7:1] 154 UINT8 ECC: 2; // ECC code [9:8] 155 UINT8 FILE_FORMAT: 2; // File format [11:10] 156 UINT8 TMP_WRITE_PROTECT: 1; // Temporary write protection [12:12] 157 UINT8 PERM_WRITE_PROTECT: 1; // Permanent write protection [13:13] 158 UINT8 COPY: 1; // Copy flag (OTP) [14:14] 159 UINT8 FILE_FORMAT_GRP: 1; // File format group [15:15] 160 UINT16 CONTENT_PROT_APP: 1; // Content protection application [16:16] 161 UINT16 Reserved0: 4; // 0 [20:17] 162 UINT16 WRITE_BL_PARTIAL: 1; // Partial blocks for write allowed [21:21] 163 UINT16 WRITE_BL_LEN: 4; // Max. write data block length [25:22] 164 UINT16 R2W_FACTOR: 3; // Write speed factor [28:26] 165 UINT16 DEFAULT_ECC: 2; // Manufacturer default ECC [30:29] 166 UINT16 WP_GRP_ENABLE: 1; // Write protect group enable [31:31] 167 UINT32 WP_GRP_SIZE: 5; // Write protect group size [36:32] 168 UINT32 ERASE_GRP_MULT: 5; // Erase group size multiplier [41:37] 169 UINT32 ERASE_GRP_SIZE: 5; // Erase group size [46:42] 170 UINT32 C_SIZE_MULT: 3; // Device size multiplier [49:47] 171 UINT32 VDD_W_CURR_MAX: 3; // Max. write current @ VDD max [52:50] 172 UINT32 VDD_W_CURR_MIN: 3; // Max. write current @ VDD min [55:53] 173 UINT32 VDD_R_CURR_MAX: 3; // Max. read current @ VDD max [58:56] 174 UINT32 VDD_R_CURR_MIN: 3; // Max. read current @ VDD min [61:59] 175 UINT32 C_SIZELow2: 2;// Device size [73:62] 176 UINT32 C_SIZEHigh10: 10;// Device size [73:62] 177 UINT32 Reserved1: 2; // 0 [75:74] 178 UINT32 DSR_IMP: 1; // DSR implemented [76:76] 179 UINT32 READ_BLK_MISALIGN: 1; // Read block misalignment [77:77] 180 UINT32 WRITE_BLK_MISALIGN: 1; // Write block misalignment [78:78] 181 UINT32 READ_BL_PARTIAL: 1; // Partial blocks for read allowed [79:79] 182 UINT32 READ_BL_LEN: 4; // Max. read data block length [83:80] 183 UINT32 CCC: 12;// Card command classes [95:84] 184 UINT8 TRAN_SPEED ; // Max. bus clock frequency [103:96] 185 UINT8 NSAC ; // Data read access-time 2 in CLK cycles (NSAC*100) [111:104] 186 UINT8 TAAC ; // Data read access-time 1 [119:112] 187 UINT8 Reserved2: 2; // 0 [121:120] 188 UINT8 SPEC_VERS: 4; // System specification version [125:122] 189 UINT8 CSD_STRUCTURE: 2; // CSD structure [127:126] 190 } CSD; 191 192 typedef struct { 193 UINT8 Reserved133_0[134]; // [133:0] 0 194 UINT8 SEC_BAD_BLOCK_MGMNT; // [134] Bad Block Management mode 195 UINT8 Reserved135; // [135] 0 196 UINT8 ENH_START_ADDR[4]; // [139:136] Enhanced User Data Start Address 197 UINT8 ENH_SIZE_MULT[3]; // [142:140] Enhanced User Data Start Size 198 UINT8 GP_SIZE_MULT_1[3]; // [145:143] GPP1 Size 199 UINT8 GP_SIZE_MULT_2[3]; // [148:146] GPP2 Size 200 UINT8 GP_SIZE_MULT_3[3]; // [151:149] GPP3 Size 201 UINT8 GP_SIZE_MULT_4[3]; // [154:152] GPP4 Size 202 UINT8 PARTITION_SETTING_COMPLETED; // [155] Partitioning Setting 203 UINT8 PARTITIONS_ATTRIBUTES; // [156] Partitions attributes 204 UINT8 MAX_ENH_SIZE_MULT[3]; // [159:157] GPP4 Start Size 205 UINT8 PARTITIONING_SUPPORT; // [160] Partitioning Support 206 UINT8 HPI_MGMT; // [161] HPI management 207 UINT8 RST_n_FUNCTION; // [162] H/W reset function 208 UINT8 BKOPS_EN; // [163] Enable background operations handshake 209 UINT8 BKOPS_START; // [164] Manually start background operations 210 UINT8 Reserved165; // [165] 0 211 UINT8 WR_REL_PARAM; // [166] Write reliability parameter register 212 UINT8 WR_REL_SET; // [167] Write reliability setting register 213 UINT8 RPMB_SIZE_MULT; // [168] RPMB Size 214 UINT8 FW_CONFIG; // [169] FW configuration 215 UINT8 Reserved170; // [170] 0 216 UINT8 USER_WP; // [171] User area write protection 217 UINT8 Reserved172; // [172] 0 218 UINT8 BOOT_WP; // [173] Boot area write protection 219 UINT8 Reserved174; // [174] 0 220 UINT8 ERASE_GROUP_DEF; // [175] High density erase group definition 221 UINT8 Reserved176; // [176] 0 222 UINT8 BOOT_BUS_WIDTH; // [177] Boot bus width 223 UINT8 BOOT_CONFIG_PROT; // [178] Boot config protection 224 UINT8 PARTITION_CONFIG; // [179] Partition config 225 UINT8 Reserved180; // [180] 0 226 UINT8 ERASED_MEM_CONT; // [181] Erased Memory Content 227 UINT8 Reserved182; // [182] 0 228 UINT8 BUS_WIDTH; // [183] Bus Width Mode 229 UINT8 Reserved184; // [184] 0 230 UINT8 HS_TIMING; // [185] High Speed Interface Timing 231 UINT8 Reserved186; // [186] 0 232 UINT8 POWER_CLASS; // [187] Power Class 233 UINT8 Reserved188; // [188] 0 234 UINT8 CMD_SET_REV; // [189] Command Set Revision 235 UINT8 Reserved190; // [190] 0 236 UINT8 CMD_SET; // [191] Command Set 237 UINT8 EXT_CSD_REV; // [192] Extended CSD Revision 238 UINT8 Reserved193; // [193] 0 239 UINT8 CSD_STRUCTURE; // [194] CSD Structure Version 240 UINT8 Reserved195; // [195] 0 241 UINT8 CARD_TYPE; // [196] Card Type 242 UINT8 Reserved197; // [197] 0 243 UINT8 OUT_OF_INTERRUPT_TIME; // [198] Out-of-interrupt busy timing 244 UINT8 PARTITION_SWITCH_TIME; // [199] Partition switching timing 245 UINT8 PWR_CL_52_195; // [200] Power Class for 52MHz @ 1.95V 246 UINT8 PWR_CL_26_195; // [201] Power Class for 26MHz @ 1.95V 247 UINT8 PWR_CL_52_360; // [202] Power Class for 52MHz @ 3.6V 248 UINT8 PWR_CL_26_360; // [203] Power Class for 26MHz @ 3.6V 249 UINT8 Reserved204; // [204] 0 250 UINT8 MIN_PERF_R_4_26; // [205] Minimum Read Performance for 4bit @26MHz 251 UINT8 MIN_PERF_W_4_26; // [206] Minimum Write Performance for 4bit @26MHz 252 UINT8 MIN_PERF_R_8_26_4_52; // [207] Minimum Read Performance for 8bit @26MHz/4bit @52MHz 253 UINT8 MIN_PERF_W_8_26_4_52; // [208] Minimum Write Performance for 8bit @26MHz/4bit @52MHz 254 UINT8 MIN_PERF_R_8_52; // [209] Minimum Read Performance for 8bit @52MHz 255 UINT8 MIN_PERF_W_8_52; // [210] Minimum Write Performance for 8bit @52MHz 256 UINT8 Reserved211; // [211] 0 257 UINT8 SEC_COUNT[4]; // [215:212] Sector Count 258 UINT8 Reserved216; // [216] 0 259 UINT8 S_A_TIMEOUT; // [217] Sleep/awake timeout 260 UINT8 Reserved218; // [218] 0 261 UINT8 S_C_VCCQ; // [219] Sleep current (VCCQ) 262 UINT8 S_C_VCC; // [220] Sleep current (VCC) 263 UINT8 HC_WP_GRP_SIZE; // [221] High-capacity write protect group size 264 UINT8 REL_WR_SEC_C; // [222] Reliable write sector count 265 UINT8 ERASE_TIMEOUT_MULT; // [223] High-capacity erase timeout 266 UINT8 HC_ERASE_GRP_SIZE; // [224] High-capacity erase unit size 267 UINT8 ACC_SIZE; // [225] Access size 268 UINT8 BOOT_SIZE_MULTI; // [226] Boot partition size 269 UINT8 Reserved227; // [227] 0 270 UINT8 BOOT_INFO; // [228] Boot information 271 UINT8 SEC_TRIM_MULT; // [229] Secure TRIM Multiplier 272 UINT8 SEC_ERASE_MULT; // [230] Secure Erase Multiplier 273 UINT8 SEC_FEATURE_SUPPORT; // [231] Secure Feature support 274 UINT8 TRIM_MULT; // [232] TRIM Multiplier 275 UINT8 Reserved233; // [233] 0 276 UINT8 MIN_PERF_DDR_R_8_52; // [234] Min Read Performance for 8-bit @ 52MHz 277 UINT8 MIN_PERF_DDR_W_8_52; // [235] Min Write Performance for 8-bit @ 52MHz 278 UINT8 Reserved237_236[2]; // [237:236] 0 279 UINT8 PWR_CL_DDR_52_195; // [238] Power class for 52MHz, DDR at 1.95V 280 UINT8 PWR_CL_DDR_52_360; // [239] Power class for 52MHz, DDR at 3.6V 281 UINT8 Reserved240; // [240] 0 282 UINT8 INI_TIMEOUT_AP; // [241] 1st initialization time after partitioning 283 UINT8 CORRECTLY_PRG_SECTORS_NUM[4]; // [245:242] Number of correctly programmed sectors 284 UINT8 BKOPS_STATUS; // [246] Background operations status 285 UINT8 Reserved501_247[255]; // [501:247] 0 286 UINT8 BKOPS_SUPPORT; // [502] Background operations support 287 UINT8 HPI_FEATURES; // [503] HPI features 288 UINT8 S_CMD_SET; // [504] Sector Count 289 UINT8 Reserved511_505[7]; // [511:505] Sector Count 290 } EXT_CSD; 291 292 293 // 294 //Card Status definition 295 // 296 typedef struct { 297 UINT32 Reserved0: 2; //Reserved for Manufacturer Test Mode 298 UINT32 Reserved1: 2; //Reserved for Application Specific commands 299 UINT32 Reserved2: 1; // 300 UINT32 SAPP_CMD: 1; // 301 UINT32 Reserved3: 1; //Reserved 302 UINT32 SWITCH_ERROR: 1; // 303 UINT32 READY_FOR_DATA: 1; // 304 UINT32 CURRENT_STATE: 4; // 305 UINT32 ERASE_RESET: 1; // 306 UINT32 Reserved4: 1; //Reserved 307 UINT32 WP_ERASE_SKIP: 1; // 308 UINT32 CID_CSD_OVERWRITE: 1; // 309 UINT32 OVERRUN: 1; // 310 UINT32 UNDERRUN: 1; // 311 UINT32 ERROR: 1; // 312 UINT32 CC_ERROR: 1; // 313 UINT32 CARD_ECC_FAILED: 1; // 314 UINT32 ILLEGAL_COMMAND: 1; // 315 UINT32 COM_CRC_ERROR: 1; // 316 UINT32 LOCK_UNLOCK_FAILED: 1; // 317 UINT32 CARD_IS_LOCKED: 1; // 318 UINT32 WP_VIOLATION: 1; // 319 UINT32 ERASE_PARAM: 1; // 320 UINT32 ERASE_SEQ_ERROR: 1; // 321 UINT32 BLOCK_LEN_ERROR: 1; // 322 UINT32 ADDRESS_MISALIGN: 1; // 323 UINT32 ADDRESS_OUT_OF_RANGE:1; // 324 } CARD_STATUS; 325 326 typedef struct { 327 UINT32 CmdSet: 3; 328 UINT32 Reserved0: 5; 329 UINT32 Value: 8; 330 UINT32 Index: 8; 331 UINT32 Access: 2; 332 UINT32 Reserved1: 6; 333 } SWITCH_ARGUMENT; 334 335 #define CommandSet_Mode 0 336 #define SetBits_Mode 1 337 #define ClearBits_Mode 2 338 #define WriteByte_Mode 3 339 340 341 #define Idle_STATE 0 342 #define Ready_STATE 1 343 #define Ident_STATE 2 344 #define Stby_STATE 3 345 #define Tran_STATE 4 346 #define Data_STATE 5 347 #define Rcv_STATE 6 348 #define Prg_STATE 7 349 #define Dis_STATE 8 350 #define Btst_STATE 9 351 352 353 354 #pragma pack() 355 #endif 356
