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    Searched refs:CMD2 (Results 1 - 7 of 7) sorted by null

  /device/linaro/bootloader/edk2/QuarkSocPkg/QuarkSouthCluster/Include/
MMC.h 27 #define CMD2 2
66 #define ALL_SEND_CID CMD2
  /device/linaro/bootloader/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/IndustryStandard/
Mmc.h 39 #define CMD2 2
78 #define ALL_SEND_CID CMD2
  /external/syslinux/gpxe/src/drivers/net/
amd8111e.c 156 /* Clear CMD2 */
157 writel(CMD2_CLEAR, mmio + CMD2);
211 readl(mmio + CMD2);
251 writel(VAL0 | APAD_XMT | REX_RTRY | REX_UFLO, mmio + CMD2);
amd8111e.h 45 Registers CMD0, CMD2, CMD3,CMD7 and INTEN0 uses a write access technique called command style access. It allows the write to selected bits of this register without altering the bits that are not selected. Command style registers are divided into 4 bytes that can be written independently. Higher order bit of each byte is the value bit that specifies the value that will be written into the selected bits of register.
62 #define CMD2 0x50 /* Command2 register */
  /device/linaro/bootloader/edk2/Omap35xxPkg/Include/Omap3530/
Omap3530MMCHS.h 167 #define CMD2 (INDX(2) | CCCE_ENABLE | RSP_TYPE_136BITS)
  /device/linaro/bootloader/edk2/Omap35xxPkg/MmcHostDxe/
MmcHostDxe.c 69 Translation = CMD2;
  /device/linaro/bootloader/edk2/Omap35xxPkg/MMCHSDxe/
MMCHS.c 541 Status = SendCmd (CMD2, CMD2_INT_EN, CmdArgument);
543 DEBUG ((EFI_D_ERROR, "CMD2 fails. Status: %x\n", Status));
547 DEBUG ((EFI_D_INFO, "CMD2 response: %x %x %x %x\n", MmioRead32 (MMCHS_RSP10), MmioRead32 (MMCHS_RSP32), MmioRead32 (MMCHS_RSP54), MmioRead32 (MMCHS_RSP76)));
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