1 /** @file 2 3 Header file for Industry MMC 4.2 spec. 4 5 Copyright (c) 2013-2015 Intel Corporation. 6 7 This program and the accompanying materials 8 are licensed and made available under the terms and conditions of the BSD License 9 which accompanies this distribution. The full text of the license may be found at 10 http://opensource.org/licenses/bsd-license.php 11 12 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 13 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 14 15 **/ 16 17 #ifndef _MMC_H 18 #define _MMC_H 19 20 #pragma pack(1) 21 // 22 //Command definition 23 // 24 25 #define CMD0 0 26 #define CMD1 1 27 #define CMD2 2 28 #define CMD3 3 29 #define CMD4 4 30 #define CMD6 6 31 #define CMD7 7 32 #define CMD8 8 33 #define CMD9 9 34 #define CMD10 10 35 #define CMD11 11 36 #define CMD12 12 37 #define CMD13 13 38 #define CMD14 14 39 #define CMD15 15 40 #define CMD16 16 41 #define CMD17 17 42 #define CMD18 18 43 #define CMD19 19 44 #define CMD20 20 45 #define CMD23 23 46 #define CMD24 24 47 #define CMD25 25 48 #define CMD26 26 49 #define CMD27 27 50 #define CMD28 28 51 #define CMD29 29 52 #define CMD30 30 53 #define CMD35 35 54 #define CMD36 36 55 #define CMD38 38 56 #define CMD39 39 57 #define CMD40 40 58 #define CMD42 42 59 #define CMD55 55 60 #define CMD56 56 61 62 63 64 #define GO_IDLE_STATE CMD0 65 #define SEND_OP_COND CMD1 66 #define ALL_SEND_CID CMD2 67 #define SET_RELATIVE_ADDR CMD3 68 #define SET_DSR CMD4 69 #define SWITCH CMD6 70 #define SELECT_DESELECT_CARD CMD7 71 #define SEND_EXT_CSD CMD8 72 #define SEND_CSD CMD9 73 #define SEND_CID CMD10 74 #define READ_DAT_UNTIL_STOP CMD11 75 #define STOP_TRANSMISSION CMD12 76 #define SEND_STATUS CMD13 77 #define BUSTEST_R CMD14 78 #define GO_INACTIVE_STATE CMD15 79 #define SET_BLOCKLEN CMD16 80 #define READ_SINGLE_BLOCK CMD17 81 #define READ_MULTIPLE_BLOCK CMD18 82 #define BUSTEST_W CMD19 83 #define WRITE_DAT_UNTIL_STOP CMD20 84 #define SET_BLOCK_COUNT CMD23 85 #define WRITE_BLOCK CMD24 86 #define WRITE_MULTIPLE_BLOCK CMD25 87 #define PROGRAM_CID CMD26 88 #define PROGRAM_CSD CMD27 89 #define SET_WRITE_PROT CMD28 90 #define CLR_WRITE_PROT CMD29 91 #define SEND_WRITE_PROT CMD30 92 #define ERASE_GROUP_START CMD35 93 #define ERASE_GROUP_END CMD36 94 #define ERASE CMD38 95 #define FAST_IO CMD39 96 #define GO_IRQ_STATE CMD40 97 #define LOCK_UNLOCK CMD42 98 #define APP_CMD CMD55 99 #define GEN_CMD CMD56 100 101 102 #define CMD_INDEX_MASK 0x3F 103 #define AUTO_CMD12_ENABLE BIT6 104 #define AUTO_CMD23_ENABLE BIT7 105 106 #define FREQUENCY_OD (400 * 1000) 107 #define FREQUENCY_MMC_PP (26 * 1000 * 1000) 108 #define FREQUENCY_MMC_PP_HIGH (52 * 1000 * 1000) 109 110 #define DEFAULT_DSR_VALUE 0x404 111 112 // 113 //Registers definition 114 // 115 116 typedef struct { 117 UINT32 Reserved0: 7; // 0 118 UINT32 V170_V195: 1; // 1.70V - 1.95V 119 UINT32 V200_V260: 7; // 2.00V - 2.60V 120 UINT32 V270_V360: 9; // 2.70V - 3.60V 121 UINT32 Reserved1: 5; // 0 122 UINT32 AccessMode: 2; // 00b (byte mode), 10b (sector mode) 123 UINT32 Busy: 1; // This bit is set to LOW if the card has not finished the power up routine 124 }OCR; 125 126 127 typedef struct { 128 UINT8 NotUsed: 1; // 1 129 UINT8 CRC: 7; // CRC7 checksum 130 UINT8 MDT; // Manufacturing date 131 UINT32 PSN; // Product serial number 132 UINT8 PRV; // Product revision 133 UINT8 PNM[6]; // Product name 134 UINT16 OID; // OEM/Application ID 135 UINT8 MID; // Manufacturer ID 136 }CID; 137 138 139 typedef struct { 140 UINT8 NotUsed: 1; // 1 [0:0] 141 UINT8 CRC: 7; // CRC [7:1] 142 UINT8 ECC: 2; // ECC code [9:8] 143 UINT8 FILE_FORMAT: 2; // File format [11:10] 144 UINT8 TMP_WRITE_PROTECT: 1; // Temporary write protection [12:12] 145 UINT8 PERM_WRITE_PROTECT: 1; // Permanent write protection [13:13] 146 UINT8 COPY: 1; // Copy flag (OTP) [14:14] 147 UINT8 FILE_FORMAT_GRP: 1; // File format group [15:15] 148 UINT16 CONTENT_PROT_APP: 1; // Content protection application [16:16] 149 UINT16 Reserved0: 4; // 0 [20:17] 150 UINT16 WRITE_BL_PARTIAL: 1; // Partial blocks for write allowed [21:21] 151 UINT16 WRITE_BL_LEN: 4; // Max. write data block length [25:22] 152 UINT16 R2W_FACTOR: 3; // Write speed factor [28:26] 153 UINT16 DEFAULT_ECC: 2; // Manufacturer default ECC [30:29] 154 UINT16 WP_GRP_ENABLE: 1; // Write protect group enable [31:31] 155 UINT32 WP_GRP_SIZE: 5; // Write protect group size [36:32] 156 UINT32 ERASE_GRP_MULT: 5; // Erase group size multiplier [41:37] 157 UINT32 ERASE_GRP_SIZE: 5; // Erase group size [46:42] 158 UINT32 C_SIZE_MULT: 3; // Device size multiplier [49:47] 159 UINT32 VDD_W_CURR_MAX: 3; // Max. write current @ VDD max [52:50] 160 UINT32 VDD_W_CURR_MIN: 3; // Max. write current @ VDD min [55:53] 161 UINT32 VDD_R_CURR_MAX: 3; // Max. read current @ VDD max [58:56] 162 UINT32 VDD_R_CURR_MIN: 3; // Max. read current @ VDD min [61:59] 163 UINT32 C_SIZELow2: 2;// Device size [73:62] 164 UINT32 C_SIZEHigh10: 10;// Device size [73:62] 165 UINT32 Reserved1: 2; // 0 [75:74] 166 UINT32 DSR_IMP: 1; // DSR implemented [76:76] 167 UINT32 READ_BLK_MISALIGN: 1; // Read block misalignment [77:77] 168 UINT32 WRITE_BLK_MISALIGN: 1; // Write block misalignment [78:78] 169 UINT32 READ_BL_PARTIAL: 1; // Partial blocks for read allowed [79:79] 170 UINT32 READ_BL_LEN: 4; // Max. read data block length [83:80] 171 UINT32 CCC: 12;// Card command classes [95:84] 172 UINT8 TRAN_SPEED ; // Max. bus clock frequency [103:96] 173 UINT8 NSAC ; // Data read access-time 2 in CLK cycles (NSAC*100) [111:104] 174 UINT8 TAAC ; // Data read access-time 1 [119:112] 175 UINT8 Reserved2: 2; // 0 [121:120] 176 UINT8 SPEC_VERS: 4; // System specification version [125:122] 177 UINT8 CSD_STRUCTURE: 2; // CSD structure [127:126] 178 }CSD; 179 180 typedef struct { 181 UINT8 Reserved0[181]; // 0 [0:180] 182 UINT8 ERASED_MEM_CONT; // Erased Memory Content [181] 183 UINT8 Reserved2; // Erased Memory Content [182] 184 UINT8 BUS_WIDTH; // Bus Width Mode [183] 185 UINT8 Reserved3; // 0 [184] 186 UINT8 HS_TIMING; // High Speed Interface Timing [185] 187 UINT8 Reserved4; // 0 [186] 188 UINT8 POWER_CLASS; // Power Class [187] 189 UINT8 Reserved5; // 0 [188] 190 UINT8 CMD_SET_REV; // Command Set Revision [189] 191 UINT8 Reserved6; // 0 [190] 192 UINT8 CMD_SET; // Command Set [191] 193 UINT8 EXT_CSD_REV; // Extended CSD Revision [192] 194 UINT8 Reserved7; // 0 [193] 195 UINT8 CSD_STRUCTURE; // CSD Structure Version [194] 196 UINT8 Reserved8; // 0 [195] 197 UINT8 CARD_TYPE; // Card Type [196] 198 UINT8 Reserved9[3]; // 0 [199:197] 199 UINT8 PWR_CL_52_195; // Power Class for 52MHz @ 1.95V [200] 200 UINT8 PWR_CL_26_195; // Power Class for 26MHz @ 1.95V [201] 201 UINT8 PWR_CL_52_360; // Power Class for 52MHz @ 3.6V [202] 202 UINT8 PWR_CL_26_360; // Power Class for 26MHz @ 3.6V [203] 203 UINT8 Reserved10; // 0 [204] 204 UINT8 MIN_PERF_R_4_26; // Minimum Read Performance for 4bit @26MHz [205] 205 UINT8 MIN_PERF_W_4_26; // Minimum Write Performance for 4bit @26MHz [206] 206 UINT8 MIN_PERF_R_8_26_4_52; // Minimum Read Performance for 8bit @26MHz/4bit @52MHz [207] 207 UINT8 MIN_PERF_W_8_26_4_52; // Minimum Write Performance for 8bit @26MHz/4bit @52MHz [208] 208 UINT8 MIN_PERF_R_8_52; // Minimum Read Performance for 8bit @52MHz [209] 209 UINT8 MIN_PERF_W_8_52; // Minimum Write Performance for 8bit @52MHz [210] 210 UINT8 Reserved11; // 0 [211] 211 UINT8 SEC_COUNT[4]; // Sector Count [215:212] 212 UINT8 Reserved12[288]; // 0 [503:216] 213 UINT8 S_CMD_SET; // Sector Count [504] 214 UINT8 Reserved13[7]; // Sector Count [511:505] 215 }EXT_CSD; 216 217 218 // 219 //Card Status definition 220 // 221 typedef struct { 222 UINT32 Reserved0: 2; //Reserved for Manufacturer Test Mode 223 UINT32 Reserved1: 2; //Reserved for Application Specific commands 224 UINT32 Reserved2: 1; // 225 UINT32 SAPP_CMD: 1; // 226 UINT32 Reserved3: 1; //Reserved 227 UINT32 SWITCH_ERROR: 1; // 228 UINT32 READY_FOR_DATA: 1; // 229 UINT32 CURRENT_STATE: 4; // 230 UINT32 ERASE_RESET: 1; // 231 UINT32 Reserved4: 1; //Reserved 232 UINT32 WP_ERASE_SKIP: 1; // 233 UINT32 CID_CSD_OVERWRITE: 1; // 234 UINT32 OVERRUN: 1; // 235 UINT32 UNDERRUN: 1; // 236 UINT32 ERROR: 1; // 237 UINT32 CC_ERROR: 1; // 238 UINT32 CARD_ECC_FAILED: 1; // 239 UINT32 ILLEGAL_COMMAND: 1; // 240 UINT32 COM_CRC_ERROR: 1; // 241 UINT32 LOCK_UNLOCK_FAILED: 1; // 242 UINT32 CARD_IS_LOCKED: 1; // 243 UINT32 WP_VIOLATION: 1; // 244 UINT32 ERASE_PARAM: 1; // 245 UINT32 ERASE_SEQ_ERROR: 1; // 246 UINT32 BLOCK_LEN_ERROR: 1; // 247 UINT32 ADDRESS_MISALIGN: 1; // 248 UINT32 ADDRESS_OUT_OF_RANGE:1; // 249 }CARD_STATUS; 250 251 typedef struct { 252 UINT32 CmdSet: 3; 253 UINT32 Reserved0: 5; 254 UINT32 Value: 8; 255 UINT32 Index: 8; 256 UINT32 Access: 2; 257 UINT32 Reserved1: 6; 258 }SWITCH_ARGUMENT; 259 260 #define CommandSet_Mode 0 261 #define SetBits_Mode 1 262 #define ClearBits_Mode 2 263 #define WriteByte_Mode 3 264 265 266 #define Idle_STATE 0 267 #define Ready_STATE 1 268 #define Ident_STATE 2 269 #define Stby_STATE 3 270 #define Tran_STATE 4 271 #define Data_STATE 5 272 #define Rcv_STATE 6 273 #define Prg_STATE 7 274 #define Dis_STATE 8 275 #define Btst_STATE 9 276 277 278 279 #pragma pack() 280 #endif 281
