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Searched
refs:FP0
(Results
1 - 9
of
9
) sorted by null
/external/llvm/lib/Target/X86/
X86FloatingPoint.cpp
101
// Bit mask of live FP registers. Bit 0 =
FP0
, bit 1 = FP1, &c.
129
if (LI.PhysReg < X86::
FP0
|| LI.PhysReg > X86::FP6)
131
Mask |= 1 << (LI.PhysReg - X86::
FP0
);
153
// The first entries correspond to
FP0
-FP6, the rest are scratch registers
296
assert(Reg >= X86::
FP0
&& Reg <= X86::FP6 && "Expected FP register!");
297
return Reg - X86::
FP0
;
308
static_assert(X86::FP6 == X86::
FP0
+6, "Register enums aren't sorted right!");
311
if (!MRI.reg_nodbg_empty(X86::
FP0
+ i)) {
430
if (Reg >= X86::
FP0
&& Reg <= X86::FP6 && isLive(Reg-X86::
FP0
)) {
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X86FastISel.cpp
[
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...]
X86ISelLowering.cpp
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/external/swiftshader/third_party/LLVM/lib/Target/X86/
X86FloatingPoint.cpp
90
// Bit mask of live FP registers. Bit 0 =
FP0
, bit 1 = FP1, &c.
119
unsigned Reg = *I - X86::
FP0
;
143
// The first entries correspond to
FP0
-FP6, the rest are scratch registers
331
assert(Reg >= X86::
FP0
&& Reg <= X86::FP6 && "Expected FP register!");
332
return Reg - X86::
FP0
;
343
assert(X86::FP6 == X86::
FP0
+6 && "Register enums aren't sorted right!");
345
if (MF.getRegInfo().isPhysRegUsed(X86::
FP0
+i)) {
462
if (Reg >= X86::
FP0
&& Reg <= X86::FP6) {
463
DEBUG(dbgs() << "Register FP#" << Reg-X86::
FP0
<< " is dead!\n");
464
freeStackSlotAfter(I, Reg-X86::
FP0
);
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all
...]
/toolchain/binutils/binutils-2.27/gas/config/
m68k-parse.h
64
FP0
, /* Eight FP registers */
m68k-parse.y
661
$$ = $1 -
FP0
+ 16;
856
else if (reg >=
FP0
&& reg <= FP7)
tc-i960.c
320
#define
FP0
64
322
{ "
fp0
", 64 },
331
#define IS_SF_REG(n) ((SF0 <= (n)) && ((n) <
FP0
))
332
#define IS_FP_REG(n) ((n) >=
FP0
)
740
regopP->n = n -
FP0
;
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...]
tc-m68k.c
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...]
/external/llvm/lib/Target/X86/MCTargetDesc/
X86MCTargetDesc.cpp
91
MRI->mapLLVMRegToCVReg(X86::
FP0
+ I, FP0Start + I);
Completed in 133 milliseconds