1 //===-- X86FloatingPoint.cpp - Floating point Reg -> Stack converter ------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines the pass which converts floating point instructions from 11 // pseudo registers into register stack instructions. This pass uses live 12 // variable information to indicate where the FPn registers are used and their 13 // lifetimes. 14 // 15 // The x87 hardware tracks liveness of the stack registers, so it is necessary 16 // to implement exact liveness tracking between basic blocks. The CFG edges are 17 // partitioned into bundles where the same FP registers must be live in 18 // identical stack positions. Instructions are inserted at the end of each basic 19 // block to rearrange the live registers to match the outgoing bundle. 20 // 21 // This approach avoids splitting critical edges at the potential cost of more 22 // live register shuffling instructions when critical edges are present. 23 // 24 //===----------------------------------------------------------------------===// 25 26 #include "X86.h" 27 #include "X86InstrInfo.h" 28 #include "llvm/ADT/DepthFirstIterator.h" 29 #include "llvm/ADT/STLExtras.h" 30 #include "llvm/ADT/SmallPtrSet.h" 31 #include "llvm/ADT/SmallSet.h" 32 #include "llvm/ADT/SmallVector.h" 33 #include "llvm/ADT/Statistic.h" 34 #include "llvm/CodeGen/EdgeBundles.h" 35 #include "llvm/CodeGen/LivePhysRegs.h" 36 #include "llvm/CodeGen/MachineFunctionPass.h" 37 #include "llvm/CodeGen/MachineInstrBuilder.h" 38 #include "llvm/CodeGen/MachineRegisterInfo.h" 39 #include "llvm/CodeGen/Passes.h" 40 #include "llvm/IR/InlineAsm.h" 41 #include "llvm/Support/Debug.h" 42 #include "llvm/Support/ErrorHandling.h" 43 #include "llvm/Support/raw_ostream.h" 44 #include "llvm/Target/TargetInstrInfo.h" 45 #include "llvm/Target/TargetMachine.h" 46 #include "llvm/Target/TargetSubtargetInfo.h" 47 #include <algorithm> 48 #include <bitset> 49 using namespace llvm; 50 51 #define DEBUG_TYPE "x86-codegen" 52 53 STATISTIC(NumFXCH, "Number of fxch instructions inserted"); 54 STATISTIC(NumFP , "Number of floating point instructions"); 55 56 namespace { 57 const unsigned ScratchFPReg = 7; 58 59 struct FPS : public MachineFunctionPass { 60 static char ID; 61 FPS() : MachineFunctionPass(ID) { 62 initializeEdgeBundlesPass(*PassRegistry::getPassRegistry()); 63 // This is really only to keep valgrind quiet. 64 // The logic in isLive() is too much for it. 65 memset(Stack, 0, sizeof(Stack)); 66 memset(RegMap, 0, sizeof(RegMap)); 67 } 68 69 void getAnalysisUsage(AnalysisUsage &AU) const override { 70 AU.setPreservesCFG(); 71 AU.addRequired<EdgeBundles>(); 72 AU.addPreservedID(MachineLoopInfoID); 73 AU.addPreservedID(MachineDominatorsID); 74 MachineFunctionPass::getAnalysisUsage(AU); 75 } 76 77 bool runOnMachineFunction(MachineFunction &MF) override; 78 79 MachineFunctionProperties getRequiredProperties() const override { 80 return MachineFunctionProperties().set( 81 MachineFunctionProperties::Property::AllVRegsAllocated); 82 } 83 84 const char *getPassName() const override { return "X86 FP Stackifier"; } 85 86 private: 87 const TargetInstrInfo *TII; // Machine instruction info. 88 89 // Two CFG edges are related if they leave the same block, or enter the same 90 // block. The transitive closure of an edge under this relation is a 91 // LiveBundle. It represents a set of CFG edges where the live FP stack 92 // registers must be allocated identically in the x87 stack. 93 // 94 // A LiveBundle is usually all the edges leaving a block, or all the edges 95 // entering a block, but it can contain more edges if critical edges are 96 // present. 97 // 98 // The set of live FP registers in a LiveBundle is calculated by bundleCFG, 99 // but the exact mapping of FP registers to stack slots is fixed later. 100 struct LiveBundle { 101 // Bit mask of live FP registers. Bit 0 = FP0, bit 1 = FP1, &c. 102 unsigned Mask; 103 104 // Number of pre-assigned live registers in FixStack. This is 0 when the 105 // stack order has not yet been fixed. 106 unsigned FixCount; 107 108 // Assigned stack order for live-in registers. 109 // FixStack[i] == getStackEntry(i) for all i < FixCount. 110 unsigned char FixStack[8]; 111 112 LiveBundle() : Mask(0), FixCount(0) {} 113 114 // Have the live registers been assigned a stack order yet? 115 bool isFixed() const { return !Mask || FixCount; } 116 }; 117 118 // Numbered LiveBundle structs. LiveBundles[0] is used for all CFG edges 119 // with no live FP registers. 120 SmallVector<LiveBundle, 8> LiveBundles; 121 122 // The edge bundle analysis provides indices into the LiveBundles vector. 123 EdgeBundles *Bundles; 124 125 // Return a bitmask of FP registers in block's live-in list. 126 static unsigned calcLiveInMask(MachineBasicBlock *MBB) { 127 unsigned Mask = 0; 128 for (const auto &LI : MBB->liveins()) { 129 if (LI.PhysReg < X86::FP0 || LI.PhysReg > X86::FP6) 130 continue; 131 Mask |= 1 << (LI.PhysReg - X86::FP0); 132 } 133 return Mask; 134 } 135 136 // Partition all the CFG edges into LiveBundles. 137 void bundleCFG(MachineFunction &MF); 138 139 MachineBasicBlock *MBB; // Current basic block 140 141 // The hardware keeps track of how many FP registers are live, so we have 142 // to model that exactly. Usually, each live register corresponds to an 143 // FP<n> register, but when dealing with calls, returns, and inline 144 // assembly, it is sometimes necessary to have live scratch registers. 145 unsigned Stack[8]; // FP<n> Registers in each stack slot... 146 unsigned StackTop; // The current top of the FP stack. 147 148 enum { 149 NumFPRegs = 8 // Including scratch pseudo-registers. 150 }; 151 152 // For each live FP<n> register, point to its Stack[] entry. 153 // The first entries correspond to FP0-FP6, the rest are scratch registers 154 // used when we need slightly different live registers than what the 155 // register allocator thinks. 156 unsigned RegMap[NumFPRegs]; 157 158 // Set up our stack model to match the incoming registers to MBB. 159 void setupBlockStack(); 160 161 // Shuffle live registers to match the expectations of successor blocks. 162 void finishBlockStack(); 163 164 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) 165 void dumpStack() const { 166 dbgs() << "Stack contents:"; 167 for (unsigned i = 0; i != StackTop; ++i) { 168 dbgs() << " FP" << Stack[i]; 169 assert(RegMap[Stack[i]] == i && "Stack[] doesn't match RegMap[]!"); 170 } 171 } 172 #endif 173 174 /// getSlot - Return the stack slot number a particular register number is 175 /// in. 176 unsigned getSlot(unsigned RegNo) const { 177 assert(RegNo < NumFPRegs && "Regno out of range!"); 178 return RegMap[RegNo]; 179 } 180 181 /// isLive - Is RegNo currently live in the stack? 182 bool isLive(unsigned RegNo) const { 183 unsigned Slot = getSlot(RegNo); 184 return Slot < StackTop && Stack[Slot] == RegNo; 185 } 186 187 /// getStackEntry - Return the X86::FP<n> register in register ST(i). 188 unsigned getStackEntry(unsigned STi) const { 189 if (STi >= StackTop) 190 report_fatal_error("Access past stack top!"); 191 return Stack[StackTop-1-STi]; 192 } 193 194 /// getSTReg - Return the X86::ST(i) register which contains the specified 195 /// FP<RegNo> register. 196 unsigned getSTReg(unsigned RegNo) const { 197 return StackTop - 1 - getSlot(RegNo) + X86::ST0; 198 } 199 200 // pushReg - Push the specified FP<n> register onto the stack. 201 void pushReg(unsigned Reg) { 202 assert(Reg < NumFPRegs && "Register number out of range!"); 203 if (StackTop >= 8) 204 report_fatal_error("Stack overflow!"); 205 Stack[StackTop] = Reg; 206 RegMap[Reg] = StackTop++; 207 } 208 209 bool isAtTop(unsigned RegNo) const { return getSlot(RegNo) == StackTop-1; } 210 void moveToTop(unsigned RegNo, MachineBasicBlock::iterator I) { 211 DebugLoc dl = I == MBB->end() ? DebugLoc() : I->getDebugLoc(); 212 if (isAtTop(RegNo)) return; 213 214 unsigned STReg = getSTReg(RegNo); 215 unsigned RegOnTop = getStackEntry(0); 216 217 // Swap the slots the regs are in. 218 std::swap(RegMap[RegNo], RegMap[RegOnTop]); 219 220 // Swap stack slot contents. 221 if (RegMap[RegOnTop] >= StackTop) 222 report_fatal_error("Access past stack top!"); 223 std::swap(Stack[RegMap[RegOnTop]], Stack[StackTop-1]); 224 225 // Emit an fxch to update the runtime processors version of the state. 226 BuildMI(*MBB, I, dl, TII->get(X86::XCH_F)).addReg(STReg); 227 ++NumFXCH; 228 } 229 230 void duplicateToTop(unsigned RegNo, unsigned AsReg, 231 MachineBasicBlock::iterator I) { 232 DebugLoc dl = I == MBB->end() ? DebugLoc() : I->getDebugLoc(); 233 unsigned STReg = getSTReg(RegNo); 234 pushReg(AsReg); // New register on top of stack 235 236 BuildMI(*MBB, I, dl, TII->get(X86::LD_Frr)).addReg(STReg); 237 } 238 239 /// popStackAfter - Pop the current value off of the top of the FP stack 240 /// after the specified instruction. 241 void popStackAfter(MachineBasicBlock::iterator &I); 242 243 /// freeStackSlotAfter - Free the specified register from the register 244 /// stack, so that it is no longer in a register. If the register is 245 /// currently at the top of the stack, we just pop the current instruction, 246 /// otherwise we store the current top-of-stack into the specified slot, 247 /// then pop the top of stack. 248 void freeStackSlotAfter(MachineBasicBlock::iterator &I, unsigned Reg); 249 250 /// freeStackSlotBefore - Just the pop, no folding. Return the inserted 251 /// instruction. 252 MachineBasicBlock::iterator 253 freeStackSlotBefore(MachineBasicBlock::iterator I, unsigned FPRegNo); 254 255 /// Adjust the live registers to be the set in Mask. 256 void adjustLiveRegs(unsigned Mask, MachineBasicBlock::iterator I); 257 258 /// Shuffle the top FixCount stack entries such that FP reg FixStack[0] is 259 /// st(0), FP reg FixStack[1] is st(1) etc. 260 void shuffleStackTop(const unsigned char *FixStack, unsigned FixCount, 261 MachineBasicBlock::iterator I); 262 263 bool processBasicBlock(MachineFunction &MF, MachineBasicBlock &MBB); 264 265 void handleCall(MachineBasicBlock::iterator &I); 266 void handleReturn(MachineBasicBlock::iterator &I); 267 void handleZeroArgFP(MachineBasicBlock::iterator &I); 268 void handleOneArgFP(MachineBasicBlock::iterator &I); 269 void handleOneArgFPRW(MachineBasicBlock::iterator &I); 270 void handleTwoArgFP(MachineBasicBlock::iterator &I); 271 void handleCompareFP(MachineBasicBlock::iterator &I); 272 void handleCondMovFP(MachineBasicBlock::iterator &I); 273 void handleSpecialFP(MachineBasicBlock::iterator &I); 274 275 // Check if a COPY instruction is using FP registers. 276 static bool isFPCopy(MachineInstr &MI) { 277 unsigned DstReg = MI.getOperand(0).getReg(); 278 unsigned SrcReg = MI.getOperand(1).getReg(); 279 280 return X86::RFP80RegClass.contains(DstReg) || 281 X86::RFP80RegClass.contains(SrcReg); 282 } 283 284 void setKillFlags(MachineBasicBlock &MBB) const; 285 }; 286 char FPS::ID = 0; 287 } 288 289 FunctionPass *llvm::createX86FloatingPointStackifierPass() { return new FPS(); } 290 291 /// getFPReg - Return the X86::FPx register number for the specified operand. 292 /// For example, this returns 3 for X86::FP3. 293 static unsigned getFPReg(const MachineOperand &MO) { 294 assert(MO.isReg() && "Expected an FP register!"); 295 unsigned Reg = MO.getReg(); 296 assert(Reg >= X86::FP0 && Reg <= X86::FP6 && "Expected FP register!"); 297 return Reg - X86::FP0; 298 } 299 300 /// runOnMachineFunction - Loop over all of the basic blocks, transforming FP 301 /// register references into FP stack references. 302 /// 303 bool FPS::runOnMachineFunction(MachineFunction &MF) { 304 // We only need to run this pass if there are any FP registers used in this 305 // function. If it is all integer, there is nothing for us to do! 306 bool FPIsUsed = false; 307 308 static_assert(X86::FP6 == X86::FP0+6, "Register enums aren't sorted right!"); 309 const MachineRegisterInfo &MRI = MF.getRegInfo(); 310 for (unsigned i = 0; i <= 6; ++i) 311 if (!MRI.reg_nodbg_empty(X86::FP0 + i)) { 312 FPIsUsed = true; 313 break; 314 } 315 316 // Early exit. 317 if (!FPIsUsed) return false; 318 319 Bundles = &getAnalysis<EdgeBundles>(); 320 TII = MF.getSubtarget().getInstrInfo(); 321 322 // Prepare cross-MBB liveness. 323 bundleCFG(MF); 324 325 StackTop = 0; 326 327 // Process the function in depth first order so that we process at least one 328 // of the predecessors for every reachable block in the function. 329 SmallPtrSet<MachineBasicBlock*, 8> Processed; 330 MachineBasicBlock *Entry = &MF.front(); 331 332 bool Changed = false; 333 for (MachineBasicBlock *BB : depth_first_ext(Entry, Processed)) 334 Changed |= processBasicBlock(MF, *BB); 335 336 // Process any unreachable blocks in arbitrary order now. 337 if (MF.size() != Processed.size()) 338 for (MachineBasicBlock &BB : MF) 339 if (Processed.insert(&BB).second) 340 Changed |= processBasicBlock(MF, BB); 341 342 LiveBundles.clear(); 343 344 return Changed; 345 } 346 347 /// bundleCFG - Scan all the basic blocks to determine consistent live-in and 348 /// live-out sets for the FP registers. Consistent means that the set of 349 /// registers live-out from a block is identical to the live-in set of all 350 /// successors. This is not enforced by the normal live-in lists since 351 /// registers may be implicitly defined, or not used by all successors. 352 void FPS::bundleCFG(MachineFunction &MF) { 353 assert(LiveBundles.empty() && "Stale data in LiveBundles"); 354 LiveBundles.resize(Bundles->getNumBundles()); 355 356 // Gather the actual live-in masks for all MBBs. 357 for (MachineBasicBlock &MBB : MF) { 358 const unsigned Mask = calcLiveInMask(&MBB); 359 if (!Mask) 360 continue; 361 // Update MBB ingoing bundle mask. 362 LiveBundles[Bundles->getBundle(MBB.getNumber(), false)].Mask |= Mask; 363 } 364 } 365 366 /// processBasicBlock - Loop over all of the instructions in the basic block, 367 /// transforming FP instructions into their stack form. 368 /// 369 bool FPS::processBasicBlock(MachineFunction &MF, MachineBasicBlock &BB) { 370 bool Changed = false; 371 MBB = &BB; 372 373 setKillFlags(BB); 374 setupBlockStack(); 375 376 for (MachineBasicBlock::iterator I = BB.begin(); I != BB.end(); ++I) { 377 MachineInstr &MI = *I; 378 uint64_t Flags = MI.getDesc().TSFlags; 379 380 unsigned FPInstClass = Flags & X86II::FPTypeMask; 381 if (MI.isInlineAsm()) 382 FPInstClass = X86II::SpecialFP; 383 384 if (MI.isCopy() && isFPCopy(MI)) 385 FPInstClass = X86II::SpecialFP; 386 387 if (MI.isImplicitDef() && 388 X86::RFP80RegClass.contains(MI.getOperand(0).getReg())) 389 FPInstClass = X86II::SpecialFP; 390 391 if (MI.isCall()) 392 FPInstClass = X86II::SpecialFP; 393 394 if (FPInstClass == X86II::NotFP) 395 continue; // Efficiently ignore non-fp insts! 396 397 MachineInstr *PrevMI = nullptr; 398 if (I != BB.begin()) 399 PrevMI = &*std::prev(I); 400 401 ++NumFP; // Keep track of # of pseudo instrs 402 DEBUG(dbgs() << "\nFPInst:\t" << MI); 403 404 // Get dead variables list now because the MI pointer may be deleted as part 405 // of processing! 406 SmallVector<unsigned, 8> DeadRegs; 407 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { 408 const MachineOperand &MO = MI.getOperand(i); 409 if (MO.isReg() && MO.isDead()) 410 DeadRegs.push_back(MO.getReg()); 411 } 412 413 switch (FPInstClass) { 414 case X86II::ZeroArgFP: handleZeroArgFP(I); break; 415 case X86II::OneArgFP: handleOneArgFP(I); break; // fstp ST(0) 416 case X86II::OneArgFPRW: handleOneArgFPRW(I); break; // ST(0) = fsqrt(ST(0)) 417 case X86II::TwoArgFP: handleTwoArgFP(I); break; 418 case X86II::CompareFP: handleCompareFP(I); break; 419 case X86II::CondMovFP: handleCondMovFP(I); break; 420 case X86II::SpecialFP: handleSpecialFP(I); break; 421 default: llvm_unreachable("Unknown FP Type!"); 422 } 423 424 // Check to see if any of the values defined by this instruction are dead 425 // after definition. If so, pop them. 426 for (unsigned i = 0, e = DeadRegs.size(); i != e; ++i) { 427 unsigned Reg = DeadRegs[i]; 428 // Check if Reg is live on the stack. An inline-asm register operand that 429 // is in the clobber list and marked dead might not be live on the stack. 430 if (Reg >= X86::FP0 && Reg <= X86::FP6 && isLive(Reg-X86::FP0)) { 431 DEBUG(dbgs() << "Register FP#" << Reg-X86::FP0 << " is dead!\n"); 432 freeStackSlotAfter(I, Reg-X86::FP0); 433 } 434 } 435 436 // Print out all of the instructions expanded to if -debug 437 DEBUG({ 438 MachineBasicBlock::iterator PrevI = PrevMI; 439 if (I == PrevI) { 440 dbgs() << "Just deleted pseudo instruction\n"; 441 } else { 442 MachineBasicBlock::iterator Start = I; 443 // Rewind to first instruction newly inserted. 444 while (Start != BB.begin() && std::prev(Start) != PrevI) 445 --Start; 446 dbgs() << "Inserted instructions:\n\t"; 447 Start->print(dbgs()); 448 while (++Start != std::next(I)) { 449 } 450 } 451 dumpStack(); 452 }); 453 (void)PrevMI; 454 455 Changed = true; 456 } 457 458 finishBlockStack(); 459 460 return Changed; 461 } 462 463 /// setupBlockStack - Use the live bundles to set up our model of the stack 464 /// to match predecessors' live out stack. 465 void FPS::setupBlockStack() { 466 DEBUG(dbgs() << "\nSetting up live-ins for BB#" << MBB->getNumber() 467 << " derived from " << MBB->getName() << ".\n"); 468 StackTop = 0; 469 // Get the live-in bundle for MBB. 470 const LiveBundle &Bundle = 471 LiveBundles[Bundles->getBundle(MBB->getNumber(), false)]; 472 473 if (!Bundle.Mask) { 474 DEBUG(dbgs() << "Block has no FP live-ins.\n"); 475 return; 476 } 477 478 // Depth-first iteration should ensure that we always have an assigned stack. 479 assert(Bundle.isFixed() && "Reached block before any predecessors"); 480 481 // Push the fixed live-in registers. 482 for (unsigned i = Bundle.FixCount; i > 0; --i) { 483 MBB->addLiveIn(X86::ST0+i-1); 484 DEBUG(dbgs() << "Live-in st(" << (i-1) << "): %FP" 485 << unsigned(Bundle.FixStack[i-1]) << '\n'); 486 pushReg(Bundle.FixStack[i-1]); 487 } 488 489 // Kill off unwanted live-ins. This can happen with a critical edge. 490 // FIXME: We could keep these live registers around as zombies. They may need 491 // to be revived at the end of a short block. It might save a few instrs. 492 adjustLiveRegs(calcLiveInMask(MBB), MBB->begin()); 493 DEBUG(MBB->dump()); 494 } 495 496 /// finishBlockStack - Revive live-outs that are implicitly defined out of 497 /// MBB. Shuffle live registers to match the expected fixed stack of any 498 /// predecessors, and ensure that all predecessors are expecting the same 499 /// stack. 500 void FPS::finishBlockStack() { 501 // The RET handling below takes care of return blocks for us. 502 if (MBB->succ_empty()) 503 return; 504 505 DEBUG(dbgs() << "Setting up live-outs for BB#" << MBB->getNumber() 506 << " derived from " << MBB->getName() << ".\n"); 507 508 // Get MBB's live-out bundle. 509 unsigned BundleIdx = Bundles->getBundle(MBB->getNumber(), true); 510 LiveBundle &Bundle = LiveBundles[BundleIdx]; 511 512 // We may need to kill and define some registers to match successors. 513 // FIXME: This can probably be combined with the shuffle below. 514 MachineBasicBlock::iterator Term = MBB->getFirstTerminator(); 515 adjustLiveRegs(Bundle.Mask, Term); 516 517 if (!Bundle.Mask) { 518 DEBUG(dbgs() << "No live-outs.\n"); 519 return; 520 } 521 522 // Has the stack order been fixed yet? 523 DEBUG(dbgs() << "LB#" << BundleIdx << ": "); 524 if (Bundle.isFixed()) { 525 DEBUG(dbgs() << "Shuffling stack to match.\n"); 526 shuffleStackTop(Bundle.FixStack, Bundle.FixCount, Term); 527 } else { 528 // Not fixed yet, we get to choose. 529 DEBUG(dbgs() << "Fixing stack order now.\n"); 530 Bundle.FixCount = StackTop; 531 for (unsigned i = 0; i < StackTop; ++i) 532 Bundle.FixStack[i] = getStackEntry(i); 533 } 534 } 535 536 537 //===----------------------------------------------------------------------===// 538 // Efficient Lookup Table Support 539 //===----------------------------------------------------------------------===// 540 541 namespace { 542 struct TableEntry { 543 uint16_t from; 544 uint16_t to; 545 bool operator<(const TableEntry &TE) const { return from < TE.from; } 546 friend bool operator<(const TableEntry &TE, unsigned V) { 547 return TE.from < V; 548 } 549 friend bool LLVM_ATTRIBUTE_UNUSED operator<(unsigned V, 550 const TableEntry &TE) { 551 return V < TE.from; 552 } 553 }; 554 } 555 556 static int Lookup(ArrayRef<TableEntry> Table, unsigned Opcode) { 557 const TableEntry *I = std::lower_bound(Table.begin(), Table.end(), Opcode); 558 if (I != Table.end() && I->from == Opcode) 559 return I->to; 560 return -1; 561 } 562 563 #ifdef NDEBUG 564 #define ASSERT_SORTED(TABLE) 565 #else 566 #define ASSERT_SORTED(TABLE) \ 567 { static bool TABLE##Checked = false; \ 568 if (!TABLE##Checked) { \ 569 assert(std::is_sorted(std::begin(TABLE), std::end(TABLE)) && \ 570 "All lookup tables must be sorted for efficient access!"); \ 571 TABLE##Checked = true; \ 572 } \ 573 } 574 #endif 575 576 //===----------------------------------------------------------------------===// 577 // Register File -> Register Stack Mapping Methods 578 //===----------------------------------------------------------------------===// 579 580 // OpcodeTable - Sorted map of register instructions to their stack version. 581 // The first element is an register file pseudo instruction, the second is the 582 // concrete X86 instruction which uses the register stack. 583 // 584 static const TableEntry OpcodeTable[] = { 585 { X86::ABS_Fp32 , X86::ABS_F }, 586 { X86::ABS_Fp64 , X86::ABS_F }, 587 { X86::ABS_Fp80 , X86::ABS_F }, 588 { X86::ADD_Fp32m , X86::ADD_F32m }, 589 { X86::ADD_Fp64m , X86::ADD_F64m }, 590 { X86::ADD_Fp64m32 , X86::ADD_F32m }, 591 { X86::ADD_Fp80m32 , X86::ADD_F32m }, 592 { X86::ADD_Fp80m64 , X86::ADD_F64m }, 593 { X86::ADD_FpI16m32 , X86::ADD_FI16m }, 594 { X86::ADD_FpI16m64 , X86::ADD_FI16m }, 595 { X86::ADD_FpI16m80 , X86::ADD_FI16m }, 596 { X86::ADD_FpI32m32 , X86::ADD_FI32m }, 597 { X86::ADD_FpI32m64 , X86::ADD_FI32m }, 598 { X86::ADD_FpI32m80 , X86::ADD_FI32m }, 599 { X86::CHS_Fp32 , X86::CHS_F }, 600 { X86::CHS_Fp64 , X86::CHS_F }, 601 { X86::CHS_Fp80 , X86::CHS_F }, 602 { X86::CMOVBE_Fp32 , X86::CMOVBE_F }, 603 { X86::CMOVBE_Fp64 , X86::CMOVBE_F }, 604 { X86::CMOVBE_Fp80 , X86::CMOVBE_F }, 605 { X86::CMOVB_Fp32 , X86::CMOVB_F }, 606 { X86::CMOVB_Fp64 , X86::CMOVB_F }, 607 { X86::CMOVB_Fp80 , X86::CMOVB_F }, 608 { X86::CMOVE_Fp32 , X86::CMOVE_F }, 609 { X86::CMOVE_Fp64 , X86::CMOVE_F }, 610 { X86::CMOVE_Fp80 , X86::CMOVE_F }, 611 { X86::CMOVNBE_Fp32 , X86::CMOVNBE_F }, 612 { X86::CMOVNBE_Fp64 , X86::CMOVNBE_F }, 613 { X86::CMOVNBE_Fp80 , X86::CMOVNBE_F }, 614 { X86::CMOVNB_Fp32 , X86::CMOVNB_F }, 615 { X86::CMOVNB_Fp64 , X86::CMOVNB_F }, 616 { X86::CMOVNB_Fp80 , X86::CMOVNB_F }, 617 { X86::CMOVNE_Fp32 , X86::CMOVNE_F }, 618 { X86::CMOVNE_Fp64 , X86::CMOVNE_F }, 619 { X86::CMOVNE_Fp80 , X86::CMOVNE_F }, 620 { X86::CMOVNP_Fp32 , X86::CMOVNP_F }, 621 { X86::CMOVNP_Fp64 , X86::CMOVNP_F }, 622 { X86::CMOVNP_Fp80 , X86::CMOVNP_F }, 623 { X86::CMOVP_Fp32 , X86::CMOVP_F }, 624 { X86::CMOVP_Fp64 , X86::CMOVP_F }, 625 { X86::CMOVP_Fp80 , X86::CMOVP_F }, 626 { X86::COS_Fp32 , X86::COS_F }, 627 { X86::COS_Fp64 , X86::COS_F }, 628 { X86::COS_Fp80 , X86::COS_F }, 629 { X86::DIVR_Fp32m , X86::DIVR_F32m }, 630 { X86::DIVR_Fp64m , X86::DIVR_F64m }, 631 { X86::DIVR_Fp64m32 , X86::DIVR_F32m }, 632 { X86::DIVR_Fp80m32 , X86::DIVR_F32m }, 633 { X86::DIVR_Fp80m64 , X86::DIVR_F64m }, 634 { X86::DIVR_FpI16m32, X86::DIVR_FI16m}, 635 { X86::DIVR_FpI16m64, X86::DIVR_FI16m}, 636 { X86::DIVR_FpI16m80, X86::DIVR_FI16m}, 637 { X86::DIVR_FpI32m32, X86::DIVR_FI32m}, 638 { X86::DIVR_FpI32m64, X86::DIVR_FI32m}, 639 { X86::DIVR_FpI32m80, X86::DIVR_FI32m}, 640 { X86::DIV_Fp32m , X86::DIV_F32m }, 641 { X86::DIV_Fp64m , X86::DIV_F64m }, 642 { X86::DIV_Fp64m32 , X86::DIV_F32m }, 643 { X86::DIV_Fp80m32 , X86::DIV_F32m }, 644 { X86::DIV_Fp80m64 , X86::DIV_F64m }, 645 { X86::DIV_FpI16m32 , X86::DIV_FI16m }, 646 { X86::DIV_FpI16m64 , X86::DIV_FI16m }, 647 { X86::DIV_FpI16m80 , X86::DIV_FI16m }, 648 { X86::DIV_FpI32m32 , X86::DIV_FI32m }, 649 { X86::DIV_FpI32m64 , X86::DIV_FI32m }, 650 { X86::DIV_FpI32m80 , X86::DIV_FI32m }, 651 { X86::ILD_Fp16m32 , X86::ILD_F16m }, 652 { X86::ILD_Fp16m64 , X86::ILD_F16m }, 653 { X86::ILD_Fp16m80 , X86::ILD_F16m }, 654 { X86::ILD_Fp32m32 , X86::ILD_F32m }, 655 { X86::ILD_Fp32m64 , X86::ILD_F32m }, 656 { X86::ILD_Fp32m80 , X86::ILD_F32m }, 657 { X86::ILD_Fp64m32 , X86::ILD_F64m }, 658 { X86::ILD_Fp64m64 , X86::ILD_F64m }, 659 { X86::ILD_Fp64m80 , X86::ILD_F64m }, 660 { X86::ISTT_Fp16m32 , X86::ISTT_FP16m}, 661 { X86::ISTT_Fp16m64 , X86::ISTT_FP16m}, 662 { X86::ISTT_Fp16m80 , X86::ISTT_FP16m}, 663 { X86::ISTT_Fp32m32 , X86::ISTT_FP32m}, 664 { X86::ISTT_Fp32m64 , X86::ISTT_FP32m}, 665 { X86::ISTT_Fp32m80 , X86::ISTT_FP32m}, 666 { X86::ISTT_Fp64m32 , X86::ISTT_FP64m}, 667 { X86::ISTT_Fp64m64 , X86::ISTT_FP64m}, 668 { X86::ISTT_Fp64m80 , X86::ISTT_FP64m}, 669 { X86::IST_Fp16m32 , X86::IST_F16m }, 670 { X86::IST_Fp16m64 , X86::IST_F16m }, 671 { X86::IST_Fp16m80 , X86::IST_F16m }, 672 { X86::IST_Fp32m32 , X86::IST_F32m }, 673 { X86::IST_Fp32m64 , X86::IST_F32m }, 674 { X86::IST_Fp32m80 , X86::IST_F32m }, 675 { X86::IST_Fp64m32 , X86::IST_FP64m }, 676 { X86::IST_Fp64m64 , X86::IST_FP64m }, 677 { X86::IST_Fp64m80 , X86::IST_FP64m }, 678 { X86::LD_Fp032 , X86::LD_F0 }, 679 { X86::LD_Fp064 , X86::LD_F0 }, 680 { X86::LD_Fp080 , X86::LD_F0 }, 681 { X86::LD_Fp132 , X86::LD_F1 }, 682 { X86::LD_Fp164 , X86::LD_F1 }, 683 { X86::LD_Fp180 , X86::LD_F1 }, 684 { X86::LD_Fp32m , X86::LD_F32m }, 685 { X86::LD_Fp32m64 , X86::LD_F32m }, 686 { X86::LD_Fp32m80 , X86::LD_F32m }, 687 { X86::LD_Fp64m , X86::LD_F64m }, 688 { X86::LD_Fp64m80 , X86::LD_F64m }, 689 { X86::LD_Fp80m , X86::LD_F80m }, 690 { X86::MUL_Fp32m , X86::MUL_F32m }, 691 { X86::MUL_Fp64m , X86::MUL_F64m }, 692 { X86::MUL_Fp64m32 , X86::MUL_F32m }, 693 { X86::MUL_Fp80m32 , X86::MUL_F32m }, 694 { X86::MUL_Fp80m64 , X86::MUL_F64m }, 695 { X86::MUL_FpI16m32 , X86::MUL_FI16m }, 696 { X86::MUL_FpI16m64 , X86::MUL_FI16m }, 697 { X86::MUL_FpI16m80 , X86::MUL_FI16m }, 698 { X86::MUL_FpI32m32 , X86::MUL_FI32m }, 699 { X86::MUL_FpI32m64 , X86::MUL_FI32m }, 700 { X86::MUL_FpI32m80 , X86::MUL_FI32m }, 701 { X86::SIN_Fp32 , X86::SIN_F }, 702 { X86::SIN_Fp64 , X86::SIN_F }, 703 { X86::SIN_Fp80 , X86::SIN_F }, 704 { X86::SQRT_Fp32 , X86::SQRT_F }, 705 { X86::SQRT_Fp64 , X86::SQRT_F }, 706 { X86::SQRT_Fp80 , X86::SQRT_F }, 707 { X86::ST_Fp32m , X86::ST_F32m }, 708 { X86::ST_Fp64m , X86::ST_F64m }, 709 { X86::ST_Fp64m32 , X86::ST_F32m }, 710 { X86::ST_Fp80m32 , X86::ST_F32m }, 711 { X86::ST_Fp80m64 , X86::ST_F64m }, 712 { X86::ST_FpP80m , X86::ST_FP80m }, 713 { X86::SUBR_Fp32m , X86::SUBR_F32m }, 714 { X86::SUBR_Fp64m , X86::SUBR_F64m }, 715 { X86::SUBR_Fp64m32 , X86::SUBR_F32m }, 716 { X86::SUBR_Fp80m32 , X86::SUBR_F32m }, 717 { X86::SUBR_Fp80m64 , X86::SUBR_F64m }, 718 { X86::SUBR_FpI16m32, X86::SUBR_FI16m}, 719 { X86::SUBR_FpI16m64, X86::SUBR_FI16m}, 720 { X86::SUBR_FpI16m80, X86::SUBR_FI16m}, 721 { X86::SUBR_FpI32m32, X86::SUBR_FI32m}, 722 { X86::SUBR_FpI32m64, X86::SUBR_FI32m}, 723 { X86::SUBR_FpI32m80, X86::SUBR_FI32m}, 724 { X86::SUB_Fp32m , X86::SUB_F32m }, 725 { X86::SUB_Fp64m , X86::SUB_F64m }, 726 { X86::SUB_Fp64m32 , X86::SUB_F32m }, 727 { X86::SUB_Fp80m32 , X86::SUB_F32m }, 728 { X86::SUB_Fp80m64 , X86::SUB_F64m }, 729 { X86::SUB_FpI16m32 , X86::SUB_FI16m }, 730 { X86::SUB_FpI16m64 , X86::SUB_FI16m }, 731 { X86::SUB_FpI16m80 , X86::SUB_FI16m }, 732 { X86::SUB_FpI32m32 , X86::SUB_FI32m }, 733 { X86::SUB_FpI32m64 , X86::SUB_FI32m }, 734 { X86::SUB_FpI32m80 , X86::SUB_FI32m }, 735 { X86::TST_Fp32 , X86::TST_F }, 736 { X86::TST_Fp64 , X86::TST_F }, 737 { X86::TST_Fp80 , X86::TST_F }, 738 { X86::UCOM_FpIr32 , X86::UCOM_FIr }, 739 { X86::UCOM_FpIr64 , X86::UCOM_FIr }, 740 { X86::UCOM_FpIr80 , X86::UCOM_FIr }, 741 { X86::UCOM_Fpr32 , X86::UCOM_Fr }, 742 { X86::UCOM_Fpr64 , X86::UCOM_Fr }, 743 { X86::UCOM_Fpr80 , X86::UCOM_Fr }, 744 }; 745 746 static unsigned getConcreteOpcode(unsigned Opcode) { 747 ASSERT_SORTED(OpcodeTable); 748 int Opc = Lookup(OpcodeTable, Opcode); 749 assert(Opc != -1 && "FP Stack instruction not in OpcodeTable!"); 750 return Opc; 751 } 752 753 //===----------------------------------------------------------------------===// 754 // Helper Methods 755 //===----------------------------------------------------------------------===// 756 757 // PopTable - Sorted map of instructions to their popping version. The first 758 // element is an instruction, the second is the version which pops. 759 // 760 static const TableEntry PopTable[] = { 761 { X86::ADD_FrST0 , X86::ADD_FPrST0 }, 762 763 { X86::DIVR_FrST0, X86::DIVR_FPrST0 }, 764 { X86::DIV_FrST0 , X86::DIV_FPrST0 }, 765 766 { X86::IST_F16m , X86::IST_FP16m }, 767 { X86::IST_F32m , X86::IST_FP32m }, 768 769 { X86::MUL_FrST0 , X86::MUL_FPrST0 }, 770 771 { X86::ST_F32m , X86::ST_FP32m }, 772 { X86::ST_F64m , X86::ST_FP64m }, 773 { X86::ST_Frr , X86::ST_FPrr }, 774 775 { X86::SUBR_FrST0, X86::SUBR_FPrST0 }, 776 { X86::SUB_FrST0 , X86::SUB_FPrST0 }, 777 778 { X86::UCOM_FIr , X86::UCOM_FIPr }, 779 780 { X86::UCOM_FPr , X86::UCOM_FPPr }, 781 { X86::UCOM_Fr , X86::UCOM_FPr }, 782 }; 783 784 /// popStackAfter - Pop the current value off of the top of the FP stack after 785 /// the specified instruction. This attempts to be sneaky and combine the pop 786 /// into the instruction itself if possible. The iterator is left pointing to 787 /// the last instruction, be it a new pop instruction inserted, or the old 788 /// instruction if it was modified in place. 789 /// 790 void FPS::popStackAfter(MachineBasicBlock::iterator &I) { 791 MachineInstr &MI = *I; 792 const DebugLoc &dl = MI.getDebugLoc(); 793 ASSERT_SORTED(PopTable); 794 if (StackTop == 0) 795 report_fatal_error("Cannot pop empty stack!"); 796 RegMap[Stack[--StackTop]] = ~0; // Update state 797 798 // Check to see if there is a popping version of this instruction... 799 int Opcode = Lookup(PopTable, I->getOpcode()); 800 if (Opcode != -1) { 801 I->setDesc(TII->get(Opcode)); 802 if (Opcode == X86::UCOM_FPPr) 803 I->RemoveOperand(0); 804 } else { // Insert an explicit pop 805 I = BuildMI(*MBB, ++I, dl, TII->get(X86::ST_FPrr)).addReg(X86::ST0); 806 } 807 } 808 809 /// freeStackSlotAfter - Free the specified register from the register stack, so 810 /// that it is no longer in a register. If the register is currently at the top 811 /// of the stack, we just pop the current instruction, otherwise we store the 812 /// current top-of-stack into the specified slot, then pop the top of stack. 813 void FPS::freeStackSlotAfter(MachineBasicBlock::iterator &I, unsigned FPRegNo) { 814 if (getStackEntry(0) == FPRegNo) { // already at the top of stack? easy. 815 popStackAfter(I); 816 return; 817 } 818 819 // Otherwise, store the top of stack into the dead slot, killing the operand 820 // without having to add in an explicit xchg then pop. 821 // 822 I = freeStackSlotBefore(++I, FPRegNo); 823 } 824 825 /// freeStackSlotBefore - Free the specified register without trying any 826 /// folding. 827 MachineBasicBlock::iterator 828 FPS::freeStackSlotBefore(MachineBasicBlock::iterator I, unsigned FPRegNo) { 829 unsigned STReg = getSTReg(FPRegNo); 830 unsigned OldSlot = getSlot(FPRegNo); 831 unsigned TopReg = Stack[StackTop-1]; 832 Stack[OldSlot] = TopReg; 833 RegMap[TopReg] = OldSlot; 834 RegMap[FPRegNo] = ~0; 835 Stack[--StackTop] = ~0; 836 return BuildMI(*MBB, I, DebugLoc(), TII->get(X86::ST_FPrr)) 837 .addReg(STReg) 838 .getInstr(); 839 } 840 841 /// adjustLiveRegs - Kill and revive registers such that exactly the FP 842 /// registers with a bit in Mask are live. 843 void FPS::adjustLiveRegs(unsigned Mask, MachineBasicBlock::iterator I) { 844 unsigned Defs = Mask; 845 unsigned Kills = 0; 846 for (unsigned i = 0; i < StackTop; ++i) { 847 unsigned RegNo = Stack[i]; 848 if (!(Defs & (1 << RegNo))) 849 // This register is live, but we don't want it. 850 Kills |= (1 << RegNo); 851 else 852 // We don't need to imp-def this live register. 853 Defs &= ~(1 << RegNo); 854 } 855 assert((Kills & Defs) == 0 && "Register needs killing and def'ing?"); 856 857 // Produce implicit-defs for free by using killed registers. 858 while (Kills && Defs) { 859 unsigned KReg = countTrailingZeros(Kills); 860 unsigned DReg = countTrailingZeros(Defs); 861 DEBUG(dbgs() << "Renaming %FP" << KReg << " as imp %FP" << DReg << "\n"); 862 std::swap(Stack[getSlot(KReg)], Stack[getSlot(DReg)]); 863 std::swap(RegMap[KReg], RegMap[DReg]); 864 Kills &= ~(1 << KReg); 865 Defs &= ~(1 << DReg); 866 } 867 868 // Kill registers by popping. 869 if (Kills && I != MBB->begin()) { 870 MachineBasicBlock::iterator I2 = std::prev(I); 871 while (StackTop) { 872 unsigned KReg = getStackEntry(0); 873 if (!(Kills & (1 << KReg))) 874 break; 875 DEBUG(dbgs() << "Popping %FP" << KReg << "\n"); 876 popStackAfter(I2); 877 Kills &= ~(1 << KReg); 878 } 879 } 880 881 // Manually kill the rest. 882 while (Kills) { 883 unsigned KReg = countTrailingZeros(Kills); 884 DEBUG(dbgs() << "Killing %FP" << KReg << "\n"); 885 freeStackSlotBefore(I, KReg); 886 Kills &= ~(1 << KReg); 887 } 888 889 // Load zeros for all the imp-defs. 890 while(Defs) { 891 unsigned DReg = countTrailingZeros(Defs); 892 DEBUG(dbgs() << "Defining %FP" << DReg << " as 0\n"); 893 BuildMI(*MBB, I, DebugLoc(), TII->get(X86::LD_F0)); 894 pushReg(DReg); 895 Defs &= ~(1 << DReg); 896 } 897 898 // Now we should have the correct registers live. 899 DEBUG(dumpStack()); 900 assert(StackTop == countPopulation(Mask) && "Live count mismatch"); 901 } 902 903 /// shuffleStackTop - emit fxch instructions before I to shuffle the top 904 /// FixCount entries into the order given by FixStack. 905 /// FIXME: Is there a better algorithm than insertion sort? 906 void FPS::shuffleStackTop(const unsigned char *FixStack, 907 unsigned FixCount, 908 MachineBasicBlock::iterator I) { 909 // Move items into place, starting from the desired stack bottom. 910 while (FixCount--) { 911 // Old register at position FixCount. 912 unsigned OldReg = getStackEntry(FixCount); 913 // Desired register at position FixCount. 914 unsigned Reg = FixStack[FixCount]; 915 if (Reg == OldReg) 916 continue; 917 // (Reg st0) (OldReg st0) = (Reg OldReg st0) 918 moveToTop(Reg, I); 919 if (FixCount > 0) 920 moveToTop(OldReg, I); 921 } 922 DEBUG(dumpStack()); 923 } 924 925 926 //===----------------------------------------------------------------------===// 927 // Instruction transformation implementation 928 //===----------------------------------------------------------------------===// 929 930 void FPS::handleCall(MachineBasicBlock::iterator &I) { 931 unsigned STReturns = 0; 932 933 for (const auto &MO : I->operands()) { 934 if (!MO.isReg()) 935 continue; 936 937 unsigned R = MO.getReg() - X86::FP0; 938 939 if (R < 8) { 940 assert(MO.isDef() && MO.isImplicit()); 941 STReturns |= 1 << R; 942 } 943 } 944 945 unsigned N = countTrailingOnes(STReturns); 946 947 // FP registers used for function return must be consecutive starting at 948 // FP0. 949 assert(STReturns == 0 || (isMask_32(STReturns) && N <= 2)); 950 951 for (unsigned I = 0; I < N; ++I) 952 pushReg(N - I - 1); 953 } 954 955 /// If RET has an FP register use operand, pass the first one in ST(0) and 956 /// the second one in ST(1). 957 void FPS::handleReturn(MachineBasicBlock::iterator &I) { 958 MachineInstr &MI = *I; 959 960 // Find the register operands. 961 unsigned FirstFPRegOp = ~0U, SecondFPRegOp = ~0U; 962 unsigned LiveMask = 0; 963 964 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { 965 MachineOperand &Op = MI.getOperand(i); 966 if (!Op.isReg() || Op.getReg() < X86::FP0 || Op.getReg() > X86::FP6) 967 continue; 968 // FP Register uses must be kills unless there are two uses of the same 969 // register, in which case only one will be a kill. 970 assert(Op.isUse() && 971 (Op.isKill() || // Marked kill. 972 getFPReg(Op) == FirstFPRegOp || // Second instance. 973 MI.killsRegister(Op.getReg())) && // Later use is marked kill. 974 "Ret only defs operands, and values aren't live beyond it"); 975 976 if (FirstFPRegOp == ~0U) 977 FirstFPRegOp = getFPReg(Op); 978 else { 979 assert(SecondFPRegOp == ~0U && "More than two fp operands!"); 980 SecondFPRegOp = getFPReg(Op); 981 } 982 LiveMask |= (1 << getFPReg(Op)); 983 984 // Remove the operand so that later passes don't see it. 985 MI.RemoveOperand(i); 986 --i; 987 --e; 988 } 989 990 // We may have been carrying spurious live-ins, so make sure only the 991 // returned registers are left live. 992 adjustLiveRegs(LiveMask, MI); 993 if (!LiveMask) return; // Quick check to see if any are possible. 994 995 // There are only four possibilities here: 996 // 1) we are returning a single FP value. In this case, it has to be in 997 // ST(0) already, so just declare success by removing the value from the 998 // FP Stack. 999 if (SecondFPRegOp == ~0U) { 1000 // Assert that the top of stack contains the right FP register. 1001 assert(StackTop == 1 && FirstFPRegOp == getStackEntry(0) && 1002 "Top of stack not the right register for RET!"); 1003 1004 // Ok, everything is good, mark the value as not being on the stack 1005 // anymore so that our assertion about the stack being empty at end of 1006 // block doesn't fire. 1007 StackTop = 0; 1008 return; 1009 } 1010 1011 // Otherwise, we are returning two values: 1012 // 2) If returning the same value for both, we only have one thing in the FP 1013 // stack. Consider: RET FP1, FP1 1014 if (StackTop == 1) { 1015 assert(FirstFPRegOp == SecondFPRegOp && FirstFPRegOp == getStackEntry(0)&& 1016 "Stack misconfiguration for RET!"); 1017 1018 // Duplicate the TOS so that we return it twice. Just pick some other FPx 1019 // register to hold it. 1020 unsigned NewReg = ScratchFPReg; 1021 duplicateToTop(FirstFPRegOp, NewReg, MI); 1022 FirstFPRegOp = NewReg; 1023 } 1024 1025 /// Okay we know we have two different FPx operands now: 1026 assert(StackTop == 2 && "Must have two values live!"); 1027 1028 /// 3) If SecondFPRegOp is currently in ST(0) and FirstFPRegOp is currently 1029 /// in ST(1). In this case, emit an fxch. 1030 if (getStackEntry(0) == SecondFPRegOp) { 1031 assert(getStackEntry(1) == FirstFPRegOp && "Unknown regs live"); 1032 moveToTop(FirstFPRegOp, MI); 1033 } 1034 1035 /// 4) Finally, FirstFPRegOp must be in ST(0) and SecondFPRegOp must be in 1036 /// ST(1). Just remove both from our understanding of the stack and return. 1037 assert(getStackEntry(0) == FirstFPRegOp && "Unknown regs live"); 1038 assert(getStackEntry(1) == SecondFPRegOp && "Unknown regs live"); 1039 StackTop = 0; 1040 } 1041 1042 /// handleZeroArgFP - ST(0) = fld0 ST(0) = flds <mem> 1043 /// 1044 void FPS::handleZeroArgFP(MachineBasicBlock::iterator &I) { 1045 MachineInstr &MI = *I; 1046 unsigned DestReg = getFPReg(MI.getOperand(0)); 1047 1048 // Change from the pseudo instruction to the concrete instruction. 1049 MI.RemoveOperand(0); // Remove the explicit ST(0) operand 1050 MI.setDesc(TII->get(getConcreteOpcode(MI.getOpcode()))); 1051 1052 // Result gets pushed on the stack. 1053 pushReg(DestReg); 1054 } 1055 1056 /// handleOneArgFP - fst <mem>, ST(0) 1057 /// 1058 void FPS::handleOneArgFP(MachineBasicBlock::iterator &I) { 1059 MachineInstr &MI = *I; 1060 unsigned NumOps = MI.getDesc().getNumOperands(); 1061 assert((NumOps == X86::AddrNumOperands + 1 || NumOps == 1) && 1062 "Can only handle fst* & ftst instructions!"); 1063 1064 // Is this the last use of the source register? 1065 unsigned Reg = getFPReg(MI.getOperand(NumOps - 1)); 1066 bool KillsSrc = MI.killsRegister(X86::FP0 + Reg); 1067 1068 // FISTP64m is strange because there isn't a non-popping versions. 1069 // If we have one _and_ we don't want to pop the operand, duplicate the value 1070 // on the stack instead of moving it. This ensure that popping the value is 1071 // always ok. 1072 // Ditto FISTTP16m, FISTTP32m, FISTTP64m, ST_FpP80m. 1073 // 1074 if (!KillsSrc && (MI.getOpcode() == X86::IST_Fp64m32 || 1075 MI.getOpcode() == X86::ISTT_Fp16m32 || 1076 MI.getOpcode() == X86::ISTT_Fp32m32 || 1077 MI.getOpcode() == X86::ISTT_Fp64m32 || 1078 MI.getOpcode() == X86::IST_Fp64m64 || 1079 MI.getOpcode() == X86::ISTT_Fp16m64 || 1080 MI.getOpcode() == X86::ISTT_Fp32m64 || 1081 MI.getOpcode() == X86::ISTT_Fp64m64 || 1082 MI.getOpcode() == X86::IST_Fp64m80 || 1083 MI.getOpcode() == X86::ISTT_Fp16m80 || 1084 MI.getOpcode() == X86::ISTT_Fp32m80 || 1085 MI.getOpcode() == X86::ISTT_Fp64m80 || 1086 MI.getOpcode() == X86::ST_FpP80m)) { 1087 duplicateToTop(Reg, ScratchFPReg, I); 1088 } else { 1089 moveToTop(Reg, I); // Move to the top of the stack... 1090 } 1091 1092 // Convert from the pseudo instruction to the concrete instruction. 1093 MI.RemoveOperand(NumOps - 1); // Remove explicit ST(0) operand 1094 MI.setDesc(TII->get(getConcreteOpcode(MI.getOpcode()))); 1095 1096 if (MI.getOpcode() == X86::IST_FP64m || MI.getOpcode() == X86::ISTT_FP16m || 1097 MI.getOpcode() == X86::ISTT_FP32m || MI.getOpcode() == X86::ISTT_FP64m || 1098 MI.getOpcode() == X86::ST_FP80m) { 1099 if (StackTop == 0) 1100 report_fatal_error("Stack empty??"); 1101 --StackTop; 1102 } else if (KillsSrc) { // Last use of operand? 1103 popStackAfter(I); 1104 } 1105 } 1106 1107 1108 /// handleOneArgFPRW: Handle instructions that read from the top of stack and 1109 /// replace the value with a newly computed value. These instructions may have 1110 /// non-fp operands after their FP operands. 1111 /// 1112 /// Examples: 1113 /// R1 = fchs R2 1114 /// R1 = fadd R2, [mem] 1115 /// 1116 void FPS::handleOneArgFPRW(MachineBasicBlock::iterator &I) { 1117 MachineInstr &MI = *I; 1118 #ifndef NDEBUG 1119 unsigned NumOps = MI.getDesc().getNumOperands(); 1120 assert(NumOps >= 2 && "FPRW instructions must have 2 ops!!"); 1121 #endif 1122 1123 // Is this the last use of the source register? 1124 unsigned Reg = getFPReg(MI.getOperand(1)); 1125 bool KillsSrc = MI.killsRegister(X86::FP0 + Reg); 1126 1127 if (KillsSrc) { 1128 // If this is the last use of the source register, just make sure it's on 1129 // the top of the stack. 1130 moveToTop(Reg, I); 1131 if (StackTop == 0) 1132 report_fatal_error("Stack cannot be empty!"); 1133 --StackTop; 1134 pushReg(getFPReg(MI.getOperand(0))); 1135 } else { 1136 // If this is not the last use of the source register, _copy_ it to the top 1137 // of the stack. 1138 duplicateToTop(Reg, getFPReg(MI.getOperand(0)), I); 1139 } 1140 1141 // Change from the pseudo instruction to the concrete instruction. 1142 MI.RemoveOperand(1); // Drop the source operand. 1143 MI.RemoveOperand(0); // Drop the destination operand. 1144 MI.setDesc(TII->get(getConcreteOpcode(MI.getOpcode()))); 1145 } 1146 1147 1148 //===----------------------------------------------------------------------===// 1149 // Define tables of various ways to map pseudo instructions 1150 // 1151 1152 // ForwardST0Table - Map: A = B op C into: ST(0) = ST(0) op ST(i) 1153 static const TableEntry ForwardST0Table[] = { 1154 { X86::ADD_Fp32 , X86::ADD_FST0r }, 1155 { X86::ADD_Fp64 , X86::ADD_FST0r }, 1156 { X86::ADD_Fp80 , X86::ADD_FST0r }, 1157 { X86::DIV_Fp32 , X86::DIV_FST0r }, 1158 { X86::DIV_Fp64 , X86::DIV_FST0r }, 1159 { X86::DIV_Fp80 , X86::DIV_FST0r }, 1160 { X86::MUL_Fp32 , X86::MUL_FST0r }, 1161 { X86::MUL_Fp64 , X86::MUL_FST0r }, 1162 { X86::MUL_Fp80 , X86::MUL_FST0r }, 1163 { X86::SUB_Fp32 , X86::SUB_FST0r }, 1164 { X86::SUB_Fp64 , X86::SUB_FST0r }, 1165 { X86::SUB_Fp80 , X86::SUB_FST0r }, 1166 }; 1167 1168 // ReverseST0Table - Map: A = B op C into: ST(0) = ST(i) op ST(0) 1169 static const TableEntry ReverseST0Table[] = { 1170 { X86::ADD_Fp32 , X86::ADD_FST0r }, // commutative 1171 { X86::ADD_Fp64 , X86::ADD_FST0r }, // commutative 1172 { X86::ADD_Fp80 , X86::ADD_FST0r }, // commutative 1173 { X86::DIV_Fp32 , X86::DIVR_FST0r }, 1174 { X86::DIV_Fp64 , X86::DIVR_FST0r }, 1175 { X86::DIV_Fp80 , X86::DIVR_FST0r }, 1176 { X86::MUL_Fp32 , X86::MUL_FST0r }, // commutative 1177 { X86::MUL_Fp64 , X86::MUL_FST0r }, // commutative 1178 { X86::MUL_Fp80 , X86::MUL_FST0r }, // commutative 1179 { X86::SUB_Fp32 , X86::SUBR_FST0r }, 1180 { X86::SUB_Fp64 , X86::SUBR_FST0r }, 1181 { X86::SUB_Fp80 , X86::SUBR_FST0r }, 1182 }; 1183 1184 // ForwardSTiTable - Map: A = B op C into: ST(i) = ST(0) op ST(i) 1185 static const TableEntry ForwardSTiTable[] = { 1186 { X86::ADD_Fp32 , X86::ADD_FrST0 }, // commutative 1187 { X86::ADD_Fp64 , X86::ADD_FrST0 }, // commutative 1188 { X86::ADD_Fp80 , X86::ADD_FrST0 }, // commutative 1189 { X86::DIV_Fp32 , X86::DIVR_FrST0 }, 1190 { X86::DIV_Fp64 , X86::DIVR_FrST0 }, 1191 { X86::DIV_Fp80 , X86::DIVR_FrST0 }, 1192 { X86::MUL_Fp32 , X86::MUL_FrST0 }, // commutative 1193 { X86::MUL_Fp64 , X86::MUL_FrST0 }, // commutative 1194 { X86::MUL_Fp80 , X86::MUL_FrST0 }, // commutative 1195 { X86::SUB_Fp32 , X86::SUBR_FrST0 }, 1196 { X86::SUB_Fp64 , X86::SUBR_FrST0 }, 1197 { X86::SUB_Fp80 , X86::SUBR_FrST0 }, 1198 }; 1199 1200 // ReverseSTiTable - Map: A = B op C into: ST(i) = ST(i) op ST(0) 1201 static const TableEntry ReverseSTiTable[] = { 1202 { X86::ADD_Fp32 , X86::ADD_FrST0 }, 1203 { X86::ADD_Fp64 , X86::ADD_FrST0 }, 1204 { X86::ADD_Fp80 , X86::ADD_FrST0 }, 1205 { X86::DIV_Fp32 , X86::DIV_FrST0 }, 1206 { X86::DIV_Fp64 , X86::DIV_FrST0 }, 1207 { X86::DIV_Fp80 , X86::DIV_FrST0 }, 1208 { X86::MUL_Fp32 , X86::MUL_FrST0 }, 1209 { X86::MUL_Fp64 , X86::MUL_FrST0 }, 1210 { X86::MUL_Fp80 , X86::MUL_FrST0 }, 1211 { X86::SUB_Fp32 , X86::SUB_FrST0 }, 1212 { X86::SUB_Fp64 , X86::SUB_FrST0 }, 1213 { X86::SUB_Fp80 , X86::SUB_FrST0 }, 1214 }; 1215 1216 1217 /// handleTwoArgFP - Handle instructions like FADD and friends which are virtual 1218 /// instructions which need to be simplified and possibly transformed. 1219 /// 1220 /// Result: ST(0) = fsub ST(0), ST(i) 1221 /// ST(i) = fsub ST(0), ST(i) 1222 /// ST(0) = fsubr ST(0), ST(i) 1223 /// ST(i) = fsubr ST(0), ST(i) 1224 /// 1225 void FPS::handleTwoArgFP(MachineBasicBlock::iterator &I) { 1226 ASSERT_SORTED(ForwardST0Table); ASSERT_SORTED(ReverseST0Table); 1227 ASSERT_SORTED(ForwardSTiTable); ASSERT_SORTED(ReverseSTiTable); 1228 MachineInstr &MI = *I; 1229 1230 unsigned NumOperands = MI.getDesc().getNumOperands(); 1231 assert(NumOperands == 3 && "Illegal TwoArgFP instruction!"); 1232 unsigned Dest = getFPReg(MI.getOperand(0)); 1233 unsigned Op0 = getFPReg(MI.getOperand(NumOperands - 2)); 1234 unsigned Op1 = getFPReg(MI.getOperand(NumOperands - 1)); 1235 bool KillsOp0 = MI.killsRegister(X86::FP0 + Op0); 1236 bool KillsOp1 = MI.killsRegister(X86::FP0 + Op1); 1237 DebugLoc dl = MI.getDebugLoc(); 1238 1239 unsigned TOS = getStackEntry(0); 1240 1241 // One of our operands must be on the top of the stack. If neither is yet, we 1242 // need to move one. 1243 if (Op0 != TOS && Op1 != TOS) { // No operand at TOS? 1244 // We can choose to move either operand to the top of the stack. If one of 1245 // the operands is killed by this instruction, we want that one so that we 1246 // can update right on top of the old version. 1247 if (KillsOp0) { 1248 moveToTop(Op0, I); // Move dead operand to TOS. 1249 TOS = Op0; 1250 } else if (KillsOp1) { 1251 moveToTop(Op1, I); 1252 TOS = Op1; 1253 } else { 1254 // All of the operands are live after this instruction executes, so we 1255 // cannot update on top of any operand. Because of this, we must 1256 // duplicate one of the stack elements to the top. It doesn't matter 1257 // which one we pick. 1258 // 1259 duplicateToTop(Op0, Dest, I); 1260 Op0 = TOS = Dest; 1261 KillsOp0 = true; 1262 } 1263 } else if (!KillsOp0 && !KillsOp1) { 1264 // If we DO have one of our operands at the top of the stack, but we don't 1265 // have a dead operand, we must duplicate one of the operands to a new slot 1266 // on the stack. 1267 duplicateToTop(Op0, Dest, I); 1268 Op0 = TOS = Dest; 1269 KillsOp0 = true; 1270 } 1271 1272 // Now we know that one of our operands is on the top of the stack, and at 1273 // least one of our operands is killed by this instruction. 1274 assert((TOS == Op0 || TOS == Op1) && (KillsOp0 || KillsOp1) && 1275 "Stack conditions not set up right!"); 1276 1277 // We decide which form to use based on what is on the top of the stack, and 1278 // which operand is killed by this instruction. 1279 ArrayRef<TableEntry> InstTable; 1280 bool isForward = TOS == Op0; 1281 bool updateST0 = (TOS == Op0 && !KillsOp1) || (TOS == Op1 && !KillsOp0); 1282 if (updateST0) { 1283 if (isForward) 1284 InstTable = ForwardST0Table; 1285 else 1286 InstTable = ReverseST0Table; 1287 } else { 1288 if (isForward) 1289 InstTable = ForwardSTiTable; 1290 else 1291 InstTable = ReverseSTiTable; 1292 } 1293 1294 int Opcode = Lookup(InstTable, MI.getOpcode()); 1295 assert(Opcode != -1 && "Unknown TwoArgFP pseudo instruction!"); 1296 1297 // NotTOS - The register which is not on the top of stack... 1298 unsigned NotTOS = (TOS == Op0) ? Op1 : Op0; 1299 1300 // Replace the old instruction with a new instruction 1301 MBB->remove(&*I++); 1302 I = BuildMI(*MBB, I, dl, TII->get(Opcode)).addReg(getSTReg(NotTOS)); 1303 1304 // If both operands are killed, pop one off of the stack in addition to 1305 // overwriting the other one. 1306 if (KillsOp0 && KillsOp1 && Op0 != Op1) { 1307 assert(!updateST0 && "Should have updated other operand!"); 1308 popStackAfter(I); // Pop the top of stack 1309 } 1310 1311 // Update stack information so that we know the destination register is now on 1312 // the stack. 1313 unsigned UpdatedSlot = getSlot(updateST0 ? TOS : NotTOS); 1314 assert(UpdatedSlot < StackTop && Dest < 7); 1315 Stack[UpdatedSlot] = Dest; 1316 RegMap[Dest] = UpdatedSlot; 1317 MBB->getParent()->DeleteMachineInstr(&MI); // Remove the old instruction 1318 } 1319 1320 /// handleCompareFP - Handle FUCOM and FUCOMI instructions, which have two FP 1321 /// register arguments and no explicit destinations. 1322 /// 1323 void FPS::handleCompareFP(MachineBasicBlock::iterator &I) { 1324 ASSERT_SORTED(ForwardST0Table); ASSERT_SORTED(ReverseST0Table); 1325 ASSERT_SORTED(ForwardSTiTable); ASSERT_SORTED(ReverseSTiTable); 1326 MachineInstr &MI = *I; 1327 1328 unsigned NumOperands = MI.getDesc().getNumOperands(); 1329 assert(NumOperands == 2 && "Illegal FUCOM* instruction!"); 1330 unsigned Op0 = getFPReg(MI.getOperand(NumOperands - 2)); 1331 unsigned Op1 = getFPReg(MI.getOperand(NumOperands - 1)); 1332 bool KillsOp0 = MI.killsRegister(X86::FP0 + Op0); 1333 bool KillsOp1 = MI.killsRegister(X86::FP0 + Op1); 1334 1335 // Make sure the first operand is on the top of stack, the other one can be 1336 // anywhere. 1337 moveToTop(Op0, I); 1338 1339 // Change from the pseudo instruction to the concrete instruction. 1340 MI.getOperand(0).setReg(getSTReg(Op1)); 1341 MI.RemoveOperand(1); 1342 MI.setDesc(TII->get(getConcreteOpcode(MI.getOpcode()))); 1343 1344 // If any of the operands are killed by this instruction, free them. 1345 if (KillsOp0) freeStackSlotAfter(I, Op0); 1346 if (KillsOp1 && Op0 != Op1) freeStackSlotAfter(I, Op1); 1347 } 1348 1349 /// handleCondMovFP - Handle two address conditional move instructions. These 1350 /// instructions move a st(i) register to st(0) iff a condition is true. These 1351 /// instructions require that the first operand is at the top of the stack, but 1352 /// otherwise don't modify the stack at all. 1353 void FPS::handleCondMovFP(MachineBasicBlock::iterator &I) { 1354 MachineInstr &MI = *I; 1355 1356 unsigned Op0 = getFPReg(MI.getOperand(0)); 1357 unsigned Op1 = getFPReg(MI.getOperand(2)); 1358 bool KillsOp1 = MI.killsRegister(X86::FP0 + Op1); 1359 1360 // The first operand *must* be on the top of the stack. 1361 moveToTop(Op0, I); 1362 1363 // Change the second operand to the stack register that the operand is in. 1364 // Change from the pseudo instruction to the concrete instruction. 1365 MI.RemoveOperand(0); 1366 MI.RemoveOperand(1); 1367 MI.getOperand(0).setReg(getSTReg(Op1)); 1368 MI.setDesc(TII->get(getConcreteOpcode(MI.getOpcode()))); 1369 1370 // If we kill the second operand, make sure to pop it from the stack. 1371 if (Op0 != Op1 && KillsOp1) { 1372 // Get this value off of the register stack. 1373 freeStackSlotAfter(I, Op1); 1374 } 1375 } 1376 1377 1378 /// handleSpecialFP - Handle special instructions which behave unlike other 1379 /// floating point instructions. This is primarily intended for use by pseudo 1380 /// instructions. 1381 /// 1382 void FPS::handleSpecialFP(MachineBasicBlock::iterator &Inst) { 1383 MachineInstr &MI = *Inst; 1384 1385 if (MI.isCall()) { 1386 handleCall(Inst); 1387 return; 1388 } 1389 1390 if (MI.isReturn()) { 1391 handleReturn(Inst); 1392 return; 1393 } 1394 1395 switch (MI.getOpcode()) { 1396 default: llvm_unreachable("Unknown SpecialFP instruction!"); 1397 case TargetOpcode::COPY: { 1398 // We handle three kinds of copies: FP <- FP, FP <- ST, and ST <- FP. 1399 const MachineOperand &MO1 = MI.getOperand(1); 1400 const MachineOperand &MO0 = MI.getOperand(0); 1401 bool KillsSrc = MI.killsRegister(MO1.getReg()); 1402 1403 // FP <- FP copy. 1404 unsigned DstFP = getFPReg(MO0); 1405 unsigned SrcFP = getFPReg(MO1); 1406 assert(isLive(SrcFP) && "Cannot copy dead register"); 1407 if (KillsSrc) { 1408 // If the input operand is killed, we can just change the owner of the 1409 // incoming stack slot into the result. 1410 unsigned Slot = getSlot(SrcFP); 1411 Stack[Slot] = DstFP; 1412 RegMap[DstFP] = Slot; 1413 } else { 1414 // For COPY we just duplicate the specified value to a new stack slot. 1415 // This could be made better, but would require substantial changes. 1416 duplicateToTop(SrcFP, DstFP, Inst); 1417 } 1418 break; 1419 } 1420 1421 case TargetOpcode::IMPLICIT_DEF: { 1422 // All FP registers must be explicitly defined, so load a 0 instead. 1423 unsigned Reg = MI.getOperand(0).getReg() - X86::FP0; 1424 DEBUG(dbgs() << "Emitting LD_F0 for implicit FP" << Reg << '\n'); 1425 BuildMI(*MBB, Inst, MI.getDebugLoc(), TII->get(X86::LD_F0)); 1426 pushReg(Reg); 1427 break; 1428 } 1429 1430 case TargetOpcode::INLINEASM: { 1431 // The inline asm MachineInstr currently only *uses* FP registers for the 1432 // 'f' constraint. These should be turned into the current ST(x) register 1433 // in the machine instr. 1434 // 1435 // There are special rules for x87 inline assembly. The compiler must know 1436 // exactly how many registers are popped and pushed implicitly by the asm. 1437 // Otherwise it is not possible to restore the stack state after the inline 1438 // asm. 1439 // 1440 // There are 3 kinds of input operands: 1441 // 1442 // 1. Popped inputs. These must appear at the stack top in ST0-STn. A 1443 // popped input operand must be in a fixed stack slot, and it is either 1444 // tied to an output operand, or in the clobber list. The MI has ST use 1445 // and def operands for these inputs. 1446 // 1447 // 2. Fixed inputs. These inputs appear in fixed stack slots, but are 1448 // preserved by the inline asm. The fixed stack slots must be STn-STm 1449 // following the popped inputs. A fixed input operand cannot be tied to 1450 // an output or appear in the clobber list. The MI has ST use operands 1451 // and no defs for these inputs. 1452 // 1453 // 3. Preserved inputs. These inputs use the "f" constraint which is 1454 // represented as an FP register. The inline asm won't change these 1455 // stack slots. 1456 // 1457 // Outputs must be in ST registers, FP outputs are not allowed. Clobbered 1458 // registers do not count as output operands. The inline asm changes the 1459 // stack as if it popped all the popped inputs and then pushed all the 1460 // output operands. 1461 1462 // Scan the assembly for ST registers used, defined and clobbered. We can 1463 // only tell clobbers from defs by looking at the asm descriptor. 1464 unsigned STUses = 0, STDefs = 0, STClobbers = 0, STDeadDefs = 0; 1465 unsigned NumOps = 0; 1466 SmallSet<unsigned, 1> FRegIdx; 1467 unsigned RCID; 1468 1469 for (unsigned i = InlineAsm::MIOp_FirstOperand, e = MI.getNumOperands(); 1470 i != e && MI.getOperand(i).isImm(); i += 1 + NumOps) { 1471 unsigned Flags = MI.getOperand(i).getImm(); 1472 1473 NumOps = InlineAsm::getNumOperandRegisters(Flags); 1474 if (NumOps != 1) 1475 continue; 1476 const MachineOperand &MO = MI.getOperand(i + 1); 1477 if (!MO.isReg()) 1478 continue; 1479 unsigned STReg = MO.getReg() - X86::FP0; 1480 if (STReg >= 8) 1481 continue; 1482 1483 // If the flag has a register class constraint, this must be an operand 1484 // with constraint "f". Record its index and continue. 1485 if (InlineAsm::hasRegClassConstraint(Flags, RCID)) { 1486 FRegIdx.insert(i + 1); 1487 continue; 1488 } 1489 1490 switch (InlineAsm::getKind(Flags)) { 1491 case InlineAsm::Kind_RegUse: 1492 STUses |= (1u << STReg); 1493 break; 1494 case InlineAsm::Kind_RegDef: 1495 case InlineAsm::Kind_RegDefEarlyClobber: 1496 STDefs |= (1u << STReg); 1497 if (MO.isDead()) 1498 STDeadDefs |= (1u << STReg); 1499 break; 1500 case InlineAsm::Kind_Clobber: 1501 STClobbers |= (1u << STReg); 1502 break; 1503 default: 1504 break; 1505 } 1506 } 1507 1508 if (STUses && !isMask_32(STUses)) 1509 MI.emitError("fixed input regs must be last on the x87 stack"); 1510 unsigned NumSTUses = countTrailingOnes(STUses); 1511 1512 // Defs must be contiguous from the stack top. ST0-STn. 1513 if (STDefs && !isMask_32(STDefs)) { 1514 MI.emitError("output regs must be last on the x87 stack"); 1515 STDefs = NextPowerOf2(STDefs) - 1; 1516 } 1517 unsigned NumSTDefs = countTrailingOnes(STDefs); 1518 1519 // So must the clobbered stack slots. ST0-STm, m >= n. 1520 if (STClobbers && !isMask_32(STDefs | STClobbers)) 1521 MI.emitError("clobbers must be last on the x87 stack"); 1522 1523 // Popped inputs are the ones that are also clobbered or defined. 1524 unsigned STPopped = STUses & (STDefs | STClobbers); 1525 if (STPopped && !isMask_32(STPopped)) 1526 MI.emitError("implicitly popped regs must be last on the x87 stack"); 1527 unsigned NumSTPopped = countTrailingOnes(STPopped); 1528 1529 DEBUG(dbgs() << "Asm uses " << NumSTUses << " fixed regs, pops " 1530 << NumSTPopped << ", and defines " << NumSTDefs << " regs.\n"); 1531 1532 #ifndef NDEBUG 1533 // If any input operand uses constraint "f", all output register 1534 // constraints must be early-clobber defs. 1535 for (unsigned I = 0, E = MI.getNumOperands(); I < E; ++I) 1536 if (FRegIdx.count(I)) { 1537 assert((1 << getFPReg(MI.getOperand(I)) & STDefs) == 0 && 1538 "Operands with constraint \"f\" cannot overlap with defs"); 1539 } 1540 #endif 1541 1542 // Collect all FP registers (register operands with constraints "t", "u", 1543 // and "f") to kill afer the instruction. 1544 unsigned FPKills = ((1u << NumFPRegs) - 1) & ~0xff; 1545 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { 1546 MachineOperand &Op = MI.getOperand(i); 1547 if (!Op.isReg() || Op.getReg() < X86::FP0 || Op.getReg() > X86::FP6) 1548 continue; 1549 unsigned FPReg = getFPReg(Op); 1550 1551 // If we kill this operand, make sure to pop it from the stack after the 1552 // asm. We just remember it for now, and pop them all off at the end in 1553 // a batch. 1554 if (Op.isUse() && Op.isKill()) 1555 FPKills |= 1U << FPReg; 1556 } 1557 1558 // Do not include registers that are implicitly popped by defs/clobbers. 1559 FPKills &= ~(STDefs | STClobbers); 1560 1561 // Now we can rearrange the live registers to match what was requested. 1562 unsigned char STUsesArray[8]; 1563 1564 for (unsigned I = 0; I < NumSTUses; ++I) 1565 STUsesArray[I] = I; 1566 1567 shuffleStackTop(STUsesArray, NumSTUses, Inst); 1568 DEBUG({dbgs() << "Before asm: "; dumpStack();}); 1569 1570 // With the stack layout fixed, rewrite the FP registers. 1571 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { 1572 MachineOperand &Op = MI.getOperand(i); 1573 if (!Op.isReg() || Op.getReg() < X86::FP0 || Op.getReg() > X86::FP6) 1574 continue; 1575 1576 unsigned FPReg = getFPReg(Op); 1577 1578 if (FRegIdx.count(i)) 1579 // Operand with constraint "f". 1580 Op.setReg(getSTReg(FPReg)); 1581 else 1582 // Operand with a single register class constraint ("t" or "u"). 1583 Op.setReg(X86::ST0 + FPReg); 1584 } 1585 1586 // Simulate the inline asm popping its inputs and pushing its outputs. 1587 StackTop -= NumSTPopped; 1588 1589 for (unsigned i = 0; i < NumSTDefs; ++i) 1590 pushReg(NumSTDefs - i - 1); 1591 1592 // If this asm kills any FP registers (is the last use of them) we must 1593 // explicitly emit pop instructions for them. Do this now after the asm has 1594 // executed so that the ST(x) numbers are not off (which would happen if we 1595 // did this inline with operand rewriting). 1596 // 1597 // Note: this might be a non-optimal pop sequence. We might be able to do 1598 // better by trying to pop in stack order or something. 1599 while (FPKills) { 1600 unsigned FPReg = countTrailingZeros(FPKills); 1601 if (isLive(FPReg)) 1602 freeStackSlotAfter(Inst, FPReg); 1603 FPKills &= ~(1U << FPReg); 1604 } 1605 1606 // Don't delete the inline asm! 1607 return; 1608 } 1609 } 1610 1611 Inst = MBB->erase(Inst); // Remove the pseudo instruction 1612 1613 // We want to leave I pointing to the previous instruction, but what if we 1614 // just erased the first instruction? 1615 if (Inst == MBB->begin()) { 1616 DEBUG(dbgs() << "Inserting dummy KILL\n"); 1617 Inst = BuildMI(*MBB, Inst, DebugLoc(), TII->get(TargetOpcode::KILL)); 1618 } else 1619 --Inst; 1620 } 1621 1622 void FPS::setKillFlags(MachineBasicBlock &MBB) const { 1623 const TargetRegisterInfo *TRI = 1624 MBB.getParent()->getSubtarget().getRegisterInfo(); 1625 LivePhysRegs LPR(TRI); 1626 1627 LPR.addLiveOuts(MBB); 1628 1629 for (MachineBasicBlock::reverse_iterator I = MBB.rbegin(), E = MBB.rend(); 1630 I != E; ++I) { 1631 if (I->isDebugValue()) 1632 continue; 1633 1634 std::bitset<8> Defs; 1635 SmallVector<MachineOperand *, 2> Uses; 1636 MachineInstr &MI = *I; 1637 1638 for (auto &MO : I->operands()) { 1639 if (!MO.isReg()) 1640 continue; 1641 1642 unsigned Reg = MO.getReg() - X86::FP0; 1643 1644 if (Reg >= 8) 1645 continue; 1646 1647 if (MO.isDef()) { 1648 Defs.set(Reg); 1649 if (!LPR.contains(MO.getReg())) 1650 MO.setIsDead(); 1651 } else 1652 Uses.push_back(&MO); 1653 } 1654 1655 for (auto *MO : Uses) 1656 if (Defs.test(getFPReg(*MO)) || !LPR.contains(MO->getReg())) 1657 MO->setIsKill(); 1658 1659 LPR.stepBackward(MI); 1660 } 1661 } 1662
