1 /* tc-m68k.c -- Assemble for the m68k family 2 Copyright (C) 1987-2016 Free Software Foundation, Inc. 3 4 This file is part of GAS, the GNU Assembler. 5 6 GAS is free software; you can redistribute it and/or modify 7 it under the terms of the GNU General Public License as published by 8 the Free Software Foundation; either version 3, or (at your option) 9 any later version. 10 11 GAS is distributed in the hope that it will be useful, 12 but WITHOUT ANY WARRANTY; without even the implied warranty of 13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 GNU General Public License for more details. 15 16 You should have received a copy of the GNU General Public License 17 along with GAS; see the file COPYING. If not, write to the Free 18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 19 02110-1301, USA. */ 20 21 #include "as.h" 22 #include "safe-ctype.h" 23 #include "obstack.h" 24 #include "subsegs.h" 25 #include "dwarf2dbg.h" 26 #include "dw2gencfi.h" 27 28 #include "opcode/m68k.h" 29 #include "m68k-parse.h" 30 31 #if defined (OBJ_ELF) 32 #include "elf/m68k.h" 33 #endif 34 35 #ifdef M68KCOFF 36 #include "obj-coff.h" 37 #endif 38 39 #ifdef OBJ_ELF 40 static void m68k_elf_cons (int); 41 #endif 42 43 /* This string holds the chars that always start a comment. If the 44 pre-processor is disabled, these aren't very useful. The macro 45 tc_comment_chars points to this. We use this, rather than the 46 usual comment_chars, so that the --bitwise-or option will work. */ 47 #if defined (TE_SVR4) || defined (TE_DELTA) 48 const char *m68k_comment_chars = "|#"; 49 #else 50 const char *m68k_comment_chars = "|"; 51 #endif 52 53 /* This array holds the chars that only start a comment at the beginning of 54 a line. If the line seems to have the form '# 123 filename' 55 .line and .file directives will appear in the pre-processed output */ 56 /* Note that input_file.c hand checks for '#' at the beginning of the 57 first line of the input file. This is because the compiler outputs 58 #NO_APP at the beginning of its output. */ 59 /* Also note that comments like this one will always work. */ 60 const char line_comment_chars[] = "#*"; 61 62 const char line_separator_chars[] = ";"; 63 64 /* Chars that can be used to separate mant from exp in floating point nums. */ 65 const char EXP_CHARS[] = "eE"; 66 67 /* Chars that mean this number is a floating point constant, as 68 in "0f12.456" or "0d1.2345e12". */ 69 70 const char FLT_CHARS[] = "rRsSfFdDxXeEpP"; 71 72 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be 73 changed in read.c . Ideally it shouldn't have to know about it at all, 74 but nothing is ideal around here. */ 75 76 /* Are we trying to generate PIC code? If so, absolute references 77 ought to be made into linkage table references or pc-relative 78 references. Not implemented. For ELF there are other means 79 to denote pic relocations. */ 80 int flag_want_pic; 81 82 static int flag_short_refs; /* -l option. */ 83 static int flag_long_jumps; /* -S option. */ 84 static int flag_keep_pcrel; /* --pcrel option. */ 85 86 #ifdef REGISTER_PREFIX_OPTIONAL 87 int flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL; 88 #else 89 int flag_reg_prefix_optional; 90 #endif 91 92 /* Whether --register-prefix-optional was used on the command line. */ 93 static int reg_prefix_optional_seen; 94 95 /* The floating point coprocessor to use by default. */ 96 static enum m68k_register m68k_float_copnum = COP1; 97 98 /* If this is non-zero, then references to number(%pc) will be taken 99 to refer to number, rather than to %pc + number. */ 100 static int m68k_abspcadd; 101 102 /* If this is non-zero, then the quick forms of the move, add, and sub 103 instructions are used when possible. */ 104 static int m68k_quick = 1; 105 106 /* If this is non-zero, then if the size is not specified for a base 107 or outer displacement, the assembler assumes that the size should 108 be 32 bits. */ 109 static int m68k_rel32 = 1; 110 111 /* This is non-zero if m68k_rel32 was set from the command line. */ 112 static int m68k_rel32_from_cmdline; 113 114 /* The default width to use for an index register when using a base 115 displacement. */ 116 static enum m68k_size m68k_index_width_default = SIZE_LONG; 117 118 /* We want to warn if any text labels are misaligned. In order to get 119 the right line number, we need to record the line number for each 120 label. */ 121 struct label_line 122 { 123 struct label_line *next; 124 symbolS *label; 125 const char *file; 126 unsigned int line; 127 int text; 128 }; 129 130 /* The list of labels. */ 131 132 static struct label_line *labels; 133 134 /* The current label. */ 135 136 static struct label_line *current_label; 137 138 /* Pointer to list holding the opcodes sorted by name. */ 139 static struct m68k_opcode const ** m68k_sorted_opcodes; 140 141 /* Its an arbitrary name: This means I don't approve of it. 142 See flames below. */ 143 static struct obstack robyn; 144 145 struct m68k_incant 146 { 147 const char *m_operands; 148 unsigned long m_opcode; 149 short m_opnum; 150 short m_codenum; 151 int m_arch; 152 struct m68k_incant *m_next; 153 }; 154 155 #define getone(x) ((((x)->m_opcode)>>16)&0xffff) 156 #define gettwo(x) (((x)->m_opcode)&0xffff) 157 158 static const enum m68k_register m68000_ctrl[] = { 0 }; 159 static const enum m68k_register m68010_ctrl[] = { 160 SFC, DFC, USP, VBR, 161 0 162 }; 163 static const enum m68k_register m68020_ctrl[] = { 164 SFC, DFC, USP, VBR, CACR, CAAR, MSP, ISP, 165 0 166 }; 167 static const enum m68k_register m68040_ctrl[] = { 168 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, 169 USP, VBR, MSP, ISP, MMUSR, URP, SRP, 170 0 171 }; 172 static const enum m68k_register m68060_ctrl[] = { 173 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR, 174 USP, VBR, URP, SRP, PCR, 175 0 176 }; 177 static const enum m68k_register mcf_ctrl[] = { 178 CACR, TC, ACR0, ACR1, ACR2, ACR3, VBR, ROMBAR, 179 RAMBAR0, RAMBAR1, RAMBAR, MBAR, 180 0 181 }; 182 static const enum m68k_register mcf51_ctrl[] = { 183 VBR, CPUCR, 184 0 185 }; 186 static const enum m68k_register mcf5206_ctrl[] = { 187 CACR, ACR0, ACR1, VBR, RAMBAR0, RAMBAR_ALT, MBAR, 188 0 189 }; 190 static const enum m68k_register mcf5208_ctrl[] = { 191 CACR, ACR0, ACR1, VBR, RAMBAR, RAMBAR1, 192 0 193 }; 194 static const enum m68k_register mcf5210a_ctrl[] = { 195 VBR, CACR, ACR0, ACR1, ROMBAR, RAMBAR, RAMBAR1, MBAR, 196 0 197 }; 198 static const enum m68k_register mcf5213_ctrl[] = { 199 VBR, RAMBAR, RAMBAR1, FLASHBAR, 200 0 201 }; 202 static const enum m68k_register mcf5216_ctrl[] = { 203 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, RAMBAR1, 204 0 205 }; 206 static const enum m68k_register mcf5221x_ctrl[] = { 207 VBR, FLASHBAR, RAMBAR, RAMBAR1, 208 0 209 }; 210 static const enum m68k_register mcf52223_ctrl[] = { 211 VBR, FLASHBAR, RAMBAR, RAMBAR1, 212 0 213 }; 214 static const enum m68k_register mcf52235_ctrl[] = { 215 VBR, FLASHBAR, RAMBAR, RAMBAR1, 216 0 217 }; 218 static const enum m68k_register mcf5225_ctrl[] = { 219 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, MBAR, RAMBAR1, 220 0 221 }; 222 static const enum m68k_register mcf52259_ctrl[] = { 223 VBR, FLASHBAR, RAMBAR, RAMBAR1, 224 0 225 }; 226 static const enum m68k_register mcf52277_ctrl[] = { 227 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1, 228 0 229 }; 230 static const enum m68k_register mcf5235_ctrl[] = { 231 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1, 232 0 233 }; 234 static const enum m68k_register mcf5249_ctrl[] = { 235 VBR, CACR, ACR0, ACR1, RAMBAR0, RAMBAR1, RAMBAR, MBAR, MBAR2, 236 0 237 }; 238 static const enum m68k_register mcf5250_ctrl[] = { 239 VBR, 240 0 241 }; 242 static const enum m68k_register mcf5253_ctrl[] = { 243 VBR, CACR, ACR0, ACR1, RAMBAR0, RAMBAR1, RAMBAR, MBAR, MBAR2, 244 0 245 }; 246 static const enum m68k_register mcf5271_ctrl[] = { 247 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1, 248 0 249 }; 250 static const enum m68k_register mcf5272_ctrl[] = { 251 VBR, CACR, ACR0, ACR1, ROMBAR, RAMBAR_ALT, RAMBAR0, MBAR, 252 0 253 }; 254 static const enum m68k_register mcf5275_ctrl[] = { 255 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1, 256 0 257 }; 258 static const enum m68k_register mcf5282_ctrl[] = { 259 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, RAMBAR1, 260 0 261 }; 262 static const enum m68k_register mcf53017_ctrl[] = { 263 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1, 264 0 265 }; 266 static const enum m68k_register mcf5307_ctrl[] = { 267 VBR, CACR, ACR0, ACR1, RAMBAR0, RAMBAR_ALT, MBAR, 268 0 269 }; 270 static const enum m68k_register mcf5329_ctrl[] = { 271 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1, 272 0 273 }; 274 static const enum m68k_register mcf5373_ctrl[] = { 275 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1, 276 0 277 }; 278 static const enum m68k_register mcfv4e_ctrl[] = { 279 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR, 280 VBR, PC, ROMBAR0, ROMBAR1, RAMBAR0, RAMBAR1, 281 MBAR, SECMBAR, 282 MPCR /* Multiprocessor Control register */, 283 EDRAMBAR /* Embedded DRAM Base Address Register */, 284 /* Permutation control registers. */ 285 PCR1U0, PCR1L0, PCR1U1, PCR1L1, PCR2U0, PCR2L0, PCR2U1, PCR2L1, 286 PCR3U0, PCR3L0, PCR3U1, PCR3L1, 287 /* Legacy names */ 288 TC /* ASID */, BUSCR /* MMUBAR */, 289 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */, 290 MBAR1 /* MBAR */, MBAR2 /* SECMBAR */, MBAR0 /* SECMBAR */, 291 ROMBAR /* ROMBAR0 */, RAMBAR /* RAMBAR1 */, 292 0 293 }; 294 static const enum m68k_register mcf5407_ctrl[] = { 295 CACR, ASID, ACR0, ACR1, ACR2, ACR3, 296 VBR, PC, RAMBAR0, RAMBAR1, MBAR, 297 /* Legacy names */ 298 TC /* ASID */, 299 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */, 300 MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */, 301 0 302 }; 303 static const enum m68k_register mcf54418_ctrl[] = { 304 CACR, ASID, ACR0, ACR1, ACR2, ACR3, ACR4, ACR5, ACR6, ACR7, MMUBAR, RGPIOBAR, 305 VBR, PC, RAMBAR1, 306 /* Legacy names */ 307 TC /* ASID */, BUSCR /* MMUBAR */, 308 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */, 309 RAMBAR /* RAMBAR1 */, 310 0 311 }; 312 static const enum m68k_register mcf54455_ctrl[] = { 313 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR, 314 VBR, PC, RAMBAR1, 315 /* Legacy names */ 316 TC /* ASID */, BUSCR /* MMUBAR */, 317 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */, 318 RAMBAR /* RAMBAR1 */, 319 0 320 }; 321 static const enum m68k_register mcf5475_ctrl[] = { 322 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR, 323 VBR, PC, RAMBAR0, RAMBAR1, MBAR, 324 /* Legacy names */ 325 TC /* ASID */, BUSCR /* MMUBAR */, 326 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */, 327 MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */, 328 0 329 }; 330 static const enum m68k_register mcf5485_ctrl[] = { 331 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR, 332 VBR, PC, RAMBAR0, RAMBAR1, MBAR, 333 /* Legacy names */ 334 TC /* ASID */, BUSCR /* MMUBAR */, 335 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */, 336 MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */, 337 0 338 }; 339 static const enum m68k_register fido_ctrl[] = { 340 SFC, DFC, USP, VBR, CAC, MBO, 341 0 342 }; 343 #define cpu32_ctrl m68010_ctrl 344 345 static const enum m68k_register *control_regs; 346 347 /* Internal form of a 68020 instruction. */ 348 struct m68k_it 349 { 350 const char *error; 351 const char *args; /* List of opcode info. */ 352 int numargs; 353 354 int numo; /* Number of shorts in opcode. */ 355 short opcode[11]; 356 357 struct m68k_op operands[6]; 358 359 int nexp; /* Number of exprs in use. */ 360 struct m68k_exp exprs[4]; 361 362 int nfrag; /* Number of frags we have to produce. */ 363 struct 364 { 365 int fragoff; /* Where in the current opcode the frag ends. */ 366 symbolS *fadd; 367 offsetT foff; 368 int fragty; 369 } 370 fragb[4]; 371 372 int nrel; /* Num of reloc strucs in use. */ 373 struct 374 { 375 int n; 376 expressionS exp; 377 char wid; 378 char pcrel; 379 /* In a pc relative address the difference between the address 380 of the offset and the address that the offset is relative 381 to. This depends on the addressing mode. Basically this 382 is the value to put in the offset field to address the 383 first byte of the offset, without regarding the special 384 significance of some values (in the branch instruction, for 385 example). */ 386 int pcrel_fix; 387 #ifdef OBJ_ELF 388 /* Whether this expression needs special pic relocation, and if 389 so, which. */ 390 enum pic_relocation pic_reloc; 391 #endif 392 } 393 reloc[5]; /* Five is enough??? */ 394 }; 395 396 #define cpu_of_arch(x) ((x) & (m68000up | mcfisa_a | fido_a)) 397 #define float_of_arch(x) ((x) & mfloat) 398 #define mmu_of_arch(x) ((x) & mmmu) 399 #define arch_coldfire_p(x) ((x) & mcfisa_a) 400 #define arch_coldfire_fpu(x) ((x) & cfloat) 401 402 /* Macros for determining if cpu supports a specific addressing mode. */ 403 #define HAVE_LONG_DISP(x) \ 404 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b|mcfisa_c)) 405 #define HAVE_LONG_CALL(x) \ 406 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b|mcfisa_c)) 407 #define HAVE_LONG_COND(x) \ 408 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b|mcfisa_c)) 409 #define HAVE_LONG_BRANCH(x) \ 410 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b)) 411 #define LONG_BRANCH_VIA_COND(x) (HAVE_LONG_COND(x) && !HAVE_LONG_BRANCH(x)) 412 413 static struct m68k_it the_ins; /* The instruction being assembled. */ 414 415 #define op(ex) ((ex)->exp.X_op) 416 #define adds(ex) ((ex)->exp.X_add_symbol) 417 #define subs(ex) ((ex)->exp.X_op_symbol) 418 #define offs(ex) ((ex)->exp.X_add_number) 419 420 /* Macros for adding things to the m68k_it struct. */ 421 #define addword(w) (the_ins.opcode[the_ins.numo++] = (w)) 422 423 /* Like addword, but goes BEFORE general operands. */ 424 425 static void 426 insop (int w, const struct m68k_incant *opcode) 427 { 428 int z; 429 for (z = the_ins.numo; z > opcode->m_codenum; --z) 430 the_ins.opcode[z] = the_ins.opcode[z - 1]; 431 for (z = 0; z < the_ins.nrel; z++) 432 the_ins.reloc[z].n += 2; 433 for (z = 0; z < the_ins.nfrag; z++) 434 the_ins.fragb[z].fragoff++; 435 the_ins.opcode[opcode->m_codenum] = w; 436 the_ins.numo++; 437 } 438 439 /* The numo+1 kludge is so we can hit the low order byte of the prev word. 440 Blecch. */ 441 static void 442 add_fix (int width, struct m68k_exp *exp, int pc_rel, int pc_fix) 443 { 444 the_ins.reloc[the_ins.nrel].n = (width == 'B' || width == '3' 445 ? the_ins.numo * 2 - 1 446 : (width == 'b' 447 ? the_ins.numo * 2 + 1 448 : the_ins.numo * 2)); 449 the_ins.reloc[the_ins.nrel].exp = exp->exp; 450 the_ins.reloc[the_ins.nrel].wid = width; 451 the_ins.reloc[the_ins.nrel].pcrel_fix = pc_fix; 452 #ifdef OBJ_ELF 453 the_ins.reloc[the_ins.nrel].pic_reloc = exp->pic_reloc; 454 #endif 455 the_ins.reloc[the_ins.nrel++].pcrel = pc_rel; 456 } 457 458 /* Cause an extra frag to be generated here, inserting up to 10 bytes 459 (that value is chosen in the frag_var call in md_assemble). TYPE 460 is the subtype of the frag to be generated; its primary type is 461 rs_machine_dependent. 462 463 The TYPE parameter is also used by md_convert_frag_1 and 464 md_estimate_size_before_relax. The appropriate type of fixup will 465 be emitted by md_convert_frag_1. 466 467 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */ 468 static void 469 add_frag (symbolS *add, offsetT off, int type) 470 { 471 the_ins.fragb[the_ins.nfrag].fragoff = the_ins.numo; 472 the_ins.fragb[the_ins.nfrag].fadd = add; 473 the_ins.fragb[the_ins.nfrag].foff = off; 474 the_ins.fragb[the_ins.nfrag++].fragty = type; 475 } 476 477 #define isvar(ex) \ 478 (op (ex) != O_constant && op (ex) != O_big) 479 480 static char *crack_operand (char *str, struct m68k_op *opP); 481 static int get_num (struct m68k_exp *exp, int ok); 482 static int reverse_16_bits (int in); 483 static int reverse_8_bits (int in); 484 static void install_gen_operand (int mode, int val); 485 static void install_operand (int mode, int val); 486 static void s_bss (int); 487 static void s_data1 (int); 488 static void s_data2 (int); 489 static void s_even (int); 490 static void s_proc (int); 491 static void s_chip (int); 492 static void s_fopt (int); 493 static void s_opt (int); 494 static void s_reg (int); 495 static void s_restore (int); 496 static void s_save (int); 497 static void s_mri_if (int); 498 static void s_mri_else (int); 499 static void s_mri_endi (int); 500 static void s_mri_break (int); 501 static void s_mri_next (int); 502 static void s_mri_for (int); 503 static void s_mri_endf (int); 504 static void s_mri_repeat (int); 505 static void s_mri_until (int); 506 static void s_mri_while (int); 507 static void s_mri_endw (int); 508 static void s_m68k_cpu (int); 509 static void s_m68k_arch (int); 510 511 struct m68k_cpu 512 { 513 unsigned long arch; /* Architecture features. */ 514 const enum m68k_register *control_regs; /* Control regs on chip */ 515 const char *name; /* Name */ 516 int alias; /* Alias for a cannonical name. If 1, then 517 succeeds canonical name, if -1 then 518 succeeds canonical name, if <-1 ||>1 this is a 519 deprecated name, and the next/previous name 520 should be used. */ 521 }; 522 523 /* We hold flags for features explicitly enabled and explicitly 524 disabled. */ 525 static int current_architecture; 526 static int not_current_architecture; 527 static const struct m68k_cpu *selected_arch; 528 static const struct m68k_cpu *selected_cpu; 529 static int initialized; 530 531 /* Architecture models. */ 532 static const struct m68k_cpu m68k_archs[] = 533 { 534 {m68000, m68000_ctrl, "68000", 0}, 535 {m68010, m68010_ctrl, "68010", 0}, 536 {m68020|m68881|m68851, m68020_ctrl, "68020", 0}, 537 {m68030|m68881|m68851, m68020_ctrl, "68030", 0}, 538 {m68040, m68040_ctrl, "68040", 0}, 539 {m68060, m68060_ctrl, "68060", 0}, 540 {cpu32|m68881, cpu32_ctrl, "cpu32", 0}, 541 {fido_a, fido_ctrl, "fidoa", 0}, 542 {mcfisa_a|mcfhwdiv, NULL, "isaa", 0}, 543 {mcfisa_a|mcfhwdiv|mcfisa_aa|mcfusp, NULL, "isaaplus", 0}, 544 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfusp, NULL, "isab", 0}, 545 {mcfisa_a|mcfhwdiv|mcfisa_c|mcfusp, NULL, "isac", 0}, 546 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfmac|mcfusp, mcf_ctrl, "cfv4", 0}, 547 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "cfv4e", 0}, 548 {0,0,NULL, 0} 549 }; 550 551 /* For -mno-mac we want to turn off all types of mac. */ 552 static const unsigned no_mac = mcfmac | mcfemac; 553 554 /* Architecture extensions, here 'alias' -1 for m68k, +1 for cf and 0 555 for either. */ 556 static const struct m68k_cpu m68k_extensions[] = 557 { 558 {m68851, NULL, "68851", -1}, 559 {m68881, NULL, "68881", -1}, 560 {m68881, NULL, "68882", -1}, 561 562 {cfloat|m68881, NULL, "float", 0}, 563 564 {mcfhwdiv, NULL, "div", 1}, 565 {mcfusp, NULL, "usp", 1}, 566 {mcfmac, (void *)&no_mac, "mac", 1}, 567 {mcfemac, NULL, "emac", 1}, 568 569 {0,NULL,NULL, 0} 570 }; 571 572 /* Processor list */ 573 static const struct m68k_cpu m68k_cpus[] = 574 { 575 {m68000, m68000_ctrl, "68000", 0}, 576 {m68000, m68000_ctrl, "68ec000", 1}, 577 {m68000, m68000_ctrl, "68hc000", 1}, 578 {m68000, m68000_ctrl, "68hc001", 1}, 579 {m68000, m68000_ctrl, "68008", 1}, 580 {m68000, m68000_ctrl, "68302", 1}, 581 {m68000, m68000_ctrl, "68306", 1}, 582 {m68000, m68000_ctrl, "68307", 1}, 583 {m68000, m68000_ctrl, "68322", 1}, 584 {m68000, m68000_ctrl, "68356", 1}, 585 {m68010, m68010_ctrl, "68010", 0}, 586 {m68020|m68881|m68851, m68020_ctrl, "68020", 0}, 587 {m68020|m68881|m68851, m68020_ctrl, "68k", 1}, 588 {m68020|m68881|m68851, m68020_ctrl, "68ec020", 1}, 589 {m68030|m68881|m68851, m68020_ctrl, "68030", 0}, 590 {m68030|m68881|m68851, m68020_ctrl, "68ec030", 1}, 591 {m68040, m68040_ctrl, "68040", 0}, 592 {m68040, m68040_ctrl, "68ec040", 1}, 593 {m68060, m68060_ctrl, "68060", 0}, 594 {m68060, m68060_ctrl, "68ec060", 1}, 595 596 {cpu32|m68881, cpu32_ctrl, "cpu32", 0}, 597 {cpu32|m68881, cpu32_ctrl, "68330", 1}, 598 {cpu32|m68881, cpu32_ctrl, "68331", 1}, 599 {cpu32|m68881, cpu32_ctrl, "68332", 1}, 600 {cpu32|m68881, cpu32_ctrl, "68333", 1}, 601 {cpu32|m68881, cpu32_ctrl, "68334", 1}, 602 {cpu32|m68881, cpu32_ctrl, "68336", 1}, 603 {cpu32|m68881, cpu32_ctrl, "68340", 1}, 604 {cpu32|m68881, cpu32_ctrl, "68341", 1}, 605 {cpu32|m68881, cpu32_ctrl, "68349", 1}, 606 {cpu32|m68881, cpu32_ctrl, "68360", 1}, 607 608 {mcfisa_a|mcfisa_c|mcfusp, mcf51_ctrl, "51", 0}, 609 {mcfisa_a|mcfisa_c|mcfusp, mcf51_ctrl, "51ac", 1}, 610 {mcfisa_a|mcfisa_c|mcfusp, mcf51_ctrl, "51ag", 1}, 611 {mcfisa_a|mcfisa_c|mcfusp, mcf51_ctrl, "51cn", 1}, 612 {mcfisa_a|mcfisa_c|mcfusp|mcfmac, mcf51_ctrl, "51em", 1}, 613 {mcfisa_a|mcfisa_c|mcfusp|mcfmac, mcf51_ctrl, "51je", 1}, 614 {mcfisa_a|mcfisa_c|mcfusp|mcfemac, mcf51_ctrl, "51jf", 1}, 615 {mcfisa_a|mcfisa_c|mcfusp|mcfemac, mcf51_ctrl, "51jg", 1}, 616 {mcfisa_a|mcfisa_c|mcfusp, mcf51_ctrl, "51jm", 1}, 617 {mcfisa_a|mcfisa_c|mcfusp|mcfmac, mcf51_ctrl, "51mm", 1}, 618 {mcfisa_a|mcfisa_c|mcfusp, mcf51_ctrl, "51qe", 1}, 619 {mcfisa_a|mcfisa_c|mcfusp|mcfemac, mcf51_ctrl, "51qm", 1}, 620 621 {mcfisa_a, mcf_ctrl, "5200", 0}, 622 {mcfisa_a, mcf_ctrl, "5202", 1}, 623 {mcfisa_a, mcf_ctrl, "5204", 1}, 624 {mcfisa_a, mcf5206_ctrl, "5206", 1}, 625 626 {mcfisa_a|mcfhwdiv|mcfmac, mcf5206_ctrl, "5206e", 0}, 627 628 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5208_ctrl, "5207", -1}, 629 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5208_ctrl, "5208", 0}, 630 631 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5210a_ctrl, "5210a", 0}, 632 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5210a_ctrl, "5211a", 1}, 633 634 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5211", -1}, 635 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5212", -1}, 636 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5213", 0}, 637 638 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "5214", -1}, 639 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "5216", 0}, 640 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "521x", 2}, 641 642 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5221x_ctrl, "5221x", 0}, 643 644 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf52223_ctrl, "52221", -1}, 645 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf52223_ctrl, "52223", 0}, 646 647 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52230", -1}, 648 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52233", -1}, 649 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52234", -1}, 650 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52235", 0}, 651 652 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5225_ctrl, "5224", -1}, 653 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5225_ctrl, "5225", 0}, 654 655 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52277_ctrl, "52274", -1}, 656 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52277_ctrl, "52277", 0}, 657 658 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5232", -1}, 659 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5233", -1}, 660 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5234", -1}, 661 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5235", -1}, 662 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "523x", 0}, 663 664 {mcfisa_a|mcfhwdiv|mcfemac, mcf5249_ctrl, "5249", 0}, 665 {mcfisa_a|mcfhwdiv|mcfemac, mcf5250_ctrl, "5250", 0}, 666 {mcfisa_a|mcfhwdiv|mcfemac, mcf5253_ctrl, "5253", 0}, 667 668 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52259_ctrl, "52252", -1}, 669 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52259_ctrl, "52254", -1}, 670 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52259_ctrl, "52255", -1}, 671 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52259_ctrl, "52256", -1}, 672 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52259_ctrl, "52258", -1}, 673 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52259_ctrl, "52259", 0}, 674 675 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5271_ctrl, "5270", -1}, 676 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5271_ctrl, "5271", 0}, 677 678 {mcfisa_a|mcfhwdiv|mcfmac, mcf5272_ctrl, "5272", 0}, 679 680 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5275_ctrl, "5274", -1}, 681 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5275_ctrl, "5275", 0}, 682 683 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5280", -1}, 684 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5281", -1}, 685 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5282", -1}, 686 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "528x", 0}, 687 688 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53011", -1}, 689 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53012", -1}, 690 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53013", -1}, 691 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53014", -1}, 692 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53015", -1}, 693 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53016", -1}, 694 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53017", 0}, 695 696 {mcfisa_a|mcfhwdiv|mcfmac, mcf5307_ctrl, "5307", 0}, 697 698 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5327", -1}, 699 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5328", -1}, 700 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5329", -1}, 701 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "532x", 0}, 702 703 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "5372", -1}, 704 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "5373", -1}, 705 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "537x", 0}, 706 707 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfmac, mcf5407_ctrl, "5407",0}, 708 709 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54418_ctrl, "54410", -1}, 710 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54418_ctrl, "54415", -1}, 711 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54418_ctrl, "54416", -1}, 712 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54418_ctrl, "54417", -1}, 713 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54418_ctrl, "54418", 0}, 714 715 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54450", -1}, 716 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54451", -1}, 717 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54452", -1}, 718 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54453", -1}, 719 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54454", -1}, 720 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54455", 0}, 721 722 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5470", -1}, 723 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5471", -1}, 724 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5472", -1}, 725 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5473", -1}, 726 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5474", -1}, 727 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5475", -1}, 728 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "547x", 0}, 729 730 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5480", -1}, 731 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5481", -1}, 732 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5482", -1}, 733 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5483", -1}, 734 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5484", -1}, 735 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5485", -1}, 736 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "548x", 0}, 737 738 {fido_a, fido_ctrl, "fidoa", 0}, 739 {fido_a, fido_ctrl, "fido", 1}, 740 741 {0,NULL,NULL, 0} 742 }; 743 744 static const struct m68k_cpu *m68k_lookup_cpu 745 (const char *, const struct m68k_cpu *, int, int *); 746 static int m68k_set_arch (const char *, int, int); 747 static int m68k_set_cpu (const char *, int, int); 748 static int m68k_set_extension (const char *, int, int); 749 static void m68k_init_arch (void); 750 751 /* This is the assembler relaxation table for m68k. m68k is a rich CISC 752 architecture and we have a lot of relaxation modes. */ 753 754 /* Macros used in the relaxation code. */ 755 #define TAB(x,y) (((x) << 2) + (y)) 756 #define TABTYPE(x) ((x) >> 2) 757 758 /* Relaxation states. */ 759 #define BYTE 0 760 #define SHORT 1 761 #define LONG 2 762 #define SZ_UNDEF 3 763 764 /* Here are all the relaxation modes we support. First we can relax ordinary 765 branches. On 68020 and higher and on CPU32 all branch instructions take 766 three forms, so on these CPUs all branches always remain as such. When we 767 have to expand to the LONG form on a 68000, though, we substitute an 768 absolute jump instead. This is a direct replacement for unconditional 769 branches and a branch over a jump for conditional branches. However, if the 770 user requires PIC and disables this with --pcrel, we can only relax between 771 BYTE and SHORT forms, punting if that isn't enough. This gives us four 772 different relaxation modes for branches: */ 773 774 #define BRANCHBWL 0 /* Branch byte, word, or long. */ 775 #define BRABSJUNC 1 /* Absolute jump for LONG, unconditional. */ 776 #define BRABSJCOND 2 /* Absolute jump for LONG, conditional. */ 777 #define BRANCHBW 3 /* Branch byte or word. */ 778 779 /* We also relax coprocessor branches and DBcc's. All CPUs that support 780 coprocessor branches support them in word and long forms, so we have only 781 one relaxation mode for them. DBcc's are word only on all CPUs. We can 782 relax them to the LONG form with a branch-around sequence. This sequence 783 can use a long branch (if available) or an absolute jump (if acceptable). 784 This gives us two relaxation modes. If long branches are not available and 785 absolute jumps are not acceptable, we don't relax DBcc's. */ 786 787 #define FBRANCH 4 /* Coprocessor branch. */ 788 #define DBCCLBR 5 /* DBcc relaxable with a long branch. */ 789 #define DBCCABSJ 6 /* DBcc relaxable with an absolute jump. */ 790 791 /* That's all for instruction relaxation. However, we also relax PC-relative 792 operands. Specifically, we have three operand relaxation modes. On the 793 68000 PC-relative operands can only be 16-bit, but on 68020 and higher and 794 on CPU32 they may be 16-bit or 32-bit. For the latter we relax between the 795 two. Also PC+displacement+index operands in their simple form (with a non- 796 suppressed index without memory indirection) are supported on all CPUs, but 797 on the 68000 the displacement can be 8-bit only, whereas on 68020 and higher 798 and on CPU32 we relax it to SHORT and LONG forms as well using the extended 799 form of the PC+displacement+index operand. Finally, some absolute operands 800 can be relaxed down to 16-bit PC-relative. */ 801 802 #define PCREL1632 7 /* 16-bit or 32-bit PC-relative. */ 803 #define PCINDEX 8 /* PC + displacement + index. */ 804 #define ABSTOPCREL 9 /* Absolute relax down to 16-bit PC-relative. */ 805 806 /* This relaxation is required for branches where there is no long 807 branch and we are in pcrel mode. We generate a bne/beq pair. */ 808 #define BRANCHBWPL 10 /* Branch byte, word or pair of longs 809 */ 810 811 /* Note that calls to frag_var need to specify the maximum expansion 812 needed; this is currently 12 bytes for bne/beq pair. */ 813 #define FRAG_VAR_SIZE 12 814 815 /* The fields are: 816 How far Forward this mode will reach: 817 How far Backward this mode will reach: 818 How many bytes this mode will add to the size of the frag 819 Which mode to go to if the offset won't fit in this one 820 821 Please check tc-m68k.h:md_prepare_relax_scan if changing this table. */ 822 relax_typeS md_relax_table[] = 823 { 824 { 127, -128, 0, TAB (BRANCHBWL, SHORT) }, 825 { 32767, -32768, 2, TAB (BRANCHBWL, LONG) }, 826 { 0, 0, 4, 0 }, 827 { 1, 1, 0, 0 }, 828 829 { 127, -128, 0, TAB (BRABSJUNC, SHORT) }, 830 { 32767, -32768, 2, TAB (BRABSJUNC, LONG) }, 831 { 0, 0, 4, 0 }, 832 { 1, 1, 0, 0 }, 833 834 { 127, -128, 0, TAB (BRABSJCOND, SHORT) }, 835 { 32767, -32768, 2, TAB (BRABSJCOND, LONG) }, 836 { 0, 0, 6, 0 }, 837 { 1, 1, 0, 0 }, 838 839 { 127, -128, 0, TAB (BRANCHBW, SHORT) }, 840 { 0, 0, 2, 0 }, 841 { 1, 1, 0, 0 }, 842 { 1, 1, 0, 0 }, 843 844 { 1, 1, 0, 0 }, /* FBRANCH doesn't come BYTE. */ 845 { 32767, -32768, 2, TAB (FBRANCH, LONG) }, 846 { 0, 0, 4, 0 }, 847 { 1, 1, 0, 0 }, 848 849 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */ 850 { 32767, -32768, 2, TAB (DBCCLBR, LONG) }, 851 { 0, 0, 10, 0 }, 852 { 1, 1, 0, 0 }, 853 854 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */ 855 { 32767, -32768, 2, TAB (DBCCABSJ, LONG) }, 856 { 0, 0, 10, 0 }, 857 { 1, 1, 0, 0 }, 858 859 { 1, 1, 0, 0 }, /* PCREL1632 doesn't come BYTE. */ 860 { 32767, -32768, 2, TAB (PCREL1632, LONG) }, 861 { 0, 0, 6, 0 }, 862 { 1, 1, 0, 0 }, 863 864 { 125, -130, 0, TAB (PCINDEX, SHORT) }, 865 { 32765, -32770, 2, TAB (PCINDEX, LONG) }, 866 { 0, 0, 4, 0 }, 867 { 1, 1, 0, 0 }, 868 869 { 1, 1, 0, 0 }, /* ABSTOPCREL doesn't come BYTE. */ 870 { 32767, -32768, 2, TAB (ABSTOPCREL, LONG) }, 871 { 0, 0, 4, 0 }, 872 { 1, 1, 0, 0 }, 873 874 { 127, -128, 0, TAB (BRANCHBWPL, SHORT) }, 875 { 32767, -32768, 2, TAB (BRANCHBWPL, LONG) }, 876 { 0, 0, 10, 0 }, 877 { 1, 1, 0, 0 }, 878 }; 879 880 /* These are the machine dependent pseudo-ops. These are included so 881 the assembler can work on the output from the SUN C compiler, which 882 generates these. */ 883 884 /* This table describes all the machine specific pseudo-ops the assembler 885 has to support. The fields are: 886 pseudo-op name without dot 887 function to call to execute this pseudo-op 888 Integer arg to pass to the function. */ 889 const pseudo_typeS md_pseudo_table[] = 890 { 891 {"data1", s_data1, 0}, 892 {"data2", s_data2, 0}, 893 {"bss", s_bss, 0}, 894 {"even", s_even, 0}, 895 {"skip", s_space, 0}, 896 {"proc", s_proc, 0}, 897 #if defined (TE_SUN3) || defined (OBJ_ELF) 898 {"align", s_align_bytes, 0}, 899 #endif 900 #ifdef OBJ_ELF 901 {"swbeg", s_ignore, 0}, 902 {"long", m68k_elf_cons, 4}, 903 #endif 904 {"extend", float_cons, 'x'}, 905 {"ldouble", float_cons, 'x'}, 906 907 {"arch", s_m68k_arch, 0}, 908 {"cpu", s_m68k_cpu, 0}, 909 910 /* The following pseudo-ops are supported for MRI compatibility. */ 911 {"chip", s_chip, 0}, 912 {"comline", s_space, 1}, 913 {"fopt", s_fopt, 0}, 914 {"mask2", s_ignore, 0}, 915 {"opt", s_opt, 0}, 916 {"reg", s_reg, 0}, 917 {"restore", s_restore, 0}, 918 {"save", s_save, 0}, 919 920 {"if", s_mri_if, 0}, 921 {"if.b", s_mri_if, 'b'}, 922 {"if.w", s_mri_if, 'w'}, 923 {"if.l", s_mri_if, 'l'}, 924 {"else", s_mri_else, 0}, 925 {"else.s", s_mri_else, 's'}, 926 {"else.l", s_mri_else, 'l'}, 927 {"endi", s_mri_endi, 0}, 928 {"break", s_mri_break, 0}, 929 {"break.s", s_mri_break, 's'}, 930 {"break.l", s_mri_break, 'l'}, 931 {"next", s_mri_next, 0}, 932 {"next.s", s_mri_next, 's'}, 933 {"next.l", s_mri_next, 'l'}, 934 {"for", s_mri_for, 0}, 935 {"for.b", s_mri_for, 'b'}, 936 {"for.w", s_mri_for, 'w'}, 937 {"for.l", s_mri_for, 'l'}, 938 {"endf", s_mri_endf, 0}, 939 {"repeat", s_mri_repeat, 0}, 940 {"until", s_mri_until, 0}, 941 {"until.b", s_mri_until, 'b'}, 942 {"until.w", s_mri_until, 'w'}, 943 {"until.l", s_mri_until, 'l'}, 944 {"while", s_mri_while, 0}, 945 {"while.b", s_mri_while, 'b'}, 946 {"while.w", s_mri_while, 'w'}, 947 {"while.l", s_mri_while, 'l'}, 948 {"endw", s_mri_endw, 0}, 949 950 {0, 0, 0} 951 }; 952 953 /* The mote pseudo ops are put into the opcode table, since they 954 don't start with a . they look like opcodes to gas. */ 955 956 const pseudo_typeS mote_pseudo_table[] = 957 { 958 959 {"dcl", cons, 4}, 960 {"dc", cons, 2}, 961 {"dcw", cons, 2}, 962 {"dcb", cons, 1}, 963 964 {"dsl", s_space, 4}, 965 {"ds", s_space, 2}, 966 {"dsw", s_space, 2}, 967 {"dsb", s_space, 1}, 968 969 {"xdef", s_globl, 0}, 970 #ifdef OBJ_ELF 971 {"align", s_align_bytes, 0}, 972 #else 973 {"align", s_align_ptwo, 0}, 974 #endif 975 #ifdef M68KCOFF 976 {"sect", obj_coff_section, 0}, 977 {"section", obj_coff_section, 0}, 978 #endif 979 {0, 0, 0} 980 }; 981 982 /* Truncate and sign-extend at 32 bits, so that building on a 64-bit host 983 gives identical results to a 32-bit host. */ 984 #define TRUNC(X) ((valueT) (X) & 0xffffffff) 985 #define SEXT(X) ((TRUNC (X) ^ 0x80000000) - 0x80000000) 986 987 #define issbyte(x) ((valueT) SEXT (x) + 0x80 < 0x100) 988 #define isubyte(x) ((valueT) TRUNC (x) < 0x100) 989 #define issword(x) ((valueT) SEXT (x) + 0x8000 < 0x10000) 990 #define isuword(x) ((valueT) TRUNC (x) < 0x10000) 991 992 #define isbyte(x) ((valueT) SEXT (x) + 0xff < 0x1ff) 993 #define isword(x) ((valueT) SEXT (x) + 0xffff < 0x1ffff) 994 #define islong(x) (1) 995 996 static char notend_table[256]; 997 static char alt_notend_table[256]; 998 #define notend(s) \ 999 (! (notend_table[(unsigned char) *s] \ 1000 || (*s == ':' \ 1001 && alt_notend_table[(unsigned char) s[1]]))) 1002 1003 #ifdef OBJ_ELF 1004 1005 /* Return zero if the reference to SYMBOL from within the same segment may 1006 be relaxed. */ 1007 1008 /* On an ELF system, we can't relax an externally visible symbol, 1009 because it may be overridden by a shared library. However, if 1010 TARGET_OS is "elf", then we presume that we are assembling for an 1011 embedded system, in which case we don't have to worry about shared 1012 libraries, and we can relax any external sym. */ 1013 1014 #define relaxable_symbol(symbol) \ 1015 (!((S_IS_EXTERNAL (symbol) && EXTERN_FORCE_RELOC) \ 1016 || S_IS_WEAK (symbol))) 1017 1018 /* Compute the relocation code for a fixup of SIZE bytes, using pc 1019 relative relocation if PCREL is non-zero. PIC says whether a special 1020 pic relocation was requested. */ 1021 1022 static bfd_reloc_code_real_type 1023 get_reloc_code (int size, int pcrel, enum pic_relocation pic) 1024 { 1025 switch (pic) 1026 { 1027 case pic_got_pcrel: 1028 switch (size) 1029 { 1030 case 1: 1031 return BFD_RELOC_8_GOT_PCREL; 1032 case 2: 1033 return BFD_RELOC_16_GOT_PCREL; 1034 case 4: 1035 return BFD_RELOC_32_GOT_PCREL; 1036 } 1037 break; 1038 1039 case pic_got_off: 1040 switch (size) 1041 { 1042 case 1: 1043 return BFD_RELOC_8_GOTOFF; 1044 case 2: 1045 return BFD_RELOC_16_GOTOFF; 1046 case 4: 1047 return BFD_RELOC_32_GOTOFF; 1048 } 1049 break; 1050 1051 case pic_plt_pcrel: 1052 switch (size) 1053 { 1054 case 1: 1055 return BFD_RELOC_8_PLT_PCREL; 1056 case 2: 1057 return BFD_RELOC_16_PLT_PCREL; 1058 case 4: 1059 return BFD_RELOC_32_PLT_PCREL; 1060 } 1061 break; 1062 1063 case pic_plt_off: 1064 switch (size) 1065 { 1066 case 1: 1067 return BFD_RELOC_8_PLTOFF; 1068 case 2: 1069 return BFD_RELOC_16_PLTOFF; 1070 case 4: 1071 return BFD_RELOC_32_PLTOFF; 1072 } 1073 break; 1074 1075 case pic_tls_gd: 1076 switch (size) 1077 { 1078 case 1: 1079 return BFD_RELOC_68K_TLS_GD8; 1080 case 2: 1081 return BFD_RELOC_68K_TLS_GD16; 1082 case 4: 1083 return BFD_RELOC_68K_TLS_GD32; 1084 } 1085 break; 1086 1087 case pic_tls_ldm: 1088 switch (size) 1089 { 1090 case 1: 1091 return BFD_RELOC_68K_TLS_LDM8; 1092 case 2: 1093 return BFD_RELOC_68K_TLS_LDM16; 1094 case 4: 1095 return BFD_RELOC_68K_TLS_LDM32; 1096 } 1097 break; 1098 1099 case pic_tls_ldo: 1100 switch (size) 1101 { 1102 case 1: 1103 return BFD_RELOC_68K_TLS_LDO8; 1104 case 2: 1105 return BFD_RELOC_68K_TLS_LDO16; 1106 case 4: 1107 return BFD_RELOC_68K_TLS_LDO32; 1108 } 1109 break; 1110 1111 case pic_tls_ie: 1112 switch (size) 1113 { 1114 case 1: 1115 return BFD_RELOC_68K_TLS_IE8; 1116 case 2: 1117 return BFD_RELOC_68K_TLS_IE16; 1118 case 4: 1119 return BFD_RELOC_68K_TLS_IE32; 1120 } 1121 break; 1122 1123 case pic_tls_le: 1124 switch (size) 1125 { 1126 case 1: 1127 return BFD_RELOC_68K_TLS_LE8; 1128 case 2: 1129 return BFD_RELOC_68K_TLS_LE16; 1130 case 4: 1131 return BFD_RELOC_68K_TLS_LE32; 1132 } 1133 break; 1134 1135 case pic_none: 1136 if (pcrel) 1137 { 1138 switch (size) 1139 { 1140 case 1: 1141 return BFD_RELOC_8_PCREL; 1142 case 2: 1143 return BFD_RELOC_16_PCREL; 1144 case 4: 1145 return BFD_RELOC_32_PCREL; 1146 } 1147 } 1148 else 1149 { 1150 switch (size) 1151 { 1152 case 1: 1153 return BFD_RELOC_8; 1154 case 2: 1155 return BFD_RELOC_16; 1156 case 4: 1157 return BFD_RELOC_32; 1158 } 1159 } 1160 } 1161 1162 if (pcrel) 1163 { 1164 if (pic == pic_none) 1165 as_bad (_("Can not do %d byte pc-relative relocation"), size); 1166 else 1167 as_bad (_("Can not do %d byte pc-relative pic relocation"), size); 1168 } 1169 else 1170 { 1171 if (pic == pic_none) 1172 as_bad (_("Can not do %d byte relocation"), size); 1173 else 1174 as_bad (_("Can not do %d byte pic relocation"), size); 1175 } 1176 1177 return BFD_RELOC_NONE; 1178 } 1179 1180 /* Here we decide which fixups can be adjusted to make them relative 1181 to the beginning of the section instead of the symbol. Basically 1182 we need to make sure that the dynamic relocations are done 1183 correctly, so in some cases we force the original symbol to be 1184 used. */ 1185 int 1186 tc_m68k_fix_adjustable (fixS *fixP) 1187 { 1188 /* Adjust_reloc_syms doesn't know about the GOT. */ 1189 switch (fixP->fx_r_type) 1190 { 1191 case BFD_RELOC_8_GOT_PCREL: 1192 case BFD_RELOC_16_GOT_PCREL: 1193 case BFD_RELOC_32_GOT_PCREL: 1194 case BFD_RELOC_8_GOTOFF: 1195 case BFD_RELOC_16_GOTOFF: 1196 case BFD_RELOC_32_GOTOFF: 1197 case BFD_RELOC_8_PLT_PCREL: 1198 case BFD_RELOC_16_PLT_PCREL: 1199 case BFD_RELOC_32_PLT_PCREL: 1200 case BFD_RELOC_8_PLTOFF: 1201 case BFD_RELOC_16_PLTOFF: 1202 case BFD_RELOC_32_PLTOFF: 1203 case BFD_RELOC_68K_TLS_GD32: 1204 case BFD_RELOC_68K_TLS_GD16: 1205 case BFD_RELOC_68K_TLS_GD8: 1206 case BFD_RELOC_68K_TLS_LDM32: 1207 case BFD_RELOC_68K_TLS_LDM16: 1208 case BFD_RELOC_68K_TLS_LDM8: 1209 case BFD_RELOC_68K_TLS_LDO32: 1210 case BFD_RELOC_68K_TLS_LDO16: 1211 case BFD_RELOC_68K_TLS_LDO8: 1212 case BFD_RELOC_68K_TLS_IE32: 1213 case BFD_RELOC_68K_TLS_IE16: 1214 case BFD_RELOC_68K_TLS_IE8: 1215 case BFD_RELOC_68K_TLS_LE32: 1216 case BFD_RELOC_68K_TLS_LE16: 1217 case BFD_RELOC_68K_TLS_LE8: 1218 return 0; 1219 1220 case BFD_RELOC_VTABLE_INHERIT: 1221 case BFD_RELOC_VTABLE_ENTRY: 1222 return 0; 1223 1224 default: 1225 return 1; 1226 } 1227 } 1228 1229 #else /* !OBJ_ELF */ 1230 1231 #define get_reloc_code(SIZE,PCREL,OTHER) NO_RELOC 1232 1233 /* PR gas/3041 Weak symbols are not relaxable 1234 because they must be treated as extern. */ 1235 #define relaxable_symbol(symbol) (!(S_IS_WEAK (symbol))) 1236 1237 #endif /* OBJ_ELF */ 1238 1239 arelent * 1240 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) 1241 { 1242 arelent *reloc; 1243 bfd_reloc_code_real_type code; 1244 1245 /* If the tcbit is set, then this was a fixup of a negative value 1246 that was never resolved. We do not have a reloc to handle this, 1247 so just return. We assume that other code will have detected this 1248 situation and produced a helpful error message, so we just tell the 1249 user that the reloc cannot be produced. */ 1250 if (fixp->fx_tcbit) 1251 { 1252 if (fixp->fx_addsy) 1253 as_bad_where (fixp->fx_file, fixp->fx_line, 1254 _("Unable to produce reloc against symbol '%s'"), 1255 S_GET_NAME (fixp->fx_addsy)); 1256 return NULL; 1257 } 1258 1259 if (fixp->fx_r_type != BFD_RELOC_NONE) 1260 { 1261 code = fixp->fx_r_type; 1262 1263 /* Since DIFF_EXPR_OK is defined in tc-m68k.h, it is possible 1264 that fixup_segment converted a non-PC relative reloc into a 1265 PC relative reloc. In such a case, we need to convert the 1266 reloc code. */ 1267 if (fixp->fx_pcrel) 1268 { 1269 switch (code) 1270 { 1271 case BFD_RELOC_8: 1272 code = BFD_RELOC_8_PCREL; 1273 break; 1274 case BFD_RELOC_16: 1275 code = BFD_RELOC_16_PCREL; 1276 break; 1277 case BFD_RELOC_32: 1278 code = BFD_RELOC_32_PCREL; 1279 break; 1280 case BFD_RELOC_8_PCREL: 1281 case BFD_RELOC_16_PCREL: 1282 case BFD_RELOC_32_PCREL: 1283 case BFD_RELOC_8_GOT_PCREL: 1284 case BFD_RELOC_16_GOT_PCREL: 1285 case BFD_RELOC_32_GOT_PCREL: 1286 case BFD_RELOC_8_GOTOFF: 1287 case BFD_RELOC_16_GOTOFF: 1288 case BFD_RELOC_32_GOTOFF: 1289 case BFD_RELOC_8_PLT_PCREL: 1290 case BFD_RELOC_16_PLT_PCREL: 1291 case BFD_RELOC_32_PLT_PCREL: 1292 case BFD_RELOC_8_PLTOFF: 1293 case BFD_RELOC_16_PLTOFF: 1294 case BFD_RELOC_32_PLTOFF: 1295 case BFD_RELOC_68K_TLS_GD32: 1296 case BFD_RELOC_68K_TLS_GD16: 1297 case BFD_RELOC_68K_TLS_GD8: 1298 case BFD_RELOC_68K_TLS_LDM32: 1299 case BFD_RELOC_68K_TLS_LDM16: 1300 case BFD_RELOC_68K_TLS_LDM8: 1301 case BFD_RELOC_68K_TLS_LDO32: 1302 case BFD_RELOC_68K_TLS_LDO16: 1303 case BFD_RELOC_68K_TLS_LDO8: 1304 case BFD_RELOC_68K_TLS_IE32: 1305 case BFD_RELOC_68K_TLS_IE16: 1306 case BFD_RELOC_68K_TLS_IE8: 1307 case BFD_RELOC_68K_TLS_LE32: 1308 case BFD_RELOC_68K_TLS_LE16: 1309 case BFD_RELOC_68K_TLS_LE8: 1310 break; 1311 default: 1312 as_bad_where (fixp->fx_file, fixp->fx_line, 1313 _("Cannot make %s relocation PC relative"), 1314 bfd_get_reloc_code_name (code)); 1315 } 1316 } 1317 } 1318 else 1319 { 1320 #define F(SZ,PCREL) (((SZ) << 1) + (PCREL)) 1321 switch (F (fixp->fx_size, fixp->fx_pcrel)) 1322 { 1323 #define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break 1324 MAP (1, 0, BFD_RELOC_8); 1325 MAP (2, 0, BFD_RELOC_16); 1326 MAP (4, 0, BFD_RELOC_32); 1327 MAP (1, 1, BFD_RELOC_8_PCREL); 1328 MAP (2, 1, BFD_RELOC_16_PCREL); 1329 MAP (4, 1, BFD_RELOC_32_PCREL); 1330 default: 1331 abort (); 1332 } 1333 } 1334 #undef F 1335 #undef MAP 1336 1337 reloc = XNEW (arelent); 1338 reloc->sym_ptr_ptr = XNEW (asymbol *); 1339 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); 1340 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; 1341 #ifndef OBJ_ELF 1342 if (OUTPUT_FLAVOR == bfd_target_aout_flavour 1343 && fixp->fx_addsy 1344 && S_IS_WEAK (fixp->fx_addsy) 1345 && ! bfd_is_und_section (S_GET_SEGMENT (fixp->fx_addsy))) 1346 { 1347 /* PR gas/3041 References to weak symbols must be treated as extern 1348 in order to be overridable by the linker, even if they are defined 1349 in the same object file. So the original addend must be written 1350 "as is" into the output section without further processing. 1351 The addend value must be hacked here in order to force 1352 bfd_install_relocation() to write the original value into the 1353 output section. 1354 1) MD_APPLY_SYM_VALUE() is set to 1 for m68k/a.out, so the symbol 1355 value has already been added to the addend in fixup_segment(). We 1356 have to remove it. 1357 2) bfd_install_relocation() will incorrectly treat this symbol as 1358 resolved, so it will write the symbol value plus its addend and 1359 section VMA. As a workaround we can tweak the addend value here in 1360 order to get the original value in the section after the call to 1361 bfd_install_relocation(). */ 1362 reloc->addend = fixp->fx_addnumber 1363 /* Fix because of MD_APPLY_SYM_VALUE() */ 1364 - S_GET_VALUE (fixp->fx_addsy) 1365 /* Fix for bfd_install_relocation() */ 1366 - (S_GET_VALUE (fixp->fx_addsy) 1367 + S_GET_SEGMENT (fixp->fx_addsy)->vma); 1368 } 1369 else if (fixp->fx_pcrel) 1370 reloc->addend = fixp->fx_addnumber; 1371 else 1372 reloc->addend = 0; 1373 #else 1374 if (!fixp->fx_pcrel) 1375 reloc->addend = fixp->fx_addnumber; 1376 else 1377 reloc->addend = (section->vma 1378 + fixp->fx_pcrel_adjust 1379 + fixp->fx_addnumber 1380 + md_pcrel_from (fixp)); 1381 #endif 1382 1383 reloc->howto = bfd_reloc_type_lookup (stdoutput, code); 1384 gas_assert (reloc->howto != 0); 1385 1386 return reloc; 1387 } 1388 1389 /* Handle of the OPCODE hash table. NULL means any use before 1390 m68k_ip_begin() will crash. */ 1391 static struct hash_control *op_hash; 1392 1393 /* Assemble an m68k instruction. */ 1395 1396 static void 1397 m68k_ip (char *instring) 1398 { 1399 char *p; 1400 struct m68k_op *opP; 1401 const struct m68k_incant *opcode; 1402 const char *s; 1403 int tmpreg = 0, baseo = 0, outro = 0, nextword; 1404 char *pdot, *pdotmove; 1405 enum m68k_size siz1, siz2; 1406 char c; 1407 int losing; 1408 int opsfound; 1409 struct m68k_op operands_backup[6]; 1410 LITTLENUM_TYPE words[6]; 1411 LITTLENUM_TYPE *wordp; 1412 unsigned long ok_arch = 0; 1413 1414 if (*instring == ' ') 1415 instring++; /* Skip leading whitespace. */ 1416 1417 /* Scan up to end of operation-code, which MUST end in end-of-string 1418 or exactly 1 space. */ 1419 pdot = 0; 1420 for (p = instring; *p != '\0'; p++) 1421 { 1422 if (*p == ' ') 1423 break; 1424 if (*p == '.') 1425 pdot = p; 1426 } 1427 1428 if (p == instring) 1429 { 1430 the_ins.error = _("No operator"); 1431 return; 1432 } 1433 1434 /* p now points to the end of the opcode name, probably whitespace. 1435 Make sure the name is null terminated by clobbering the 1436 whitespace, look it up in the hash table, then fix it back. 1437 Remove a dot, first, since the opcode tables have none. */ 1438 if (pdot != NULL) 1439 { 1440 for (pdotmove = pdot; pdotmove < p; pdotmove++) 1441 *pdotmove = pdotmove[1]; 1442 p--; 1443 } 1444 1445 c = *p; 1446 *p = '\0'; 1447 opcode = (const struct m68k_incant *) hash_find (op_hash, instring); 1448 *p = c; 1449 1450 if (pdot != NULL) 1451 { 1452 for (pdotmove = p; pdotmove > pdot; pdotmove--) 1453 *pdotmove = pdotmove[-1]; 1454 *pdot = '.'; 1455 ++p; 1456 } 1457 1458 if (opcode == NULL) 1459 { 1460 the_ins.error = _("Unknown operator"); 1461 return; 1462 } 1463 1464 /* Found a legitimate opcode, start matching operands. */ 1465 while (*p == ' ') 1466 ++p; 1467 1468 if (opcode->m_operands == 0) 1469 { 1470 char *old = input_line_pointer; 1471 *old = '\n'; 1472 input_line_pointer = p; 1473 /* Ahh - it's a motorola style psuedo op. */ 1474 mote_pseudo_table[opcode->m_opnum].poc_handler 1475 (mote_pseudo_table[opcode->m_opnum].poc_val); 1476 input_line_pointer = old; 1477 *old = 0; 1478 1479 return; 1480 } 1481 1482 if (flag_mri && opcode->m_opnum == 0) 1483 { 1484 /* In MRI mode, random garbage is allowed after an instruction 1485 which accepts no operands. */ 1486 the_ins.args = opcode->m_operands; 1487 the_ins.numargs = opcode->m_opnum; 1488 the_ins.numo = opcode->m_codenum; 1489 the_ins.opcode[0] = getone (opcode); 1490 the_ins.opcode[1] = gettwo (opcode); 1491 return; 1492 } 1493 1494 for (opP = &the_ins.operands[0]; *p; opP++) 1495 { 1496 p = crack_operand (p, opP); 1497 1498 if (opP->error) 1499 { 1500 the_ins.error = opP->error; 1501 return; 1502 } 1503 } 1504 1505 opsfound = opP - &the_ins.operands[0]; 1506 1507 /* This ugly hack is to support the floating pt opcodes in their 1508 standard form. Essentially, we fake a first enty of type COP#1 */ 1509 if (opcode->m_operands[0] == 'I') 1510 { 1511 int n; 1512 1513 for (n = opsfound; n > 0; --n) 1514 the_ins.operands[n] = the_ins.operands[n - 1]; 1515 1516 memset (&the_ins.operands[0], '\0', sizeof (the_ins.operands[0])); 1517 the_ins.operands[0].mode = CONTROL; 1518 the_ins.operands[0].reg = m68k_float_copnum; 1519 opsfound++; 1520 } 1521 1522 /* We've got the operands. Find an opcode that'll accept them. */ 1523 for (losing = 0;;) 1524 { 1525 /* If we didn't get the right number of ops, or we have no 1526 common model with this pattern then reject this pattern. */ 1527 1528 ok_arch |= opcode->m_arch; 1529 if (opsfound != opcode->m_opnum 1530 || ((opcode->m_arch & current_architecture) == 0)) 1531 ++losing; 1532 else 1533 { 1534 int i; 1535 1536 /* Make a copy of the operands of this insn so that 1537 we can modify them safely, should we want to. */ 1538 gas_assert (opsfound <= (int) ARRAY_SIZE (operands_backup)); 1539 for (i = 0; i < opsfound; i++) 1540 operands_backup[i] = the_ins.operands[i]; 1541 1542 for (s = opcode->m_operands, opP = &operands_backup[0]; 1543 *s && !losing; 1544 s += 2, opP++) 1545 { 1546 /* Warning: this switch is huge! */ 1547 /* I've tried to organize the cases into this order: 1548 non-alpha first, then alpha by letter. Lower-case 1549 goes directly before uppercase counterpart. */ 1550 /* Code with multiple case ...: gets sorted by the lowest 1551 case ... it belongs to. I hope this makes sense. */ 1552 switch (*s) 1553 { 1554 case '!': 1555 switch (opP->mode) 1556 { 1557 case IMMED: 1558 case DREG: 1559 case AREG: 1560 case FPREG: 1561 case CONTROL: 1562 case AINC: 1563 case ADEC: 1564 case REGLST: 1565 losing++; 1566 break; 1567 default: 1568 break; 1569 } 1570 break; 1571 1572 case '<': 1573 switch (opP->mode) 1574 { 1575 case DREG: 1576 case AREG: 1577 case FPREG: 1578 case CONTROL: 1579 case IMMED: 1580 case ADEC: 1581 case REGLST: 1582 losing++; 1583 break; 1584 default: 1585 break; 1586 } 1587 break; 1588 1589 case '>': 1590 switch (opP->mode) 1591 { 1592 case DREG: 1593 case AREG: 1594 case FPREG: 1595 case CONTROL: 1596 case IMMED: 1597 case AINC: 1598 case REGLST: 1599 losing++; 1600 break; 1601 case ABSL: 1602 break; 1603 default: 1604 if (opP->reg == PC 1605 || opP->reg == ZPC) 1606 losing++; 1607 break; 1608 } 1609 break; 1610 1611 case 'm': 1612 switch (opP->mode) 1613 { 1614 case DREG: 1615 case AREG: 1616 case AINDR: 1617 case AINC: 1618 case ADEC: 1619 break; 1620 default: 1621 losing++; 1622 } 1623 break; 1624 1625 case 'n': 1626 switch (opP->mode) 1627 { 1628 case DISP: 1629 break; 1630 default: 1631 losing++; 1632 } 1633 break; 1634 1635 case 'o': 1636 switch (opP->mode) 1637 { 1638 case BASE: 1639 case ABSL: 1640 case IMMED: 1641 break; 1642 default: 1643 losing++; 1644 } 1645 break; 1646 1647 case 'p': 1648 switch (opP->mode) 1649 { 1650 case DREG: 1651 case AREG: 1652 case AINDR: 1653 case AINC: 1654 case ADEC: 1655 break; 1656 case DISP: 1657 if (opP->reg == PC || opP->reg == ZPC) 1658 losing++; 1659 break; 1660 default: 1661 losing++; 1662 } 1663 break; 1664 1665 case 'q': 1666 switch (opP->mode) 1667 { 1668 case DREG: 1669 case AINDR: 1670 case AINC: 1671 case ADEC: 1672 break; 1673 case DISP: 1674 if (opP->reg == PC || opP->reg == ZPC) 1675 losing++; 1676 break; 1677 default: 1678 losing++; 1679 break; 1680 } 1681 break; 1682 1683 case 'v': 1684 switch (opP->mode) 1685 { 1686 case DREG: 1687 case AINDR: 1688 case AINC: 1689 case ADEC: 1690 case ABSL: 1691 break; 1692 case DISP: 1693 if (opP->reg == PC || opP->reg == ZPC) 1694 losing++; 1695 break; 1696 default: 1697 losing++; 1698 break; 1699 } 1700 break; 1701 1702 case '#': 1703 if (opP->mode != IMMED) 1704 losing++; 1705 else if (s[1] == 'b' 1706 && ! isvar (&opP->disp) 1707 && (opP->disp.exp.X_op != O_constant 1708 || ! isbyte (opP->disp.exp.X_add_number))) 1709 losing++; 1710 else if (s[1] == 'B' 1711 && ! isvar (&opP->disp) 1712 && (opP->disp.exp.X_op != O_constant 1713 || ! issbyte (opP->disp.exp.X_add_number))) 1714 losing++; 1715 else if (s[1] == 'w' 1716 && ! isvar (&opP->disp) 1717 && (opP->disp.exp.X_op != O_constant 1718 || ! isword (opP->disp.exp.X_add_number))) 1719 losing++; 1720 else if (s[1] == 'W' 1721 && ! isvar (&opP->disp) 1722 && (opP->disp.exp.X_op != O_constant 1723 || ! issword (opP->disp.exp.X_add_number))) 1724 losing++; 1725 break; 1726 1727 case '^': 1728 case 'T': 1729 if (opP->mode != IMMED) 1730 losing++; 1731 break; 1732 1733 case '$': 1734 if (opP->mode == AREG 1735 || opP->mode == CONTROL 1736 || opP->mode == FPREG 1737 || opP->mode == IMMED 1738 || opP->mode == REGLST 1739 || (opP->mode != ABSL 1740 && (opP->reg == PC 1741 || opP->reg == ZPC))) 1742 losing++; 1743 break; 1744 1745 case '%': 1746 if (opP->mode == CONTROL 1747 || opP->mode == FPREG 1748 || opP->mode == REGLST 1749 || opP->mode == IMMED 1750 || (opP->mode != ABSL 1751 && (opP->reg == PC 1752 || opP->reg == ZPC))) 1753 losing++; 1754 break; 1755 1756 case '&': 1757 switch (opP->mode) 1758 { 1759 case DREG: 1760 case AREG: 1761 case FPREG: 1762 case CONTROL: 1763 case IMMED: 1764 case AINC: 1765 case ADEC: 1766 case REGLST: 1767 losing++; 1768 break; 1769 case ABSL: 1770 break; 1771 default: 1772 if (opP->reg == PC 1773 || opP->reg == ZPC) 1774 losing++; 1775 break; 1776 } 1777 break; 1778 1779 case '*': 1780 if (opP->mode == CONTROL 1781 || opP->mode == FPREG 1782 || opP->mode == REGLST) 1783 losing++; 1784 break; 1785 1786 case '+': 1787 if (opP->mode != AINC) 1788 losing++; 1789 break; 1790 1791 case '-': 1792 if (opP->mode != ADEC) 1793 losing++; 1794 break; 1795 1796 case '/': 1797 switch (opP->mode) 1798 { 1799 case AREG: 1800 case CONTROL: 1801 case FPREG: 1802 case AINC: 1803 case ADEC: 1804 case IMMED: 1805 case REGLST: 1806 losing++; 1807 break; 1808 default: 1809 break; 1810 } 1811 break; 1812 1813 case ';': 1814 switch (opP->mode) 1815 { 1816 case AREG: 1817 case CONTROL: 1818 case FPREG: 1819 case REGLST: 1820 losing++; 1821 break; 1822 default: 1823 break; 1824 } 1825 break; 1826 1827 case '?': 1828 switch (opP->mode) 1829 { 1830 case AREG: 1831 case CONTROL: 1832 case FPREG: 1833 case AINC: 1834 case ADEC: 1835 case IMMED: 1836 case REGLST: 1837 losing++; 1838 break; 1839 case ABSL: 1840 break; 1841 default: 1842 if (opP->reg == PC || opP->reg == ZPC) 1843 losing++; 1844 break; 1845 } 1846 break; 1847 1848 case '@': 1849 switch (opP->mode) 1850 { 1851 case AREG: 1852 case CONTROL: 1853 case FPREG: 1854 case IMMED: 1855 case REGLST: 1856 losing++; 1857 break; 1858 default: 1859 break; 1860 } 1861 break; 1862 1863 case '~': /* For now! (JF FOO is this right?) */ 1864 switch (opP->mode) 1865 { 1866 case DREG: 1867 case AREG: 1868 case CONTROL: 1869 case FPREG: 1870 case IMMED: 1871 case REGLST: 1872 losing++; 1873 break; 1874 case ABSL: 1875 break; 1876 default: 1877 if (opP->reg == PC 1878 || opP->reg == ZPC) 1879 losing++; 1880 break; 1881 } 1882 break; 1883 1884 case '3': 1885 if (opP->mode != CONTROL 1886 || (opP->reg != TT0 && opP->reg != TT1)) 1887 losing++; 1888 break; 1889 1890 case 'A': 1891 if (opP->mode != AREG) 1892 losing++; 1893 break; 1894 1895 case 'a': 1896 if (opP->mode != AINDR) 1897 ++losing; 1898 break; 1899 1900 case '4': 1901 if (opP->mode != AINDR && opP->mode != AINC && opP->mode != ADEC 1902 && (opP->mode != DISP 1903 || opP->reg < ADDR0 1904 || opP->reg > ADDR7)) 1905 ++losing; 1906 break; 1907 1908 case 'B': /* FOO */ 1909 if (opP->mode != ABSL 1910 || (flag_long_jumps 1911 && strncmp (instring, "jbsr", 4) == 0)) 1912 losing++; 1913 break; 1914 1915 case 'b': 1916 switch (opP->mode) 1917 { 1918 case IMMED: 1919 case ABSL: 1920 case AREG: 1921 case FPREG: 1922 case CONTROL: 1923 case POST: 1924 case PRE: 1925 case REGLST: 1926 losing++; 1927 break; 1928 default: 1929 break; 1930 } 1931 break; 1932 1933 case 'C': 1934 if (opP->mode != CONTROL || opP->reg != CCR) 1935 losing++; 1936 break; 1937 1938 case 'd': 1939 if (opP->mode != DISP 1940 || opP->reg < ADDR0 1941 || opP->reg > ADDR7) 1942 losing++; 1943 break; 1944 1945 case 'D': 1946 if (opP->mode != DREG) 1947 losing++; 1948 break; 1949 1950 case 'E': 1951 if (opP->reg != ACC) 1952 losing++; 1953 break; 1954 1955 case 'e': 1956 if (opP->reg != ACC && opP->reg != ACC1 1957 && opP->reg != ACC2 && opP->reg != ACC3) 1958 losing++; 1959 break; 1960 1961 case 'F': 1962 if (opP->mode != FPREG) 1963 losing++; 1964 break; 1965 1966 case 'G': 1967 if (opP->reg != MACSR) 1968 losing++; 1969 break; 1970 1971 case 'g': 1972 if (opP->reg != ACCEXT01 && opP->reg != ACCEXT23) 1973 losing++; 1974 break; 1975 1976 case 'H': 1977 if (opP->reg != MASK) 1978 losing++; 1979 break; 1980 1981 case 'I': 1982 if (opP->mode != CONTROL 1983 || opP->reg < COP0 1984 || opP->reg > COP7) 1985 losing++; 1986 break; 1987 1988 case 'i': 1989 if (opP->mode != LSH && opP->mode != RSH) 1990 losing++; 1991 break; 1992 1993 case 'J': 1994 if (opP->mode != CONTROL 1995 || opP->reg < USP 1996 || opP->reg > last_movec_reg 1997 || !control_regs) 1998 losing++; 1999 else 2000 { 2001 const enum m68k_register *rp; 2002 2003 for (rp = control_regs; *rp; rp++) 2004 { 2005 if (*rp == opP->reg) 2006 break; 2007 /* In most CPUs RAMBAR refers to control reg 2008 c05 (RAMBAR1), but a few CPUs have it 2009 refer to c04 (RAMBAR0). */ 2010 else if (*rp == RAMBAR_ALT && opP->reg == RAMBAR) 2011 { 2012 opP->reg = RAMBAR_ALT; 2013 break; 2014 } 2015 } 2016 if (*rp == 0) 2017 losing++; 2018 } 2019 break; 2020 2021 case 'k': 2022 if (opP->mode != IMMED) 2023 losing++; 2024 break; 2025 2026 case 'l': 2027 case 'L': 2028 if (opP->mode == DREG 2029 || opP->mode == AREG 2030 || opP->mode == FPREG) 2031 { 2032 if (s[1] == '8') 2033 losing++; 2034 else 2035 { 2036 switch (opP->mode) 2037 { 2038 case DREG: 2039 opP->mask = 1 << (opP->reg - DATA0); 2040 break; 2041 case AREG: 2042 opP->mask = 1 << (opP->reg - ADDR0 + 8); 2043 break; 2044 case FPREG: 2045 opP->mask = 1 << (opP->reg - FP0 + 16); 2046 break; 2047 default: 2048 abort (); 2049 } 2050 opP->mode = REGLST; 2051 } 2052 } 2053 else if (opP->mode == CONTROL) 2054 { 2055 if (s[1] != '8') 2056 losing++; 2057 else 2058 { 2059 switch (opP->reg) 2060 { 2061 case FPI: 2062 opP->mask = 1 << 24; 2063 break; 2064 case FPS: 2065 opP->mask = 1 << 25; 2066 break; 2067 case FPC: 2068 opP->mask = 1 << 26; 2069 break; 2070 default: 2071 losing++; 2072 break; 2073 } 2074 opP->mode = REGLST; 2075 } 2076 } 2077 else if (opP->mode != REGLST) 2078 losing++; 2079 else if (s[1] == '8' && (opP->mask & 0x0ffffff) != 0) 2080 losing++; 2081 else if (s[1] == '3' && (opP->mask & 0x7000000) != 0) 2082 losing++; 2083 break; 2084 2085 case 'M': 2086 if (opP->mode != IMMED) 2087 losing++; 2088 else if (opP->disp.exp.X_op != O_constant 2089 || ! issbyte (opP->disp.exp.X_add_number)) 2090 losing++; 2091 else if (! m68k_quick 2092 && instring[3] != 'q' 2093 && instring[4] != 'q') 2094 losing++; 2095 break; 2096 2097 case 'O': 2098 if (opP->mode != DREG 2099 && opP->mode != IMMED 2100 && opP->mode != ABSL) 2101 losing++; 2102 break; 2103 2104 case 'Q': 2105 if (opP->mode != IMMED) 2106 losing++; 2107 else if (opP->disp.exp.X_op != O_constant 2108 || TRUNC (opP->disp.exp.X_add_number) - 1 > 7) 2109 losing++; 2110 else if (! m68k_quick 2111 && (strncmp (instring, "add", 3) == 0 2112 || strncmp (instring, "sub", 3) == 0) 2113 && instring[3] != 'q') 2114 losing++; 2115 break; 2116 2117 case 'R': 2118 if (opP->mode != DREG && opP->mode != AREG) 2119 losing++; 2120 break; 2121 2122 case 'r': 2123 if (opP->mode != AINDR 2124 && (opP->mode != BASE 2125 || (opP->reg != 0 2126 && opP->reg != ZADDR0) 2127 || opP->disp.exp.X_op != O_absent 2128 || ((opP->index.reg < DATA0 2129 || opP->index.reg > DATA7) 2130 && (opP->index.reg < ADDR0 2131 || opP->index.reg > ADDR7)) 2132 || opP->index.size != SIZE_UNSPEC 2133 || opP->index.scale != 1)) 2134 losing++; 2135 break; 2136 2137 case 's': 2138 if (opP->mode != CONTROL 2139 || ! (opP->reg == FPI 2140 || opP->reg == FPS 2141 || opP->reg == FPC)) 2142 losing++; 2143 break; 2144 2145 case 'S': 2146 if (opP->mode != CONTROL || opP->reg != SR) 2147 losing++; 2148 break; 2149 2150 case 't': 2151 if (opP->mode != IMMED) 2152 losing++; 2153 else if (opP->disp.exp.X_op != O_constant 2154 || TRUNC (opP->disp.exp.X_add_number) > 7) 2155 losing++; 2156 break; 2157 2158 case 'U': 2159 if (opP->mode != CONTROL || opP->reg != USP) 2160 losing++; 2161 break; 2162 2163 case 'x': 2164 if (opP->mode != IMMED) 2165 losing++; 2166 else if (opP->disp.exp.X_op != O_constant 2167 || (TRUNC (opP->disp.exp.X_add_number) != 0xffffffff 2168 && TRUNC (opP->disp.exp.X_add_number) - 1 > 6)) 2169 losing++; 2170 break; 2171 2172 case 'j': 2173 if (opP->mode != IMMED) 2174 losing++; 2175 else if (opP->disp.exp.X_op != O_constant 2176 || TRUNC (opP->disp.exp.X_add_number) - 1 > 7) 2177 losing++; 2178 break; 2179 2180 case 'K': 2181 if (opP->mode != IMMED) 2182 losing++; 2183 else if (opP->disp.exp.X_op != O_constant 2184 || TRUNC (opP->disp.exp.X_add_number) > 511) 2185 losing++; 2186 break; 2187 2188 /* JF these are out of order. We could put them 2189 in order if we were willing to put up with 2190 bunches of #ifdef m68851s in the code. 2191 2192 Don't forget that you need these operands 2193 to use 68030 MMU instructions. */ 2194 #ifndef NO_68851 2195 /* Memory addressing mode used by pflushr. */ 2196 case '|': 2197 if (opP->mode == CONTROL 2198 || opP->mode == FPREG 2199 || opP->mode == DREG 2200 || opP->mode == AREG 2201 || opP->mode == REGLST) 2202 losing++; 2203 /* We should accept immediate operands, but they 2204 supposedly have to be quad word, and we don't 2205 handle that. I would like to see what a Motorola 2206 assembler does before doing something here. */ 2207 if (opP->mode == IMMED) 2208 losing++; 2209 break; 2210 2211 case 'f': 2212 if (opP->mode != CONTROL 2213 || (opP->reg != SFC && opP->reg != DFC)) 2214 losing++; 2215 break; 2216 2217 case '0': 2218 if (opP->mode != CONTROL || opP->reg != TC) 2219 losing++; 2220 break; 2221 2222 case '1': 2223 if (opP->mode != CONTROL || opP->reg != AC) 2224 losing++; 2225 break; 2226 2227 case '2': 2228 if (opP->mode != CONTROL 2229 || (opP->reg != CAL 2230 && opP->reg != VAL 2231 && opP->reg != SCC)) 2232 losing++; 2233 break; 2234 2235 case 'V': 2236 if (opP->mode != CONTROL 2237 || opP->reg != VAL) 2238 losing++; 2239 break; 2240 2241 case 'W': 2242 if (opP->mode != CONTROL 2243 || (opP->reg != DRP 2244 && opP->reg != SRP 2245 && opP->reg != CRP)) 2246 losing++; 2247 break; 2248 2249 case 'w': 2250 switch (opP->mode) 2251 { 2252 case IMMED: 2253 case ABSL: 2254 case AREG: 2255 case DREG: 2256 case FPREG: 2257 case CONTROL: 2258 case POST: 2259 case PRE: 2260 case REGLST: 2261 losing++; 2262 break; 2263 default: 2264 break; 2265 } 2266 break; 2267 2268 case 'X': 2269 if (opP->mode != CONTROL 2270 || (!(opP->reg >= BAD && opP->reg <= BAD + 7) 2271 && !(opP->reg >= BAC && opP->reg <= BAC + 7))) 2272 losing++; 2273 break; 2274 2275 case 'Y': 2276 if (opP->mode != CONTROL || opP->reg != PSR) 2277 losing++; 2278 break; 2279 2280 case 'Z': 2281 if (opP->mode != CONTROL || opP->reg != PCSR) 2282 losing++; 2283 break; 2284 #endif 2285 case 'c': 2286 if (opP->mode != CONTROL 2287 || (opP->reg != NC 2288 && opP->reg != IC 2289 && opP->reg != DC 2290 && opP->reg != BC)) 2291 losing++; 2292 break; 2293 2294 case '_': 2295 if (opP->mode != ABSL) 2296 ++losing; 2297 break; 2298 2299 case 'u': 2300 if (opP->reg < DATA0L || opP->reg > ADDR7U) 2301 losing++; 2302 /* FIXME: kludge instead of fixing parser: 2303 upper/lower registers are *not* CONTROL 2304 registers, but ordinary ones. */ 2305 if ((opP->reg >= DATA0L && opP->reg <= DATA7L) 2306 || (opP->reg >= DATA0U && opP->reg <= DATA7U)) 2307 opP->mode = DREG; 2308 else 2309 opP->mode = AREG; 2310 break; 2311 2312 case 'y': 2313 if (!(opP->mode == AINDR 2314 || (opP->mode == DISP 2315 && !(opP->reg == PC || opP->reg == ZPC)))) 2316 losing++; 2317 break; 2318 2319 case 'z': 2320 if (!(opP->mode == AINDR || opP->mode == DISP)) 2321 losing++; 2322 break; 2323 2324 default: 2325 abort (); 2326 } 2327 2328 if (losing) 2329 break; 2330 } 2331 2332 /* Since we have found the correct instruction, copy 2333 in the modifications that we may have made. */ 2334 if (!losing) 2335 for (i = 0; i < opsfound; i++) 2336 the_ins.operands[i] = operands_backup[i]; 2337 } 2338 2339 if (!losing) 2340 break; 2341 2342 opcode = opcode->m_next; 2343 2344 if (!opcode) 2345 { 2346 if (ok_arch 2347 && !(ok_arch & current_architecture)) 2348 { 2349 const struct m68k_cpu *cpu; 2350 int any = 0; 2351 size_t space = 400; 2352 char *buf = XNEWVEC (char, space + 1); 2353 size_t len; 2354 int paren = 1; 2355 2356 the_ins.error = buf; 2357 /* Make sure there's a NUL at the end of the buffer -- strncpy 2358 won't write one when it runs out of buffer. */ 2359 buf[space] = 0; 2360 #define APPEND(STRING) \ 2361 (strncpy (buf, STRING, space), len = strlen (buf), buf += len, space -= len) 2362 2363 APPEND (_("invalid instruction for this architecture; needs ")); 2364 switch (ok_arch) 2365 { 2366 case mcfisa_a: 2367 APPEND ("ColdFire ISA_A"); 2368 break; 2369 case mcfhwdiv: 2370 APPEND ("ColdFire "); 2371 APPEND (_("hardware divide")); 2372 break; 2373 case mcfisa_aa: 2374 APPEND ("ColdFire ISA_A+"); 2375 break; 2376 case mcfisa_b: 2377 APPEND ("ColdFire ISA_B"); 2378 break; 2379 case mcfisa_c: 2380 APPEND ("ColdFire ISA_C"); 2381 break; 2382 case cfloat: 2383 APPEND ("ColdFire fpu"); 2384 break; 2385 case mfloat: 2386 APPEND ("M68K fpu"); 2387 break; 2388 case mmmu: 2389 APPEND ("M68K mmu"); 2390 break; 2391 case m68020up: 2392 APPEND ("68020 "); 2393 APPEND (_("or higher")); 2394 break; 2395 case m68000up: 2396 APPEND ("68000 "); 2397 APPEND (_("or higher")); 2398 break; 2399 case m68010up: 2400 APPEND ("68010 "); 2401 APPEND (_("or higher")); 2402 break; 2403 default: 2404 paren = 0; 2405 } 2406 if (paren) 2407 APPEND (" ("); 2408 2409 for (cpu = m68k_cpus; cpu->name; cpu++) 2410 if (!cpu->alias && (cpu->arch & ok_arch)) 2411 { 2412 const struct m68k_cpu *alias; 2413 int seen_master = 0; 2414 2415 if (any) 2416 APPEND (", "); 2417 any = 0; 2418 APPEND (cpu->name); 2419 for (alias = cpu; alias != m68k_cpus; alias--) 2420 if (alias[-1].alias >= 0) 2421 break; 2422 for (; !seen_master || alias->alias > 0; alias++) 2423 { 2424 if (!alias->alias) 2425 seen_master = 1; 2426 else 2427 { 2428 if (any) 2429 APPEND (", "); 2430 else 2431 APPEND (" ["); 2432 APPEND (alias->name); 2433 any = 1; 2434 } 2435 } 2436 if (any) 2437 APPEND ("]"); 2438 any = 1; 2439 } 2440 if (paren) 2441 APPEND (")"); 2442 #undef APPEND 2443 if (!space) 2444 { 2445 /* We ran out of space, so replace the end of the list 2446 with ellipsis. */ 2447 buf -= 4; 2448 while (*buf != ' ') 2449 buf--; 2450 strcpy (buf, " ..."); 2451 } 2452 } 2453 else 2454 the_ins.error = _("operands mismatch"); 2455 return; 2456 } 2457 2458 losing = 0; 2459 } 2460 2461 /* Now assemble it. */ 2462 the_ins.args = opcode->m_operands; 2463 the_ins.numargs = opcode->m_opnum; 2464 the_ins.numo = opcode->m_codenum; 2465 the_ins.opcode[0] = getone (opcode); 2466 the_ins.opcode[1] = gettwo (opcode); 2467 2468 for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++) 2469 { 2470 int have_disp = 0; 2471 int use_pl = 0; 2472 2473 /* This switch is a doozy. 2474 Watch the first step; its a big one! */ 2475 switch (s[0]) 2476 { 2477 2478 case '*': 2479 case '~': 2480 case '%': 2481 case ';': 2482 case '@': 2483 case '!': 2484 case '&': 2485 case '$': 2486 case '?': 2487 case '/': 2488 case '<': 2489 case '>': 2490 case 'b': 2491 case 'm': 2492 case 'n': 2493 case 'o': 2494 case 'p': 2495 case 'q': 2496 case 'v': 2497 case 'w': 2498 case 'y': 2499 case 'z': 2500 case '4': 2501 #ifndef NO_68851 2502 case '|': 2503 #endif 2504 switch (opP->mode) 2505 { 2506 case IMMED: 2507 tmpreg = 0x3c; /* 7.4 */ 2508 if (strchr ("bwl", s[1])) 2509 nextword = get_num (&opP->disp, 90); 2510 else 2511 nextword = get_num (&opP->disp, 0); 2512 if (isvar (&opP->disp)) 2513 add_fix (s[1], &opP->disp, 0, 0); 2514 switch (s[1]) 2515 { 2516 case 'b': 2517 if (!isbyte (nextword)) 2518 opP->error = _("operand out of range"); 2519 addword (nextword); 2520 baseo = 0; 2521 break; 2522 case 'w': 2523 if (!isword (nextword)) 2524 opP->error = _("operand out of range"); 2525 addword (nextword); 2526 baseo = 0; 2527 break; 2528 case 'W': 2529 if (!issword (nextword)) 2530 opP->error = _("operand out of range"); 2531 addword (nextword); 2532 baseo = 0; 2533 break; 2534 case 'l': 2535 addword (nextword >> 16); 2536 addword (nextword); 2537 baseo = 0; 2538 break; 2539 2540 case 'f': 2541 baseo = 2; 2542 outro = 8; 2543 break; 2544 case 'F': 2545 baseo = 4; 2546 outro = 11; 2547 break; 2548 case 'x': 2549 baseo = 6; 2550 outro = 15; 2551 break; 2552 case 'p': 2553 baseo = 6; 2554 outro = -1; 2555 break; 2556 default: 2557 abort (); 2558 } 2559 if (!baseo) 2560 break; 2561 2562 /* We gotta put out some float. */ 2563 if (op (&opP->disp) != O_big) 2564 { 2565 valueT val; 2566 int gencnt; 2567 2568 /* Can other cases happen here? */ 2569 if (op (&opP->disp) != O_constant) 2570 abort (); 2571 2572 val = (valueT) offs (&opP->disp); 2573 gencnt = 0; 2574 do 2575 { 2576 generic_bignum[gencnt] = (LITTLENUM_TYPE) val; 2577 val >>= LITTLENUM_NUMBER_OF_BITS; 2578 ++gencnt; 2579 } 2580 while (val != 0); 2581 offs (&opP->disp) = gencnt; 2582 } 2583 if (offs (&opP->disp) > 0) 2584 { 2585 if (offs (&opP->disp) > baseo) 2586 { 2587 as_warn (_("Bignum too big for %c format; truncated"), 2588 s[1]); 2589 offs (&opP->disp) = baseo; 2590 } 2591 baseo -= offs (&opP->disp); 2592 while (baseo--) 2593 addword (0); 2594 for (wordp = generic_bignum + offs (&opP->disp) - 1; 2595 offs (&opP->disp)--; 2596 --wordp) 2597 addword (*wordp); 2598 break; 2599 } 2600 gen_to_words (words, baseo, (long) outro); 2601 for (wordp = words; baseo--; wordp++) 2602 addword (*wordp); 2603 break; 2604 case DREG: 2605 tmpreg = opP->reg - DATA; /* 0.dreg */ 2606 break; 2607 case AREG: 2608 tmpreg = 0x08 + opP->reg - ADDR; /* 1.areg */ 2609 break; 2610 case AINDR: 2611 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */ 2612 break; 2613 case ADEC: 2614 tmpreg = 0x20 + opP->reg - ADDR; /* 4.areg */ 2615 break; 2616 case AINC: 2617 tmpreg = 0x18 + opP->reg - ADDR; /* 3.areg */ 2618 break; 2619 case DISP: 2620 2621 nextword = get_num (&opP->disp, 90); 2622 2623 /* Convert mode 5 addressing with a zero offset into 2624 mode 2 addressing to reduce the instruction size by a 2625 word. */ 2626 if (! isvar (&opP->disp) 2627 && (nextword == 0) 2628 && (opP->disp.size == SIZE_UNSPEC) 2629 && (opP->reg >= ADDR0) 2630 && (opP->reg <= ADDR7)) 2631 { 2632 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */ 2633 break; 2634 } 2635 2636 if (opP->reg == PC 2637 && ! isvar (&opP->disp) 2638 && m68k_abspcadd) 2639 { 2640 opP->disp.exp.X_op = O_symbol; 2641 opP->disp.exp.X_add_symbol = 2642 section_symbol (absolute_section); 2643 } 2644 2645 /* Force into index mode. Hope this works. */ 2646 2647 /* We do the first bit for 32-bit displacements, and the 2648 second bit for 16 bit ones. It is possible that we 2649 should make the default be WORD instead of LONG, but 2650 I think that'd break GCC, so we put up with a little 2651 inefficiency for the sake of working output. */ 2652 2653 if (!issword (nextword) 2654 || (isvar (&opP->disp) 2655 && ((opP->disp.size == SIZE_UNSPEC 2656 && flag_short_refs == 0 2657 && cpu_of_arch (current_architecture) >= m68020 2658 && ! arch_coldfire_p (current_architecture)) 2659 || opP->disp.size == SIZE_LONG))) 2660 { 2661 if (cpu_of_arch (current_architecture) < m68020 2662 || arch_coldfire_p (current_architecture)) 2663 opP->error = 2664 _("displacement too large for this architecture; needs 68020 or higher"); 2665 if (opP->reg == PC) 2666 tmpreg = 0x3B; /* 7.3 */ 2667 else 2668 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */ 2669 if (isvar (&opP->disp)) 2670 { 2671 if (opP->reg == PC) 2672 { 2673 if (opP->disp.size == SIZE_LONG 2674 #ifdef OBJ_ELF 2675 /* If the displacement needs pic 2676 relocation it cannot be relaxed. */ 2677 || opP->disp.pic_reloc != pic_none 2678 #endif 2679 ) 2680 { 2681 addword (0x0170); 2682 add_fix ('l', &opP->disp, 1, 2); 2683 } 2684 else 2685 { 2686 add_frag (adds (&opP->disp), 2687 SEXT (offs (&opP->disp)), 2688 TAB (PCREL1632, SZ_UNDEF)); 2689 break; 2690 } 2691 } 2692 else 2693 { 2694 addword (0x0170); 2695 add_fix ('l', &opP->disp, 0, 0); 2696 } 2697 } 2698 else 2699 addword (0x0170); 2700 addword (nextword >> 16); 2701 } 2702 else 2703 { 2704 if (opP->reg == PC) 2705 tmpreg = 0x3A; /* 7.2 */ 2706 else 2707 tmpreg = 0x28 + opP->reg - ADDR; /* 5.areg */ 2708 2709 if (isvar (&opP->disp)) 2710 { 2711 if (opP->reg == PC) 2712 { 2713 add_fix ('w', &opP->disp, 1, 0); 2714 } 2715 else 2716 add_fix ('w', &opP->disp, 0, 0); 2717 } 2718 } 2719 addword (nextword); 2720 break; 2721 2722 case POST: 2723 case PRE: 2724 case BASE: 2725 nextword = 0; 2726 baseo = get_num (&opP->disp, 90); 2727 if (opP->mode == POST || opP->mode == PRE) 2728 outro = get_num (&opP->odisp, 90); 2729 /* Figure out the `addressing mode'. 2730 Also turn on the BASE_DISABLE bit, if needed. */ 2731 if (opP->reg == PC || opP->reg == ZPC) 2732 { 2733 tmpreg = 0x3b; /* 7.3 */ 2734 if (opP->reg == ZPC) 2735 nextword |= 0x80; 2736 } 2737 else if (opP->reg == 0) 2738 { 2739 nextword |= 0x80; 2740 tmpreg = 0x30; /* 6.garbage */ 2741 } 2742 else if (opP->reg >= ZADDR0 && opP->reg <= ZADDR7) 2743 { 2744 nextword |= 0x80; 2745 tmpreg = 0x30 + opP->reg - ZADDR0; 2746 } 2747 else 2748 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */ 2749 2750 siz1 = opP->disp.size; 2751 if (opP->mode == POST || opP->mode == PRE) 2752 siz2 = opP->odisp.size; 2753 else 2754 siz2 = SIZE_UNSPEC; 2755 2756 /* Index register stuff. */ 2757 if (opP->index.reg != 0 2758 && opP->index.reg >= DATA 2759 && opP->index.reg <= ADDR7) 2760 { 2761 nextword |= (opP->index.reg - DATA) << 12; 2762 2763 if (opP->index.size == SIZE_LONG 2764 || (opP->index.size == SIZE_UNSPEC 2765 && m68k_index_width_default == SIZE_LONG)) 2766 nextword |= 0x800; 2767 2768 if ((opP->index.scale != 1 2769 && cpu_of_arch (current_architecture) < m68020) 2770 || (opP->index.scale == 8 2771 && (arch_coldfire_p (current_architecture) 2772 && !arch_coldfire_fpu (current_architecture)))) 2773 { 2774 opP->error = 2775 _("scale factor invalid on this architecture; needs cpu32 or 68020 or higher"); 2776 } 2777 2778 if (arch_coldfire_p (current_architecture) 2779 && opP->index.size == SIZE_WORD) 2780 opP->error = _("invalid index size for coldfire"); 2781 2782 switch (opP->index.scale) 2783 { 2784 case 1: 2785 break; 2786 case 2: 2787 nextword |= 0x200; 2788 break; 2789 case 4: 2790 nextword |= 0x400; 2791 break; 2792 case 8: 2793 nextword |= 0x600; 2794 break; 2795 default: 2796 abort (); 2797 } 2798 /* IF its simple, 2799 GET US OUT OF HERE! */ 2800 2801 /* Must be INDEX, with an index register. Address 2802 register cannot be ZERO-PC, and either :b was 2803 forced, or we know it will fit. For a 68000 or 2804 68010, force this mode anyways, because the 2805 larger modes aren't supported. */ 2806 if (opP->mode == BASE 2807 && ((opP->reg >= ADDR0 2808 && opP->reg <= ADDR7) 2809 || opP->reg == PC)) 2810 { 2811 if (siz1 == SIZE_BYTE 2812 || cpu_of_arch (current_architecture) < m68020 2813 || arch_coldfire_p (current_architecture) 2814 || (siz1 == SIZE_UNSPEC 2815 && ! isvar (&opP->disp) 2816 && issbyte (baseo))) 2817 { 2818 nextword += baseo & 0xff; 2819 addword (nextword); 2820 if (isvar (&opP->disp)) 2821 { 2822 /* Do a byte relocation. If it doesn't 2823 fit (possible on m68000) let the 2824 fixup processing complain later. */ 2825 if (opP->reg == PC) 2826 add_fix ('B', &opP->disp, 1, 1); 2827 else 2828 add_fix ('B', &opP->disp, 0, 0); 2829 } 2830 else if (siz1 != SIZE_BYTE) 2831 { 2832 if (siz1 != SIZE_UNSPEC) 2833 as_warn (_("Forcing byte displacement")); 2834 if (! issbyte (baseo)) 2835 opP->error = _("byte displacement out of range"); 2836 } 2837 2838 break; 2839 } 2840 else if (siz1 == SIZE_UNSPEC 2841 && opP->reg == PC 2842 && isvar (&opP->disp) 2843 && subs (&opP->disp) == NULL 2844 #ifdef OBJ_ELF 2845 /* If the displacement needs pic 2846 relocation it cannot be relaxed. */ 2847 && opP->disp.pic_reloc == pic_none 2848 #endif 2849 ) 2850 { 2851 /* The code in md_convert_frag_1 needs to be 2852 able to adjust nextword. Call frag_grow 2853 to ensure that we have enough space in 2854 the frag obstack to make all the bytes 2855 contiguous. */ 2856 frag_grow (14); 2857 nextword += baseo & 0xff; 2858 addword (nextword); 2859 add_frag (adds (&opP->disp), 2860 SEXT (offs (&opP->disp)), 2861 TAB (PCINDEX, SZ_UNDEF)); 2862 2863 break; 2864 } 2865 } 2866 } 2867 else 2868 { 2869 nextword |= 0x40; /* No index reg. */ 2870 if (opP->index.reg >= ZDATA0 2871 && opP->index.reg <= ZDATA7) 2872 nextword |= (opP->index.reg - ZDATA0) << 12; 2873 else if (opP->index.reg >= ZADDR0 2874 || opP->index.reg <= ZADDR7) 2875 nextword |= (opP->index.reg - ZADDR0 + 8) << 12; 2876 } 2877 2878 /* It isn't simple. */ 2879 2880 if (cpu_of_arch (current_architecture) < m68020 2881 || arch_coldfire_p (current_architecture)) 2882 opP->error = 2883 _("invalid operand mode for this architecture; needs 68020 or higher"); 2884 2885 nextword |= 0x100; 2886 /* If the guy specified a width, we assume that it is 2887 wide enough. Maybe it isn't. If so, we lose. */ 2888 switch (siz1) 2889 { 2890 case SIZE_UNSPEC: 2891 if (isvar (&opP->disp) 2892 ? m68k_rel32 2893 : ! issword (baseo)) 2894 { 2895 siz1 = SIZE_LONG; 2896 nextword |= 0x30; 2897 } 2898 else if (! isvar (&opP->disp) && baseo == 0) 2899 nextword |= 0x10; 2900 else 2901 { 2902 nextword |= 0x20; 2903 siz1 = SIZE_WORD; 2904 } 2905 break; 2906 case SIZE_BYTE: 2907 as_warn (_(":b not permitted; defaulting to :w")); 2908 /* Fall through. */ 2909 case SIZE_WORD: 2910 nextword |= 0x20; 2911 break; 2912 case SIZE_LONG: 2913 nextword |= 0x30; 2914 break; 2915 } 2916 2917 /* Figure out inner displacement stuff. */ 2918 if (opP->mode == POST || opP->mode == PRE) 2919 { 2920 if (cpu_of_arch (current_architecture) & cpu32) 2921 opP->error = _("invalid operand mode for this architecture; needs 68020 or higher"); 2922 switch (siz2) 2923 { 2924 case SIZE_UNSPEC: 2925 if (isvar (&opP->odisp) 2926 ? m68k_rel32 2927 : ! issword (outro)) 2928 { 2929 siz2 = SIZE_LONG; 2930 nextword |= 0x3; 2931 } 2932 else if (! isvar (&opP->odisp) && outro == 0) 2933 nextword |= 0x1; 2934 else 2935 { 2936 nextword |= 0x2; 2937 siz2 = SIZE_WORD; 2938 } 2939 break; 2940 case 1: 2941 as_warn (_(":b not permitted; defaulting to :w")); 2942 /* Fall through. */ 2943 case 2: 2944 nextword |= 0x2; 2945 break; 2946 case 3: 2947 nextword |= 0x3; 2948 break; 2949 } 2950 if (opP->mode == POST 2951 && (nextword & 0x40) == 0) 2952 nextword |= 0x04; 2953 } 2954 addword (nextword); 2955 2956 if (siz1 != SIZE_UNSPEC && isvar (&opP->disp)) 2957 { 2958 if (opP->reg == PC || opP->reg == ZPC) 2959 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 1, 2); 2960 else 2961 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 0, 0); 2962 } 2963 if (siz1 == SIZE_LONG) 2964 addword (baseo >> 16); 2965 if (siz1 != SIZE_UNSPEC) 2966 addword (baseo); 2967 2968 if (siz2 != SIZE_UNSPEC && isvar (&opP->odisp)) 2969 add_fix (siz2 == SIZE_LONG ? 'l' : 'w', &opP->odisp, 0, 0); 2970 if (siz2 == SIZE_LONG) 2971 addword (outro >> 16); 2972 if (siz2 != SIZE_UNSPEC) 2973 addword (outro); 2974 2975 break; 2976 2977 case ABSL: 2978 nextword = get_num (&opP->disp, 90); 2979 switch (opP->disp.size) 2980 { 2981 default: 2982 abort (); 2983 case SIZE_UNSPEC: 2984 if (!isvar (&opP->disp) && issword (offs (&opP->disp))) 2985 { 2986 tmpreg = 0x38; /* 7.0 */ 2987 addword (nextword); 2988 break; 2989 } 2990 if (isvar (&opP->disp) 2991 && !subs (&opP->disp) 2992 && adds (&opP->disp) 2993 #ifdef OBJ_ELF 2994 /* If the displacement needs pic relocation it 2995 cannot be relaxed. */ 2996 && opP->disp.pic_reloc == pic_none 2997 #endif 2998 && !flag_long_jumps 2999 && !strchr ("~%&$?", s[0])) 3000 { 3001 tmpreg = 0x3A; /* 7.2 */ 3002 add_frag (adds (&opP->disp), 3003 SEXT (offs (&opP->disp)), 3004 TAB (ABSTOPCREL, SZ_UNDEF)); 3005 break; 3006 } 3007 /* Fall through into long. */ 3008 case SIZE_LONG: 3009 if (isvar (&opP->disp)) 3010 add_fix ('l', &opP->disp, 0, 0); 3011 3012 tmpreg = 0x39;/* 7.1 mode */ 3013 addword (nextword >> 16); 3014 addword (nextword); 3015 break; 3016 3017 case SIZE_BYTE: 3018 as_bad (_("unsupported byte value; use a different suffix")); 3019 /* Fall through. */ 3020 3021 case SIZE_WORD: 3022 if (isvar (&opP->disp)) 3023 add_fix ('w', &opP->disp, 0, 0); 3024 3025 tmpreg = 0x38;/* 7.0 mode */ 3026 addword (nextword); 3027 break; 3028 } 3029 break; 3030 case CONTROL: 3031 case FPREG: 3032 default: 3033 as_bad (_("unknown/incorrect operand")); 3034 /* abort (); */ 3035 } 3036 3037 /* If s[0] is '4', then this is for the mac instructions 3038 that can have a trailing_ampersand set. If so, set 0x100 3039 bit on tmpreg so install_gen_operand can check for it and 3040 set the appropriate bit (word2, bit 5). */ 3041 if (s[0] == '4') 3042 { 3043 if (opP->trailing_ampersand) 3044 tmpreg |= 0x100; 3045 } 3046 install_gen_operand (s[1], tmpreg); 3047 break; 3048 3049 case '#': 3050 case '^': 3051 switch (s[1]) 3052 { /* JF: I hate floating point! */ 3053 case 'j': 3054 tmpreg = 70; 3055 break; 3056 case '8': 3057 tmpreg = 20; 3058 break; 3059 case 'C': 3060 tmpreg = 50; 3061 break; 3062 case '3': 3063 default: 3064 tmpreg = 90; 3065 break; 3066 } 3067 tmpreg = get_num (&opP->disp, tmpreg); 3068 if (isvar (&opP->disp)) 3069 add_fix (s[1], &opP->disp, 0, 0); 3070 switch (s[1]) 3071 { 3072 case 'b': /* Danger: These do no check for 3073 certain types of overflow. 3074 user beware! */ 3075 if (!isbyte (tmpreg)) 3076 opP->error = _("out of range"); 3077 insop (tmpreg, opcode); 3078 if (isvar (&opP->disp)) 3079 the_ins.reloc[the_ins.nrel - 1].n = 3080 (opcode->m_codenum) * 2 + 1; 3081 break; 3082 case 'B': 3083 if (!issbyte (tmpreg)) 3084 opP->error = _("out of range"); 3085 the_ins.opcode[the_ins.numo - 1] |= tmpreg & 0xff; 3086 if (isvar (&opP->disp)) 3087 the_ins.reloc[the_ins.nrel - 1].n = opcode->m_codenum * 2 - 1; 3088 break; 3089 case 'w': 3090 if (!isword (tmpreg)) 3091 opP->error = _("out of range"); 3092 insop (tmpreg, opcode); 3093 if (isvar (&opP->disp)) 3094 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2; 3095 break; 3096 case 'W': 3097 if (!issword (tmpreg)) 3098 opP->error = _("out of range"); 3099 insop (tmpreg, opcode); 3100 if (isvar (&opP->disp)) 3101 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2; 3102 break; 3103 case 'l': 3104 /* Because of the way insop works, we put these two out 3105 backwards. */ 3106 insop (tmpreg, opcode); 3107 insop (tmpreg >> 16, opcode); 3108 if (isvar (&opP->disp)) 3109 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2; 3110 break; 3111 case '3': 3112 tmpreg &= 0xFF; 3113 case '8': 3114 case 'C': 3115 case 'j': 3116 install_operand (s[1], tmpreg); 3117 break; 3118 default: 3119 abort (); 3120 } 3121 break; 3122 3123 case '+': 3124 case '-': 3125 case 'A': 3126 case 'a': 3127 install_operand (s[1], opP->reg - ADDR); 3128 break; 3129 3130 case 'B': 3131 tmpreg = get_num (&opP->disp, 90); 3132 3133 switch (s[1]) 3134 { 3135 case 'B': 3136 add_fix ('B', &opP->disp, 1, -1); 3137 break; 3138 case 'W': 3139 add_fix ('w', &opP->disp, 1, 0); 3140 addword (0); 3141 break; 3142 case 'L': 3143 long_branch: 3144 the_ins.opcode[0] |= 0xff; 3145 add_fix ('l', &opP->disp, 1, 0); 3146 addword (0); 3147 addword (0); 3148 break; 3149 case 'g': /* Conditional branch */ 3150 have_disp = HAVE_LONG_CALL (current_architecture); 3151 goto var_branch; 3152 3153 case 'b': /* Unconditional branch */ 3154 have_disp = HAVE_LONG_BRANCH (current_architecture); 3155 use_pl = LONG_BRANCH_VIA_COND (current_architecture); 3156 goto var_branch; 3157 3158 case 's': /* Unconditional subroutine */ 3159 have_disp = HAVE_LONG_CALL (current_architecture); 3160 3161 var_branch: 3162 if (subs (&opP->disp) /* We can't relax it. */ 3163 #ifdef OBJ_ELF 3164 /* If the displacement needs pic relocation it cannot be 3165 relaxed. */ 3166 || opP->disp.pic_reloc != pic_none 3167 #endif 3168 || 0) 3169 { 3170 if (!have_disp) 3171 as_warn (_("Can't use long branches on this architecture")); 3172 goto long_branch; 3173 } 3174 3175 /* This could either be a symbol, or an absolute 3176 address. If it's an absolute address, turn it into 3177 an absolute jump right here and keep it out of the 3178 relaxer. */ 3179 if (adds (&opP->disp) == 0) 3180 { 3181 if (the_ins.opcode[0] == 0x6000) /* jbra */ 3182 the_ins.opcode[0] = 0x4EF9; 3183 else if (the_ins.opcode[0] == 0x6100) /* jbsr */ 3184 the_ins.opcode[0] = 0x4EB9; 3185 else /* jCC */ 3186 { 3187 the_ins.opcode[0] ^= 0x0100; 3188 the_ins.opcode[0] |= 0x0006; 3189 addword (0x4EF9); 3190 } 3191 add_fix ('l', &opP->disp, 0, 0); 3192 addword (0); 3193 addword (0); 3194 break; 3195 } 3196 3197 /* Now we know it's going into the relaxer. Now figure 3198 out which mode. We try in this order of preference: 3199 long branch, absolute jump, byte/word branches only. */ 3200 if (have_disp) 3201 add_frag (adds (&opP->disp), 3202 SEXT (offs (&opP->disp)), 3203 TAB (BRANCHBWL, SZ_UNDEF)); 3204 else if (! flag_keep_pcrel) 3205 { 3206 if ((the_ins.opcode[0] == 0x6000) 3207 || (the_ins.opcode[0] == 0x6100)) 3208 add_frag (adds (&opP->disp), 3209 SEXT (offs (&opP->disp)), 3210 TAB (BRABSJUNC, SZ_UNDEF)); 3211 else 3212 add_frag (adds (&opP->disp), 3213 SEXT (offs (&opP->disp)), 3214 TAB (BRABSJCOND, SZ_UNDEF)); 3215 } 3216 else 3217 add_frag (adds (&opP->disp), 3218 SEXT (offs (&opP->disp)), 3219 (use_pl ? TAB (BRANCHBWPL, SZ_UNDEF) 3220 : TAB (BRANCHBW, SZ_UNDEF))); 3221 break; 3222 case 'w': 3223 if (isvar (&opP->disp)) 3224 { 3225 /* Check for DBcc instructions. We can relax them, 3226 but only if we have long branches and/or absolute 3227 jumps. */ 3228 if (((the_ins.opcode[0] & 0xf0f8) == 0x50c8) 3229 && (HAVE_LONG_BRANCH (current_architecture) 3230 || ! flag_keep_pcrel)) 3231 { 3232 if (HAVE_LONG_BRANCH (current_architecture)) 3233 add_frag (adds (&opP->disp), 3234 SEXT (offs (&opP->disp)), 3235 TAB (DBCCLBR, SZ_UNDEF)); 3236 else 3237 add_frag (adds (&opP->disp), 3238 SEXT (offs (&opP->disp)), 3239 TAB (DBCCABSJ, SZ_UNDEF)); 3240 break; 3241 } 3242 add_fix ('w', &opP->disp, 1, 0); 3243 } 3244 addword (0); 3245 break; 3246 case 'C': /* Fixed size LONG coproc branches. */ 3247 add_fix ('l', &opP->disp, 1, 0); 3248 addword (0); 3249 addword (0); 3250 break; 3251 case 'c': /* Var size Coprocesssor branches. */ 3252 if (subs (&opP->disp) || (adds (&opP->disp) == 0)) 3253 { 3254 the_ins.opcode[the_ins.numo - 1] |= 0x40; 3255 add_fix ('l', &opP->disp, 1, 0); 3256 addword (0); 3257 addword (0); 3258 } 3259 else 3260 add_frag (adds (&opP->disp), 3261 SEXT (offs (&opP->disp)), 3262 TAB (FBRANCH, SZ_UNDEF)); 3263 break; 3264 default: 3265 abort (); 3266 } 3267 break; 3268 3269 case 'C': /* Ignore it. */ 3270 break; 3271 3272 case 'd': /* JF this is a kludge. */ 3273 install_operand ('s', opP->reg - ADDR); 3274 tmpreg = get_num (&opP->disp, 90); 3275 if (!issword (tmpreg)) 3276 { 3277 as_warn (_("Expression out of range, using 0")); 3278 tmpreg = 0; 3279 } 3280 addword (tmpreg); 3281 break; 3282 3283 case 'D': 3284 install_operand (s[1], opP->reg - DATA); 3285 break; 3286 3287 case 'e': /* EMAC ACCx, reg/reg. */ 3288 install_operand (s[1], opP->reg - ACC); 3289 break; 3290 3291 case 'E': /* Ignore it. */ 3292 break; 3293 3294 case 'F': 3295 install_operand (s[1], opP->reg - FP0); 3296 break; 3297 3298 case 'g': /* EMAC ACCEXTx. */ 3299 install_operand (s[1], opP->reg - ACCEXT01); 3300 break; 3301 3302 case 'G': /* Ignore it. */ 3303 case 'H': 3304 break; 3305 3306 case 'I': 3307 tmpreg = opP->reg - COP0; 3308 install_operand (s[1], tmpreg); 3309 break; 3310 3311 case 'i': /* MAC/EMAC scale factor. */ 3312 install_operand (s[1], opP->mode == LSH ? 0x1 : 0x3); 3313 break; 3314 3315 case 'J': /* JF foo. */ 3316 switch (opP->reg) 3317 { 3318 case SFC: 3319 tmpreg = 0x000; 3320 break; 3321 case DFC: 3322 tmpreg = 0x001; 3323 break; 3324 case CACR: 3325 tmpreg = 0x002; 3326 break; 3327 case TC: 3328 case ASID: 3329 tmpreg = 0x003; 3330 break; 3331 case ACR0: 3332 case ITT0: 3333 tmpreg = 0x004; 3334 break; 3335 case ACR1: 3336 case ITT1: 3337 tmpreg = 0x005; 3338 break; 3339 case ACR2: 3340 case DTT0: 3341 tmpreg = 0x006; 3342 break; 3343 case ACR3: 3344 case DTT1: 3345 tmpreg = 0x007; 3346 break; 3347 case BUSCR: 3348 case MMUBAR: 3349 tmpreg = 0x008; 3350 break; 3351 case RGPIOBAR: 3352 tmpreg = 0x009; 3353 break; 3354 case ACR4: 3355 case ACR5: 3356 case ACR6: 3357 case ACR7: 3358 tmpreg = 0x00c + (opP->reg - ACR4); 3359 break; 3360 3361 case USP: 3362 tmpreg = 0x800; 3363 break; 3364 case VBR: 3365 tmpreg = 0x801; 3366 break; 3367 case CAAR: 3368 case CPUCR: 3369 tmpreg = 0x802; 3370 break; 3371 case MSP: 3372 tmpreg = 0x803; 3373 break; 3374 case ISP: 3375 tmpreg = 0x804; 3376 break; 3377 case MMUSR: 3378 tmpreg = 0x805; 3379 break; 3380 case URP: 3381 tmpreg = 0x806; 3382 break; 3383 case SRP: 3384 tmpreg = 0x807; 3385 break; 3386 case PCR: 3387 tmpreg = 0x808; 3388 break; 3389 case ROMBAR: 3390 case ROMBAR0: 3391 tmpreg = 0xC00; 3392 break; 3393 case ROMBAR1: 3394 tmpreg = 0xC01; 3395 break; 3396 case FLASHBAR: 3397 case RAMBAR0: 3398 case RAMBAR_ALT: 3399 tmpreg = 0xC04; 3400 break; 3401 case RAMBAR: 3402 case RAMBAR1: 3403 tmpreg = 0xC05; 3404 break; 3405 case MPCR: 3406 tmpreg = 0xC0C; 3407 break; 3408 case EDRAMBAR: 3409 tmpreg = 0xC0D; 3410 break; 3411 case MBAR0: 3412 case MBAR2: 3413 case SECMBAR: 3414 tmpreg = 0xC0E; 3415 break; 3416 case MBAR1: 3417 case MBAR: 3418 tmpreg = 0xC0F; 3419 break; 3420 case PCR1U0: 3421 tmpreg = 0xD02; 3422 break; 3423 case PCR1L0: 3424 tmpreg = 0xD03; 3425 break; 3426 case PCR2U0: 3427 tmpreg = 0xD04; 3428 break; 3429 case PCR2L0: 3430 tmpreg = 0xD05; 3431 break; 3432 case PCR3U0: 3433 tmpreg = 0xD06; 3434 break; 3435 case PCR3L0: 3436 tmpreg = 0xD07; 3437 break; 3438 case PCR1L1: 3439 tmpreg = 0xD0A; 3440 break; 3441 case PCR1U1: 3442 tmpreg = 0xD0B; 3443 break; 3444 case PCR2L1: 3445 tmpreg = 0xD0C; 3446 break; 3447 case PCR2U1: 3448 tmpreg = 0xD0D; 3449 break; 3450 case PCR3L1: 3451 tmpreg = 0xD0E; 3452 break; 3453 case PCR3U1: 3454 tmpreg = 0xD0F; 3455 break; 3456 case CAC: 3457 tmpreg = 0xFFE; 3458 break; 3459 case MBO: 3460 tmpreg = 0xFFF; 3461 break; 3462 default: 3463 abort (); 3464 } 3465 install_operand (s[1], tmpreg); 3466 break; 3467 3468 case 'k': 3469 tmpreg = get_num (&opP->disp, 55); 3470 install_operand (s[1], tmpreg & 0x7f); 3471 break; 3472 3473 case 'l': 3474 tmpreg = opP->mask; 3475 if (s[1] == 'w') 3476 { 3477 if (tmpreg & 0x7FF0000) 3478 as_bad (_("Floating point register in register list")); 3479 insop (reverse_16_bits (tmpreg), opcode); 3480 } 3481 else 3482 { 3483 if (tmpreg & 0x700FFFF) 3484 as_bad (_("Wrong register in floating-point reglist")); 3485 install_operand (s[1], reverse_8_bits (tmpreg >> 16)); 3486 } 3487 break; 3488 3489 case 'L': 3490 tmpreg = opP->mask; 3491 if (s[1] == 'w') 3492 { 3493 if (tmpreg & 0x7FF0000) 3494 as_bad (_("Floating point register in register list")); 3495 insop (tmpreg, opcode); 3496 } 3497 else if (s[1] == '8') 3498 { 3499 if (tmpreg & 0x0FFFFFF) 3500 as_bad (_("incorrect register in reglist")); 3501 install_operand (s[1], tmpreg >> 24); 3502 } 3503 else 3504 { 3505 if (tmpreg & 0x700FFFF) 3506 as_bad (_("wrong register in floating-point reglist")); 3507 else 3508 install_operand (s[1], tmpreg >> 16); 3509 } 3510 break; 3511 3512 case 'M': 3513 install_operand (s[1], get_num (&opP->disp, 60)); 3514 break; 3515 3516 case 'O': 3517 tmpreg = ((opP->mode == DREG) 3518 ? 0x20 + (int) (opP->reg - DATA) 3519 : (get_num (&opP->disp, 40) & 0x1F)); 3520 install_operand (s[1], tmpreg); 3521 break; 3522 3523 case 'Q': 3524 tmpreg = get_num (&opP->disp, 10); 3525 if (tmpreg == 8) 3526 tmpreg = 0; 3527 install_operand (s[1], tmpreg); 3528 break; 3529 3530 case 'R': 3531 /* This depends on the fact that ADDR registers are eight 3532 more than their corresponding DATA regs, so the result 3533 will have the ADDR_REG bit set. */ 3534 install_operand (s[1], opP->reg - DATA); 3535 break; 3536 3537 case 'r': 3538 if (opP->mode == AINDR) 3539 install_operand (s[1], opP->reg - DATA); 3540 else 3541 install_operand (s[1], opP->index.reg - DATA); 3542 break; 3543 3544 case 's': 3545 if (opP->reg == FPI) 3546 tmpreg = 0x1; 3547 else if (opP->reg == FPS) 3548 tmpreg = 0x2; 3549 else if (opP->reg == FPC) 3550 tmpreg = 0x4; 3551 else 3552 abort (); 3553 install_operand (s[1], tmpreg); 3554 break; 3555 3556 case 'S': /* Ignore it. */ 3557 break; 3558 3559 case 'T': 3560 install_operand (s[1], get_num (&opP->disp, 30)); 3561 break; 3562 3563 case 'U': /* Ignore it. */ 3564 break; 3565 3566 case 'c': 3567 switch (opP->reg) 3568 { 3569 case NC: 3570 tmpreg = 0; 3571 break; 3572 case DC: 3573 tmpreg = 1; 3574 break; 3575 case IC: 3576 tmpreg = 2; 3577 break; 3578 case BC: 3579 tmpreg = 3; 3580 break; 3581 default: 3582 as_fatal (_("failed sanity check")); 3583 } /* switch on cache token. */ 3584 install_operand (s[1], tmpreg); 3585 break; 3586 #ifndef NO_68851 3587 /* JF: These are out of order, I fear. */ 3588 case 'f': 3589 switch (opP->reg) 3590 { 3591 case SFC: 3592 tmpreg = 0; 3593 break; 3594 case DFC: 3595 tmpreg = 1; 3596 break; 3597 default: 3598 abort (); 3599 } 3600 install_operand (s[1], tmpreg); 3601 break; 3602 3603 case '0': 3604 case '1': 3605 case '2': 3606 switch (opP->reg) 3607 { 3608 case TC: 3609 tmpreg = 0; 3610 break; 3611 case CAL: 3612 tmpreg = 4; 3613 break; 3614 case VAL: 3615 tmpreg = 5; 3616 break; 3617 case SCC: 3618 tmpreg = 6; 3619 break; 3620 case AC: 3621 tmpreg = 7; 3622 break; 3623 default: 3624 abort (); 3625 } 3626 install_operand (s[1], tmpreg); 3627 break; 3628 3629 case 'V': 3630 if (opP->reg == VAL) 3631 break; 3632 abort (); 3633 3634 case 'W': 3635 switch (opP->reg) 3636 { 3637 case DRP: 3638 tmpreg = 1; 3639 break; 3640 case SRP: 3641 tmpreg = 2; 3642 break; 3643 case CRP: 3644 tmpreg = 3; 3645 break; 3646 default: 3647 abort (); 3648 } 3649 install_operand (s[1], tmpreg); 3650 break; 3651 3652 case 'X': 3653 switch (opP->reg) 3654 { 3655 case BAD: 3656 case BAD + 1: 3657 case BAD + 2: 3658 case BAD + 3: 3659 case BAD + 4: 3660 case BAD + 5: 3661 case BAD + 6: 3662 case BAD + 7: 3663 tmpreg = (4 << 10) | ((opP->reg - BAD) << 2); 3664 break; 3665 3666 case BAC: 3667 case BAC + 1: 3668 case BAC + 2: 3669 case BAC + 3: 3670 case BAC + 4: 3671 case BAC + 5: 3672 case BAC + 6: 3673 case BAC + 7: 3674 tmpreg = (5 << 10) | ((opP->reg - BAC) << 2); 3675 break; 3676 3677 default: 3678 abort (); 3679 } 3680 install_operand (s[1], tmpreg); 3681 break; 3682 case 'Y': 3683 know (opP->reg == PSR); 3684 break; 3685 case 'Z': 3686 know (opP->reg == PCSR); 3687 break; 3688 #endif /* m68851 */ 3689 case '3': 3690 switch (opP->reg) 3691 { 3692 case TT0: 3693 tmpreg = 2; 3694 break; 3695 case TT1: 3696 tmpreg = 3; 3697 break; 3698 default: 3699 abort (); 3700 } 3701 install_operand (s[1], tmpreg); 3702 break; 3703 case 't': 3704 tmpreg = get_num (&opP->disp, 20); 3705 install_operand (s[1], tmpreg); 3706 break; 3707 case '_': /* used only for move16 absolute 32-bit address. */ 3708 if (isvar (&opP->disp)) 3709 add_fix ('l', &opP->disp, 0, 0); 3710 tmpreg = get_num (&opP->disp, 90); 3711 addword (tmpreg >> 16); 3712 addword (tmpreg & 0xFFFF); 3713 break; 3714 case 'u': 3715 install_operand (s[1], opP->reg - DATA0L); 3716 opP->reg -= (DATA0L); 3717 opP->reg &= 0x0F; /* remove upper/lower bit. */ 3718 break; 3719 case 'x': 3720 tmpreg = get_num (&opP->disp, 80); 3721 if (tmpreg == -1) 3722 tmpreg = 0; 3723 install_operand (s[1], tmpreg); 3724 break; 3725 case 'j': 3726 tmpreg = get_num (&opP->disp, 10); 3727 install_operand (s[1], tmpreg - 1); 3728 break; 3729 case 'K': 3730 tmpreg = get_num (&opP->disp, 65); 3731 install_operand (s[1], tmpreg); 3732 break; 3733 default: 3734 abort (); 3735 } 3736 } 3737 3738 /* By the time whe get here (FINALLY) the_ins contains the complete 3739 instruction, ready to be emitted. . . */ 3740 } 3741 3742 static int 3743 reverse_16_bits (int in) 3744 { 3745 int out = 0; 3746 int n; 3747 3748 static int mask[16] = 3749 { 3750 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080, 3751 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000 3752 }; 3753 for (n = 0; n < 16; n++) 3754 { 3755 if (in & mask[n]) 3756 out |= mask[15 - n]; 3757 } 3758 return out; 3759 } /* reverse_16_bits() */ 3760 3761 static int 3762 reverse_8_bits (int in) 3763 { 3764 int out = 0; 3765 int n; 3766 3767 static int mask[8] = 3768 { 3769 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080, 3770 }; 3771 3772 for (n = 0; n < 8; n++) 3773 { 3774 if (in & mask[n]) 3775 out |= mask[7 - n]; 3776 } 3777 return out; 3778 } /* reverse_8_bits() */ 3779 3780 /* Cause an extra frag to be generated here, inserting up to 3781 FRAG_VAR_SIZE bytes. TYPE is the subtype of the frag to be 3782 generated; its primary type is rs_machine_dependent. 3783 3784 The TYPE parameter is also used by md_convert_frag_1 and 3785 md_estimate_size_before_relax. The appropriate type of fixup will 3786 be emitted by md_convert_frag_1. 3787 3788 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */ 3789 static void 3790 install_operand (int mode, int val) 3791 { 3792 switch (mode) 3793 { 3794 case 's': 3795 the_ins.opcode[0] |= val & 0xFF; /* JF FF is for M kludge. */ 3796 break; 3797 case 'd': 3798 the_ins.opcode[0] |= val << 9; 3799 break; 3800 case 'E': 3801 the_ins.opcode[1] |= val << 9; 3802 break; 3803 case '1': 3804 the_ins.opcode[1] |= val << 12; 3805 break; 3806 case '2': 3807 the_ins.opcode[1] |= val << 6; 3808 break; 3809 case '3': 3810 the_ins.opcode[1] |= val; 3811 break; 3812 case '4': 3813 the_ins.opcode[2] |= val << 12; 3814 break; 3815 case '5': 3816 the_ins.opcode[2] |= val << 6; 3817 break; 3818 case '6': 3819 /* DANGER! This is a hack to force cas2l and cas2w cmds to be 3820 three words long! */ 3821 the_ins.numo++; 3822 the_ins.opcode[2] |= val; 3823 break; 3824 case '7': 3825 the_ins.opcode[1] |= val << 7; 3826 break; 3827 case '8': 3828 the_ins.opcode[1] |= val << 10; 3829 break; 3830 #ifndef NO_68851 3831 case '9': 3832 the_ins.opcode[1] |= val << 5; 3833 break; 3834 #endif 3835 3836 case 't': 3837 the_ins.opcode[1] |= (val << 10) | (val << 7); 3838 break; 3839 case 'D': 3840 the_ins.opcode[1] |= (val << 12) | val; 3841 break; 3842 case 'g': 3843 the_ins.opcode[0] |= val = 0xff; 3844 break; 3845 case 'i': 3846 the_ins.opcode[0] |= val << 9; 3847 break; 3848 case 'C': 3849 the_ins.opcode[1] |= val; 3850 break; 3851 case 'j': 3852 the_ins.opcode[1] |= val; 3853 the_ins.numo++; /* What a hack. */ 3854 break; 3855 case 'k': 3856 the_ins.opcode[1] |= val << 4; 3857 break; 3858 case 'b': 3859 case 'w': 3860 case 'W': 3861 case 'l': 3862 break; 3863 case 'e': 3864 the_ins.opcode[0] |= (val << 6); 3865 break; 3866 case 'L': 3867 the_ins.opcode[1] = (val >> 16); 3868 the_ins.opcode[2] = val & 0xffff; 3869 break; 3870 case 'm': 3871 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3)); 3872 the_ins.opcode[0] |= ((val & 0x7) << 9); 3873 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4)); 3874 break; 3875 case 'n': /* MAC/EMAC Rx on !load. */ 3876 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3)); 3877 the_ins.opcode[0] |= ((val & 0x7) << 9); 3878 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4)); 3879 break; 3880 case 'o': /* MAC/EMAC Rx on load. */ 3881 the_ins.opcode[1] |= val << 12; 3882 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4)); 3883 break; 3884 case 'M': /* MAC/EMAC Ry on !load. */ 3885 the_ins.opcode[0] |= (val & 0xF); 3886 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4)); 3887 break; 3888 case 'N': /* MAC/EMAC Ry on load. */ 3889 the_ins.opcode[1] |= (val & 0xF); 3890 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4)); 3891 break; 3892 case 'h': 3893 the_ins.opcode[1] |= ((val != 1) << 10); 3894 break; 3895 case 'F': 3896 the_ins.opcode[0] |= ((val & 0x3) << 9); 3897 break; 3898 case 'f': 3899 the_ins.opcode[0] |= ((val & 0x3) << 0); 3900 break; 3901 case 'G': /* EMAC accumulator in a EMAC load instruction. */ 3902 the_ins.opcode[0] |= ((~val & 0x1) << 7); 3903 the_ins.opcode[1] |= ((val & 0x2) << (4 - 1)); 3904 break; 3905 case 'H': /* EMAC accumulator in a EMAC non-load instruction. */ 3906 the_ins.opcode[0] |= ((val & 0x1) << 7); 3907 the_ins.opcode[1] |= ((val & 0x2) << (4 - 1)); 3908 break; 3909 case 'I': 3910 the_ins.opcode[1] |= ((val & 0x3) << 9); 3911 break; 3912 case ']': 3913 the_ins.opcode[0] |= (val & 0x1) <<10; 3914 break; 3915 case 'c': 3916 default: 3917 as_fatal (_("failed sanity check.")); 3918 } 3919 } 3920 3921 static void 3922 install_gen_operand (int mode, int val) 3923 { 3924 switch (mode) 3925 { 3926 case '/': /* Special for mask loads for mac/msac insns with 3927 possible mask; trailing_ampersend set in bit 8. */ 3928 the_ins.opcode[0] |= (val & 0x3f); 3929 the_ins.opcode[1] |= (((val & 0x100) >> 8) << 5); 3930 break; 3931 case 's': 3932 the_ins.opcode[0] |= val; 3933 break; 3934 case 'd': 3935 /* This is a kludge!!! */ 3936 the_ins.opcode[0] |= (val & 0x07) << 9 | (val & 0x38) << 3; 3937 break; 3938 case 'b': 3939 case 'w': 3940 case 'l': 3941 case 'f': 3942 case 'F': 3943 case 'x': 3944 case 'p': 3945 the_ins.opcode[0] |= val; 3946 break; 3947 /* more stuff goes here. */ 3948 default: 3949 as_fatal (_("failed sanity check.")); 3950 } 3951 } 3952 3953 /* Verify that we have some number of paren pairs, do m68k_ip_op(), and 3954 then deal with the bitfield hack. */ 3955 3956 static char * 3957 crack_operand (char *str, struct m68k_op *opP) 3958 { 3959 int parens; 3960 int c; 3961 char *beg_str; 3962 int inquote = 0; 3963 3964 if (!str) 3965 { 3966 return str; 3967 } 3968 beg_str = str; 3969 for (parens = 0; *str && (parens > 0 || inquote || notend (str)); str++) 3970 { 3971 if (! inquote) 3972 { 3973 if (*str == '(') 3974 parens++; 3975 else if (*str == ')') 3976 { 3977 if (!parens) 3978 { /* ERROR. */ 3979 opP->error = _("Extra )"); 3980 return str; 3981 } 3982 --parens; 3983 } 3984 } 3985 if (flag_mri && *str == '\'') 3986 inquote = ! inquote; 3987 } 3988 if (!*str && parens) 3989 { /* ERROR. */ 3990 opP->error = _("Missing )"); 3991 return str; 3992 } 3993 c = *str; 3994 *str = '\0'; 3995 if (m68k_ip_op (beg_str, opP) != 0) 3996 { 3997 *str = c; 3998 return str; 3999 } 4000 *str = c; 4001 if (c == '}') 4002 c = *++str; /* JF bitfield hack. */ 4003 if (c) 4004 { 4005 c = *++str; 4006 if (!c) 4007 as_bad (_("Missing operand")); 4008 } 4009 4010 /* Detect MRI REG symbols and convert them to REGLSTs. */ 4011 if (opP->mode == CONTROL && (int)opP->reg < 0) 4012 { 4013 opP->mode = REGLST; 4014 opP->mask = ~(int)opP->reg; 4015 opP->reg = 0; 4016 } 4017 4018 return str; 4019 } 4020 4021 /* This is the guts of the machine-dependent assembler. STR points to a 4022 machine dependent instruction. This function is supposed to emit 4023 the frags/bytes it assembles to. 4024 */ 4025 4026 static void 4027 insert_reg (const char *regname, int regnum) 4028 { 4029 char buf[100]; 4030 int i; 4031 4032 #ifdef REGISTER_PREFIX 4033 if (!flag_reg_prefix_optional) 4034 { 4035 buf[0] = REGISTER_PREFIX; 4036 strcpy (buf + 1, regname); 4037 regname = buf; 4038 } 4039 #endif 4040 4041 symbol_table_insert (symbol_new (regname, reg_section, regnum, 4042 &zero_address_frag)); 4043 4044 for (i = 0; regname[i]; i++) 4045 buf[i] = TOUPPER (regname[i]); 4046 buf[i] = '\0'; 4047 4048 symbol_table_insert (symbol_new (buf, reg_section, regnum, 4049 &zero_address_frag)); 4050 } 4051 4052 struct init_entry 4053 { 4054 const char *name; 4055 int number; 4056 }; 4057 4058 static const struct init_entry init_table[] = 4059 { 4060 { "d0", DATA0 }, 4061 { "d1", DATA1 }, 4062 { "d2", DATA2 }, 4063 { "d3", DATA3 }, 4064 { "d4", DATA4 }, 4065 { "d5", DATA5 }, 4066 { "d6", DATA6 }, 4067 { "d7", DATA7 }, 4068 { "a0", ADDR0 }, 4069 { "a1", ADDR1 }, 4070 { "a2", ADDR2 }, 4071 { "a3", ADDR3 }, 4072 { "a4", ADDR4 }, 4073 { "a5", ADDR5 }, 4074 { "a6", ADDR6 }, 4075 { "fp", ADDR6 }, 4076 { "a7", ADDR7 }, 4077 { "sp", ADDR7 }, 4078 { "ssp", ADDR7 }, 4079 { "fp0", FP0 }, 4080 { "fp1", FP1 }, 4081 { "fp2", FP2 }, 4082 { "fp3", FP3 }, 4083 { "fp4", FP4 }, 4084 { "fp5", FP5 }, 4085 { "fp6", FP6 }, 4086 { "fp7", FP7 }, 4087 { "fpi", FPI }, 4088 { "fpiar", FPI }, 4089 { "fpc", FPI }, 4090 { "fps", FPS }, 4091 { "fpsr", FPS }, 4092 { "fpc", FPC }, 4093 { "fpcr", FPC }, 4094 { "control", FPC }, 4095 { "status", FPS }, 4096 { "iaddr", FPI }, 4097 4098 { "cop0", COP0 }, 4099 { "cop1", COP1 }, 4100 { "cop2", COP2 }, 4101 { "cop3", COP3 }, 4102 { "cop4", COP4 }, 4103 { "cop5", COP5 }, 4104 { "cop6", COP6 }, 4105 { "cop7", COP7 }, 4106 { "pc", PC }, 4107 { "zpc", ZPC }, 4108 { "sr", SR }, 4109 4110 { "ccr", CCR }, 4111 { "cc", CCR }, 4112 4113 { "acc", ACC }, 4114 { "acc0", ACC }, 4115 { "acc1", ACC1 }, 4116 { "acc2", ACC2 }, 4117 { "acc3", ACC3 }, 4118 { "accext01", ACCEXT01 }, 4119 { "accext23", ACCEXT23 }, 4120 { "macsr", MACSR }, 4121 { "mask", MASK }, 4122 4123 /* Control registers. */ 4124 { "sfc", SFC }, /* Source Function Code. */ 4125 { "sfcr", SFC }, 4126 { "dfc", DFC }, /* Destination Function Code. */ 4127 { "dfcr", DFC }, 4128 { "cacr", CACR }, /* Cache Control Register. */ 4129 { "caar", CAAR }, /* Cache Address Register. */ 4130 { "cpucr", CPUCR }, /* CPU Control Register. */ 4131 4132 { "usp", USP }, /* User Stack Pointer. */ 4133 { "vbr", VBR }, /* Vector Base Register. */ 4134 { "msp", MSP }, /* Master Stack Pointer. */ 4135 { "isp", ISP }, /* Interrupt Stack Pointer. */ 4136 4137 { "itt0", ITT0 }, /* Instruction Transparent Translation Reg 0. */ 4138 { "itt1", ITT1 }, /* Instruction Transparent Translation Reg 1. */ 4139 { "dtt0", DTT0 }, /* Data Transparent Translation Register 0. */ 4140 { "dtt1", DTT1 }, /* Data Transparent Translation Register 1. */ 4141 4142 /* 68ec040 versions of same */ 4143 { "iacr0", ITT0 }, /* Instruction Access Control Register 0. */ 4144 { "iacr1", ITT1 }, /* Instruction Access Control Register 0. */ 4145 { "dacr0", DTT0 }, /* Data Access Control Register 0. */ 4146 { "dacr1", DTT1 }, /* Data Access Control Register 0. */ 4147 4148 /* Coldfire versions of same. The ColdFire programmer's reference 4149 manual indicated that the order is 2,3,0,1, but Ken Rose 4150 <rose (at) netcom.com> says that 0,1,2,3 is the correct order. */ 4151 { "acr0", ACR0 }, /* Access Control Unit 0. */ 4152 { "acr1", ACR1 }, /* Access Control Unit 1. */ 4153 { "acr2", ACR2 }, /* Access Control Unit 2. */ 4154 { "acr3", ACR3 }, /* Access Control Unit 3. */ 4155 { "acr4", ACR4 }, /* Access Control Unit 4. */ 4156 { "acr5", ACR5 }, /* Access Control Unit 5. */ 4157 { "acr6", ACR6 }, /* Access Control Unit 6. */ 4158 { "acr7", ACR7 }, /* Access Control Unit 7. */ 4159 4160 { "tc", TC }, /* MMU Translation Control Register. */ 4161 { "tcr", TC }, 4162 { "asid", ASID }, 4163 4164 { "mmusr", MMUSR }, /* MMU Status Register. */ 4165 { "srp", SRP }, /* User Root Pointer. */ 4166 { "urp", URP }, /* Supervisor Root Pointer. */ 4167 4168 { "buscr", BUSCR }, 4169 { "mmubar", MMUBAR }, 4170 { "pcr", PCR }, 4171 4172 { "rombar", ROMBAR }, /* ROM Base Address Register. */ 4173 { "rambar0", RAMBAR0 }, /* ROM Base Address Register. */ 4174 { "rambar1", RAMBAR1 }, /* ROM Base Address Register. */ 4175 { "mbar", MBAR }, /* Module Base Address Register. */ 4176 4177 { "mbar0", MBAR0 }, /* mcfv4e registers. */ 4178 { "mbar1", MBAR1 }, /* mcfv4e registers. */ 4179 { "rombar0", ROMBAR0 }, /* mcfv4e registers. */ 4180 { "rombar1", ROMBAR1 }, /* mcfv4e registers. */ 4181 { "mpcr", MPCR }, /* mcfv4e registers. */ 4182 { "edrambar", EDRAMBAR }, /* mcfv4e registers. */ 4183 { "secmbar", SECMBAR }, /* mcfv4e registers. */ 4184 { "asid", TC }, /* mcfv4e registers. */ 4185 { "mmubar", BUSCR }, /* mcfv4e registers. */ 4186 { "pcr1u0", PCR1U0 }, /* mcfv4e registers. */ 4187 { "pcr1l0", PCR1L0 }, /* mcfv4e registers. */ 4188 { "pcr2u0", PCR2U0 }, /* mcfv4e registers. */ 4189 { "pcr2l0", PCR2L0 }, /* mcfv4e registers. */ 4190 { "pcr3u0", PCR3U0 }, /* mcfv4e registers. */ 4191 { "pcr3l0", PCR3L0 }, /* mcfv4e registers. */ 4192 { "pcr1u1", PCR1U1 }, /* mcfv4e registers. */ 4193 { "pcr1l1", PCR1L1 }, /* mcfv4e registers. */ 4194 { "pcr2u1", PCR2U1 }, /* mcfv4e registers. */ 4195 { "pcr2l1", PCR2L1 }, /* mcfv4e registers. */ 4196 { "pcr3u1", PCR3U1 }, /* mcfv4e registers. */ 4197 { "pcr3l1", PCR3L1 }, /* mcfv4e registers. */ 4198 4199 { "flashbar", FLASHBAR }, /* mcf528x registers. */ 4200 { "rambar", RAMBAR }, /* mcf528x registers. */ 4201 4202 { "mbar2", MBAR2 }, /* mcf5249 registers. */ 4203 4204 { "rgpiobar", RGPIOBAR }, /* mcf54418 registers. */ 4205 4206 { "cac", CAC }, /* fido registers. */ 4207 { "mbb", MBO }, /* fido registers (obsolete). */ 4208 { "mbo", MBO }, /* fido registers. */ 4209 /* End of control registers. */ 4210 4211 { "ac", AC }, 4212 { "bc", BC }, 4213 { "cal", CAL }, 4214 { "crp", CRP }, 4215 { "drp", DRP }, 4216 { "pcsr", PCSR }, 4217 { "psr", PSR }, 4218 { "scc", SCC }, 4219 { "val", VAL }, 4220 { "bad0", BAD0 }, 4221 { "bad1", BAD1 }, 4222 { "bad2", BAD2 }, 4223 { "bad3", BAD3 }, 4224 { "bad4", BAD4 }, 4225 { "bad5", BAD5 }, 4226 { "bad6", BAD6 }, 4227 { "bad7", BAD7 }, 4228 { "bac0", BAC0 }, 4229 { "bac1", BAC1 }, 4230 { "bac2", BAC2 }, 4231 { "bac3", BAC3 }, 4232 { "bac4", BAC4 }, 4233 { "bac5", BAC5 }, 4234 { "bac6", BAC6 }, 4235 { "bac7", BAC7 }, 4236 4237 { "ic", IC }, 4238 { "dc", DC }, 4239 { "nc", NC }, 4240 4241 { "tt0", TT0 }, 4242 { "tt1", TT1 }, 4243 /* 68ec030 versions of same. */ 4244 { "ac0", TT0 }, 4245 { "ac1", TT1 }, 4246 /* 68ec030 access control unit, identical to 030 MMU status reg. */ 4247 { "acusr", PSR }, 4248 4249 /* Suppressed data and address registers. */ 4250 { "zd0", ZDATA0 }, 4251 { "zd1", ZDATA1 }, 4252 { "zd2", ZDATA2 }, 4253 { "zd3", ZDATA3 }, 4254 { "zd4", ZDATA4 }, 4255 { "zd5", ZDATA5 }, 4256 { "zd6", ZDATA6 }, 4257 { "zd7", ZDATA7 }, 4258 { "za0", ZADDR0 }, 4259 { "za1", ZADDR1 }, 4260 { "za2", ZADDR2 }, 4261 { "za3", ZADDR3 }, 4262 { "za4", ZADDR4 }, 4263 { "za5", ZADDR5 }, 4264 { "za6", ZADDR6 }, 4265 { "za7", ZADDR7 }, 4266 4267 /* Upper and lower data and address registers, used by macw and msacw. */ 4268 { "d0l", DATA0L }, 4269 { "d1l", DATA1L }, 4270 { "d2l", DATA2L }, 4271 { "d3l", DATA3L }, 4272 { "d4l", DATA4L }, 4273 { "d5l", DATA5L }, 4274 { "d6l", DATA6L }, 4275 { "d7l", DATA7L }, 4276 4277 { "a0l", ADDR0L }, 4278 { "a1l", ADDR1L }, 4279 { "a2l", ADDR2L }, 4280 { "a3l", ADDR3L }, 4281 { "a4l", ADDR4L }, 4282 { "a5l", ADDR5L }, 4283 { "a6l", ADDR6L }, 4284 { "a7l", ADDR7L }, 4285 4286 { "d0u", DATA0U }, 4287 { "d1u", DATA1U }, 4288 { "d2u", DATA2U }, 4289 { "d3u", DATA3U }, 4290 { "d4u", DATA4U }, 4291 { "d5u", DATA5U }, 4292 { "d6u", DATA6U }, 4293 { "d7u", DATA7U }, 4294 4295 { "a0u", ADDR0U }, 4296 { "a1u", ADDR1U }, 4297 { "a2u", ADDR2U }, 4298 { "a3u", ADDR3U }, 4299 { "a4u", ADDR4U }, 4300 { "a5u", ADDR5U }, 4301 { "a6u", ADDR6U }, 4302 { "a7u", ADDR7U }, 4303 4304 { 0, 0 } 4305 }; 4306 4307 static void 4308 init_regtable (void) 4309 { 4310 int i; 4311 for (i = 0; init_table[i].name; i++) 4312 insert_reg (init_table[i].name, init_table[i].number); 4313 } 4314 4315 void 4316 md_assemble (char *str) 4317 { 4318 const char *er; 4319 short *fromP; 4320 char *toP = NULL; 4321 int m, n = 0; 4322 char *to_beg_P; 4323 int shorts_this_frag; 4324 fixS *fixP; 4325 4326 if (!selected_cpu && !selected_arch) 4327 { 4328 /* We've not selected an architecture yet. Set the default 4329 now. We do this lazily so that an initial .cpu or .arch directive 4330 can specify. */ 4331 if (!m68k_set_cpu (TARGET_CPU, 1, 1)) 4332 as_bad (_("unrecognized default cpu `%s'"), TARGET_CPU); 4333 } 4334 if (!initialized) 4335 m68k_init_arch (); 4336 4337 /* In MRI mode, the instruction and operands are separated by a 4338 space. Anything following the operands is a comment. The label 4339 has already been removed. */ 4340 if (flag_mri) 4341 { 4342 char *s; 4343 int fields = 0; 4344 int infield = 0; 4345 int inquote = 0; 4346 4347 for (s = str; *s != '\0'; s++) 4348 { 4349 if ((*s == ' ' || *s == '\t') && ! inquote) 4350 { 4351 if (infield) 4352 { 4353 ++fields; 4354 if (fields >= 2) 4355 { 4356 *s = '\0'; 4357 break; 4358 } 4359 infield = 0; 4360 } 4361 } 4362 else 4363 { 4364 if (! infield) 4365 infield = 1; 4366 if (*s == '\'') 4367 inquote = ! inquote; 4368 } 4369 } 4370 } 4371 4372 memset (&the_ins, '\0', sizeof (the_ins)); 4373 m68k_ip (str); 4374 er = the_ins.error; 4375 if (!er) 4376 { 4377 for (n = 0; n < the_ins.numargs; n++) 4378 if (the_ins.operands[n].error) 4379 { 4380 er = the_ins.operands[n].error; 4381 break; 4382 } 4383 } 4384 if (er) 4385 { 4386 as_bad (_("%s -- statement `%s' ignored"), er, str); 4387 return; 4388 } 4389 4390 /* If there is a current label, record that it marks an instruction. */ 4391 if (current_label != NULL) 4392 { 4393 current_label->text = 1; 4394 current_label = NULL; 4395 } 4396 4397 #ifdef OBJ_ELF 4398 /* Tie dwarf2 debug info to the address at the start of the insn. */ 4399 dwarf2_emit_insn (0); 4400 #endif 4401 4402 if (the_ins.nfrag == 0) 4403 { 4404 /* No frag hacking involved; just put it out. */ 4405 toP = frag_more (2 * the_ins.numo); 4406 fromP = &the_ins.opcode[0]; 4407 for (m = the_ins.numo; m; --m) 4408 { 4409 md_number_to_chars (toP, (long) (*fromP), 2); 4410 toP += 2; 4411 fromP++; 4412 } 4413 /* Put out symbol-dependent info. */ 4414 for (m = 0; m < the_ins.nrel; m++) 4415 { 4416 switch (the_ins.reloc[m].wid) 4417 { 4418 case 'B': 4419 n = 1; 4420 break; 4421 case 'b': 4422 n = 1; 4423 break; 4424 case '3': 4425 n = 1; 4426 break; 4427 case 'w': 4428 case 'W': 4429 n = 2; 4430 break; 4431 case 'l': 4432 n = 4; 4433 break; 4434 default: 4435 as_fatal (_("Don't know how to figure width of %c in md_assemble()"), 4436 the_ins.reloc[m].wid); 4437 } 4438 4439 fixP = fix_new_exp (frag_now, 4440 ((toP - frag_now->fr_literal) 4441 - the_ins.numo * 2 + the_ins.reloc[m].n), 4442 n, 4443 &the_ins.reloc[m].exp, 4444 the_ins.reloc[m].pcrel, 4445 get_reloc_code (n, the_ins.reloc[m].pcrel, 4446 the_ins.reloc[m].pic_reloc)); 4447 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix; 4448 if (the_ins.reloc[m].wid == 'B') 4449 fixP->fx_signed = 1; 4450 } 4451 return; 4452 } 4453 4454 /* There's some frag hacking. */ 4455 { 4456 /* Calculate the max frag size. */ 4457 int wid; 4458 4459 wid = 2 * the_ins.fragb[0].fragoff; 4460 for (n = 1; n < the_ins.nfrag; n++) 4461 wid += 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff); 4462 /* frag_var part. */ 4463 wid += FRAG_VAR_SIZE; 4464 /* Make sure the whole insn fits in one chunk, in particular that 4465 the var part is attached, as we access one byte before the 4466 variable frag for byte branches. */ 4467 frag_grow (wid); 4468 } 4469 4470 for (n = 0, fromP = &the_ins.opcode[0]; n < the_ins.nfrag; n++) 4471 { 4472 int wid; 4473 4474 if (n == 0) 4475 wid = 2 * the_ins.fragb[n].fragoff; 4476 else 4477 wid = 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff); 4478 toP = frag_more (wid); 4479 to_beg_P = toP; 4480 shorts_this_frag = 0; 4481 for (m = wid / 2; m; --m) 4482 { 4483 md_number_to_chars (toP, (long) (*fromP), 2); 4484 toP += 2; 4485 fromP++; 4486 shorts_this_frag++; 4487 } 4488 for (m = 0; m < the_ins.nrel; m++) 4489 { 4490 if ((the_ins.reloc[m].n) >= 2 * shorts_this_frag) 4491 { 4492 the_ins.reloc[m].n -= 2 * shorts_this_frag; 4493 break; 4494 } 4495 wid = the_ins.reloc[m].wid; 4496 if (wid == 0) 4497 continue; 4498 the_ins.reloc[m].wid = 0; 4499 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000; 4500 4501 fixP = fix_new_exp (frag_now, 4502 ((toP - frag_now->fr_literal) 4503 - the_ins.numo * 2 + the_ins.reloc[m].n), 4504 wid, 4505 &the_ins.reloc[m].exp, 4506 the_ins.reloc[m].pcrel, 4507 get_reloc_code (wid, the_ins.reloc[m].pcrel, 4508 the_ins.reloc[m].pic_reloc)); 4509 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix; 4510 } 4511 (void) frag_var (rs_machine_dependent, FRAG_VAR_SIZE, 0, 4512 (relax_substateT) (the_ins.fragb[n].fragty), 4513 the_ins.fragb[n].fadd, the_ins.fragb[n].foff, to_beg_P); 4514 } 4515 gas_assert (the_ins.nfrag >= 1); 4516 n = the_ins.numo - the_ins.fragb[the_ins.nfrag - 1].fragoff; 4517 shorts_this_frag = 0; 4518 if (n) 4519 { 4520 toP = frag_more (n * 2); 4521 while (n--) 4522 { 4523 md_number_to_chars (toP, (long) (*fromP), 2); 4524 toP += 2; 4525 fromP++; 4526 shorts_this_frag++; 4527 } 4528 } 4529 for (m = 0; m < the_ins.nrel; m++) 4530 { 4531 int wid; 4532 4533 wid = the_ins.reloc[m].wid; 4534 if (wid == 0) 4535 continue; 4536 the_ins.reloc[m].wid = 0; 4537 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000; 4538 4539 fixP = fix_new_exp (frag_now, 4540 ((the_ins.reloc[m].n + toP - frag_now->fr_literal) 4541 - shorts_this_frag * 2), 4542 wid, 4543 &the_ins.reloc[m].exp, 4544 the_ins.reloc[m].pcrel, 4545 get_reloc_code (wid, the_ins.reloc[m].pcrel, 4546 the_ins.reloc[m].pic_reloc)); 4547 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix; 4548 } 4549 } 4550 4551 /* Comparison function used by qsort to rank the opcode entries by name. */ 4552 4553 static int 4554 m68k_compare_opcode (const void * v1, const void * v2) 4555 { 4556 struct m68k_opcode * op1, * op2; 4557 int ret; 4558 4559 if (v1 == v2) 4560 return 0; 4561 4562 op1 = *(struct m68k_opcode **) v1; 4563 op2 = *(struct m68k_opcode **) v2; 4564 4565 /* Compare the two names. If different, return the comparison. 4566 If the same, return the order they are in the opcode table. */ 4567 ret = strcmp (op1->name, op2->name); 4568 if (ret) 4569 return ret; 4570 if (op1 < op2) 4571 return -1; 4572 return 1; 4573 } 4574 4575 void 4576 md_begin (void) 4577 { 4578 const struct m68k_opcode *ins; 4579 struct m68k_incant *hack, *slak; 4580 const char *retval = 0; /* Empty string, or error msg text. */ 4581 int i; 4582 4583 /* Set up hash tables with 68000 instructions. 4584 similar to what the vax assembler does. */ 4585 /* RMS claims the thing to do is take the m68k-opcode.h table, and make 4586 a copy of it at runtime, adding in the information we want but isn't 4587 there. I think it'd be better to have an awk script hack the table 4588 at compile time. Or even just xstr the table and use it as-is. But 4589 my lord ghod hath spoken, so we do it this way. Excuse the ugly var 4590 names. */ 4591 4592 if (flag_mri) 4593 { 4594 flag_reg_prefix_optional = 1; 4595 m68k_abspcadd = 1; 4596 if (! m68k_rel32_from_cmdline) 4597 m68k_rel32 = 0; 4598 } 4599 4600 /* First sort the opcode table into alphabetical order to seperate 4601 the order that the assembler wants to see the opcodes from the 4602 order that the disassembler wants to see them. */ 4603 m68k_sorted_opcodes = XNEWVEC (const struct m68k_opcode *, m68k_numopcodes); 4604 4605 for (i = m68k_numopcodes; i--;) 4606 m68k_sorted_opcodes[i] = m68k_opcodes + i; 4607 4608 qsort (m68k_sorted_opcodes, m68k_numopcodes, 4609 sizeof (m68k_sorted_opcodes[0]), m68k_compare_opcode); 4610 4611 op_hash = hash_new (); 4612 4613 obstack_begin (&robyn, 4000); 4614 for (i = 0; i < m68k_numopcodes; i++) 4615 { 4616 hack = slak = XOBNEW (&robyn, struct m68k_incant); 4617 do 4618 { 4619 ins = m68k_sorted_opcodes[i]; 4620 4621 /* We must enter all insns into the table, because .arch and 4622 .cpu directives can change things. */ 4623 slak->m_operands = ins->args; 4624 slak->m_arch = ins->arch; 4625 slak->m_opcode = ins->opcode; 4626 4627 /* In most cases we can determine the number of opcode words 4628 by checking the second word of the mask. Unfortunately 4629 some instructions have 2 opcode words, but no fixed bits 4630 in the second word. A leading dot in the operands 4631 string also indicates 2 opcodes. */ 4632 if (*slak->m_operands == '.') 4633 { 4634 slak->m_operands++; 4635 slak->m_codenum = 2; 4636 } 4637 else if (ins->match & 0xffffL) 4638 slak->m_codenum = 2; 4639 else 4640 slak->m_codenum = 1; 4641 slak->m_opnum = strlen (slak->m_operands) / 2; 4642 4643 if (i + 1 != m68k_numopcodes 4644 && !strcmp (ins->name, m68k_sorted_opcodes[i + 1]->name)) 4645 { 4646 slak->m_next = XOBNEW (&robyn, struct m68k_incant); 4647 i++; 4648 } 4649 else 4650 slak->m_next = 0; 4651 slak = slak->m_next; 4652 } 4653 while (slak); 4654 4655 retval = hash_insert (op_hash, ins->name, (char *) hack); 4656 if (retval) 4657 as_fatal (_("Internal Error: Can't hash %s: %s"), ins->name, retval); 4658 } 4659 4660 for (i = 0; i < m68k_numaliases; i++) 4661 { 4662 const char *name = m68k_opcode_aliases[i].primary; 4663 const char *alias = m68k_opcode_aliases[i].alias; 4664 void *val = hash_find (op_hash, name); 4665 4666 if (!val) 4667 as_fatal (_("Internal Error: Can't find %s in hash table"), name); 4668 retval = hash_insert (op_hash, alias, val); 4669 if (retval) 4670 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval); 4671 } 4672 4673 /* In MRI mode, all unsized branches are variable sized. Normally, 4674 they are word sized. */ 4675 if (flag_mri) 4676 { 4677 static struct m68k_opcode_alias mri_aliases[] = 4678 { 4679 { "bhi", "jhi", }, 4680 { "bls", "jls", }, 4681 { "bcc", "jcc", }, 4682 { "bcs", "jcs", }, 4683 { "bne", "jne", }, 4684 { "beq", "jeq", }, 4685 { "bvc", "jvc", }, 4686 { "bvs", "jvs", }, 4687 { "bpl", "jpl", }, 4688 { "bmi", "jmi", }, 4689 { "bge", "jge", }, 4690 { "blt", "jlt", }, 4691 { "bgt", "jgt", }, 4692 { "ble", "jle", }, 4693 { "bra", "jra", }, 4694 { "bsr", "jbsr", }, 4695 }; 4696 4697 for (i = 0; 4698 i < (int) (sizeof mri_aliases / sizeof mri_aliases[0]); 4699 i++) 4700 { 4701 const char *name = mri_aliases[i].primary; 4702 const char *alias = mri_aliases[i].alias; 4703 void *val = hash_find (op_hash, name); 4704 4705 if (!val) 4706 as_fatal (_("Internal Error: Can't find %s in hash table"), name); 4707 retval = hash_jam (op_hash, alias, val); 4708 if (retval) 4709 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval); 4710 } 4711 } 4712 4713 for (i = 0; i < (int) sizeof (notend_table); i++) 4714 { 4715 notend_table[i] = 0; 4716 alt_notend_table[i] = 0; 4717 } 4718 4719 notend_table[','] = 1; 4720 notend_table['{'] = 1; 4721 notend_table['}'] = 1; 4722 alt_notend_table['a'] = 1; 4723 alt_notend_table['A'] = 1; 4724 alt_notend_table['d'] = 1; 4725 alt_notend_table['D'] = 1; 4726 alt_notend_table['#'] = 1; 4727 alt_notend_table['&'] = 1; 4728 alt_notend_table['f'] = 1; 4729 alt_notend_table['F'] = 1; 4730 #ifdef REGISTER_PREFIX 4731 alt_notend_table[REGISTER_PREFIX] = 1; 4732 #endif 4733 4734 /* We need to put '(' in alt_notend_table to handle 4735 cas2 %d0:%d2,%d3:%d4,(%a0):(%a1) */ 4736 alt_notend_table['('] = 1; 4737 4738 /* We need to put '@' in alt_notend_table to handle 4739 cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1) */ 4740 alt_notend_table['@'] = 1; 4741 4742 /* We need to put digits in alt_notend_table to handle 4743 bfextu %d0{24:1},%d0 */ 4744 alt_notend_table['0'] = 1; 4745 alt_notend_table['1'] = 1; 4746 alt_notend_table['2'] = 1; 4747 alt_notend_table['3'] = 1; 4748 alt_notend_table['4'] = 1; 4749 alt_notend_table['5'] = 1; 4750 alt_notend_table['6'] = 1; 4751 alt_notend_table['7'] = 1; 4752 alt_notend_table['8'] = 1; 4753 alt_notend_table['9'] = 1; 4754 4755 #ifndef MIT_SYNTAX_ONLY 4756 /* Insert pseudo ops, these have to go into the opcode table since 4757 gas expects pseudo ops to start with a dot. */ 4758 { 4759 int n = 0; 4760 4761 while (mote_pseudo_table[n].poc_name) 4762 { 4763 hack = XOBNEW (&robyn, struct m68k_incant); 4764 hash_insert (op_hash, 4765 mote_pseudo_table[n].poc_name, (char *) hack); 4766 hack->m_operands = 0; 4767 hack->m_opnum = n; 4768 n++; 4769 } 4770 } 4771 #endif 4772 4773 init_regtable (); 4774 4775 #ifdef OBJ_ELF 4776 record_alignment (text_section, 2); 4777 record_alignment (data_section, 2); 4778 record_alignment (bss_section, 2); 4779 #endif 4780 } 4781 4782 4783 /* This is called when a label is defined. */ 4785 4786 void 4787 m68k_frob_label (symbolS *sym) 4788 { 4789 struct label_line *n; 4790 4791 n = XNEW (struct label_line); 4792 n->next = labels; 4793 n->label = sym; 4794 n->file = as_where (&n->line); 4795 n->text = 0; 4796 labels = n; 4797 current_label = n; 4798 4799 #ifdef OBJ_ELF 4800 dwarf2_emit_label (sym); 4801 #endif 4802 } 4803 4804 /* This is called when a value that is not an instruction is emitted. */ 4805 4806 void 4807 m68k_flush_pending_output (void) 4808 { 4809 current_label = NULL; 4810 } 4811 4812 /* This is called at the end of the assembly, when the final value of 4813 the label is known. We warn if this is a text symbol aligned at an 4814 odd location. */ 4815 4816 void 4817 m68k_frob_symbol (symbolS *sym) 4818 { 4819 if (S_GET_SEGMENT (sym) == reg_section 4820 && (int) S_GET_VALUE (sym) < 0) 4821 { 4822 S_SET_SEGMENT (sym, absolute_section); 4823 S_SET_VALUE (sym, ~(int)S_GET_VALUE (sym)); 4824 } 4825 else if ((S_GET_VALUE (sym) & 1) != 0) 4826 { 4827 struct label_line *l; 4828 4829 for (l = labels; l != NULL; l = l->next) 4830 { 4831 if (l->label == sym) 4832 { 4833 if (l->text) 4834 as_warn_where (l->file, l->line, 4835 _("text label `%s' aligned to odd boundary"), 4836 S_GET_NAME (sym)); 4837 break; 4838 } 4839 } 4840 } 4841 } 4842 4843 /* This is called if we go in or out of MRI mode because of the .mri 4845 pseudo-op. */ 4846 4847 void 4848 m68k_mri_mode_change (int on) 4849 { 4850 if (on) 4851 { 4852 if (! flag_reg_prefix_optional) 4853 { 4854 flag_reg_prefix_optional = 1; 4855 #ifdef REGISTER_PREFIX 4856 init_regtable (); 4857 #endif 4858 } 4859 m68k_abspcadd = 1; 4860 if (! m68k_rel32_from_cmdline) 4861 m68k_rel32 = 0; 4862 } 4863 else 4864 { 4865 if (! reg_prefix_optional_seen) 4866 { 4867 #ifdef REGISTER_PREFIX_OPTIONAL 4868 flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL; 4869 #else 4870 flag_reg_prefix_optional = 0; 4871 #endif 4872 #ifdef REGISTER_PREFIX 4873 init_regtable (); 4874 #endif 4875 } 4876 m68k_abspcadd = 0; 4877 if (! m68k_rel32_from_cmdline) 4878 m68k_rel32 = 1; 4879 } 4880 } 4881 4882 const char * 4883 md_atof (int type, char *litP, int *sizeP) 4884 { 4885 return ieee_md_atof (type, litP, sizeP, TRUE); 4886 } 4887 4888 void 4889 md_number_to_chars (char *buf, valueT val, int n) 4890 { 4891 number_to_chars_bigendian (buf, val, n); 4892 } 4893 4894 void 4895 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) 4896 { 4897 offsetT val = *valP; 4898 addressT upper_limit; 4899 offsetT lower_limit; 4900 4901 /* This is unnecessary but it convinces the native rs6000 compiler 4902 to generate the code we want. */ 4903 char *buf = fixP->fx_frag->fr_literal; 4904 buf += fixP->fx_where; 4905 /* End ibm compiler workaround. */ 4906 4907 val = SEXT (val); 4908 4909 if (fixP->fx_addsy == NULL && fixP->fx_pcrel == 0) 4910 fixP->fx_done = 1; 4911 4912 #ifdef OBJ_ELF 4913 if (fixP->fx_addsy) 4914 { 4915 memset (buf, 0, fixP->fx_size); 4916 fixP->fx_addnumber = val; /* Remember value for emit_reloc. */ 4917 4918 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT 4919 && !S_IS_DEFINED (fixP->fx_addsy) 4920 && !S_IS_WEAK (fixP->fx_addsy)) 4921 S_SET_WEAK (fixP->fx_addsy); 4922 4923 switch (fixP->fx_r_type) 4924 { 4925 case BFD_RELOC_68K_TLS_GD32: 4926 case BFD_RELOC_68K_TLS_GD16: 4927 case BFD_RELOC_68K_TLS_GD8: 4928 case BFD_RELOC_68K_TLS_LDM32: 4929 case BFD_RELOC_68K_TLS_LDM16: 4930 case BFD_RELOC_68K_TLS_LDM8: 4931 case BFD_RELOC_68K_TLS_LDO32: 4932 case BFD_RELOC_68K_TLS_LDO16: 4933 case BFD_RELOC_68K_TLS_LDO8: 4934 case BFD_RELOC_68K_TLS_IE32: 4935 case BFD_RELOC_68K_TLS_IE16: 4936 case BFD_RELOC_68K_TLS_IE8: 4937 case BFD_RELOC_68K_TLS_LE32: 4938 case BFD_RELOC_68K_TLS_LE16: 4939 case BFD_RELOC_68K_TLS_LE8: 4940 S_SET_THREAD_LOCAL (fixP->fx_addsy); 4941 break; 4942 4943 default: 4944 break; 4945 } 4946 4947 return; 4948 } 4949 #elif defined(OBJ_AOUT) 4950 /* PR gas/3041 Do not fix frags referencing a weak symbol. */ 4951 if (fixP->fx_addsy && S_IS_WEAK (fixP->fx_addsy)) 4952 { 4953 memset (buf, 0, fixP->fx_size); 4954 fixP->fx_addnumber = val; /* Remember value for emit_reloc. */ 4955 return; 4956 } 4957 #endif 4958 4959 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT 4960 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) 4961 return; 4962 4963 switch (fixP->fx_size) 4964 { 4965 /* The cast to offsetT below are necessary to make code 4966 correct for machines where ints are smaller than offsetT. */ 4967 case 1: 4968 *buf++ = val; 4969 upper_limit = 0x7f; 4970 lower_limit = - (offsetT) 0x80; 4971 break; 4972 case 2: 4973 *buf++ = (val >> 8); 4974 *buf++ = val; 4975 upper_limit = 0x7fff; 4976 lower_limit = - (offsetT) 0x8000; 4977 break; 4978 case 4: 4979 *buf++ = (val >> 24); 4980 *buf++ = (val >> 16); 4981 *buf++ = (val >> 8); 4982 *buf++ = val; 4983 upper_limit = 0x7fffffff; 4984 lower_limit = - (offsetT) 0x7fffffff - 1; /* Avoid constant overflow. */ 4985 break; 4986 default: 4987 BAD_CASE (fixP->fx_size); 4988 } 4989 4990 /* Fix up a negative reloc. */ 4991 if (fixP->fx_addsy == NULL && fixP->fx_subsy != NULL) 4992 { 4993 fixP->fx_addsy = fixP->fx_subsy; 4994 fixP->fx_subsy = NULL; 4995 fixP->fx_tcbit = 1; 4996 } 4997 4998 /* For non-pc-relative values, it's conceivable we might get something 4999 like "0xff" for a byte field. So extend the upper part of the range 5000 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff", 5001 so that we can do any range checking at all. */ 5002 if (! fixP->fx_pcrel && ! fixP->fx_signed) 5003 upper_limit = upper_limit * 2 + 1; 5004 5005 if ((addressT) val > upper_limit 5006 && (val > 0 || val < lower_limit)) 5007 as_bad_where (fixP->fx_file, fixP->fx_line, 5008 _("value %ld out of range"), (long)val); 5009 5010 /* A one byte PC-relative reloc means a short branch. We can't use 5011 a short branch with a value of 0 or -1, because those indicate 5012 different opcodes (branches with longer offsets). fixup_segment 5013 in write.c may have clobbered fx_pcrel, so we need to examine the 5014 reloc type. */ 5015 if ((fixP->fx_pcrel 5016 || fixP->fx_r_type == BFD_RELOC_8_PCREL) 5017 && fixP->fx_size == 1 5018 && (fixP->fx_addsy == NULL 5019 || S_IS_DEFINED (fixP->fx_addsy)) 5020 && (val == 0 || val == -1)) 5021 as_bad_where (fixP->fx_file, fixP->fx_line, 5022 _("invalid byte branch offset")); 5023 } 5024 5025 /* *fragP has been relaxed to its final size, and now needs to have 5026 the bytes inside it modified to conform to the new size There is UGLY 5027 MAGIC here. .. 5028 */ 5029 static void 5030 md_convert_frag_1 (fragS *fragP) 5031 { 5032 long disp; 5033 fixS *fixP = NULL; 5034 5035 /* Address in object code of the displacement. */ 5036 int object_address = fragP->fr_fix + fragP->fr_address; 5037 5038 /* Address in gas core of the place to store the displacement. */ 5039 /* This convinces the native rs6000 compiler to generate the code we 5040 want. */ 5041 char *buffer_address = fragP->fr_literal; 5042 buffer_address += fragP->fr_fix; 5043 /* End ibm compiler workaround. */ 5044 5045 /* The displacement of the address, from current location. */ 5046 disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0; 5047 disp = (disp + fragP->fr_offset) - object_address; 5048 5049 switch (fragP->fr_subtype) 5050 { 5051 case TAB (BRANCHBWL, BYTE): 5052 case TAB (BRABSJUNC, BYTE): 5053 case TAB (BRABSJCOND, BYTE): 5054 case TAB (BRANCHBW, BYTE): 5055 case TAB (BRANCHBWPL, BYTE): 5056 know (issbyte (disp)); 5057 if (disp == 0) 5058 as_bad_where (fragP->fr_file, fragP->fr_line, 5059 _("short branch with zero offset: use :w")); 5060 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol, 5061 fragP->fr_offset, 1, RELAX_RELOC_PC8); 5062 fixP->fx_pcrel_adjust = -1; 5063 break; 5064 case TAB (BRANCHBWL, SHORT): 5065 case TAB (BRABSJUNC, SHORT): 5066 case TAB (BRABSJCOND, SHORT): 5067 case TAB (BRANCHBW, SHORT): 5068 case TAB (BRANCHBWPL, SHORT): 5069 fragP->fr_opcode[1] = 0x00; 5070 fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, 5071 fragP->fr_offset, 1, RELAX_RELOC_PC16); 5072 fragP->fr_fix += 2; 5073 break; 5074 case TAB (BRANCHBWL, LONG): 5075 fragP->fr_opcode[1] = (char) 0xFF; 5076 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, 5077 fragP->fr_offset, 1, RELAX_RELOC_PC32); 5078 fragP->fr_fix += 4; 5079 break; 5080 case TAB (BRANCHBWPL, LONG): 5081 /* Here we are converting an unconditional branch into a pair of 5082 conditional branches, in order to get the range. */ 5083 fragP->fr_opcode[0] = 0x66; /* bne */ 5084 fragP->fr_opcode[1] = 0xFF; 5085 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, 5086 fragP->fr_offset, 1, RELAX_RELOC_PC32); 5087 fixP->fx_file = fragP->fr_file; 5088 fixP->fx_line = fragP->fr_line; 5089 fragP->fr_fix += 4; /* Skip first offset */ 5090 buffer_address += 4; 5091 *buffer_address++ = 0x67; /* beq */ 5092 *buffer_address++ = 0xff; 5093 fragP->fr_fix += 2; /* Skip second branch opcode */ 5094 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, 5095 fragP->fr_offset, 1, RELAX_RELOC_PC32); 5096 fragP->fr_fix += 4; 5097 break; 5098 case TAB (BRABSJUNC, LONG): 5099 if (fragP->fr_opcode[0] == 0x61) /* jbsr */ 5100 { 5101 if (flag_keep_pcrel) 5102 as_bad_where (fragP->fr_file, fragP->fr_line, 5103 _("Conversion of PC relative BSR to absolute JSR")); 5104 fragP->fr_opcode[0] = 0x4E; 5105 fragP->fr_opcode[1] = (char) 0xB9; /* JSR with ABSL LONG operand. */ 5106 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, 5107 fragP->fr_offset, 0, RELAX_RELOC_ABS32); 5108 fragP->fr_fix += 4; 5109 } 5110 else if (fragP->fr_opcode[0] == 0x60) /* jbra */ 5111 { 5112 if (flag_keep_pcrel) 5113 as_bad_where (fragP->fr_file, fragP->fr_line, 5114 _("Conversion of PC relative branch to absolute jump")); 5115 fragP->fr_opcode[0] = 0x4E; 5116 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG operand. */ 5117 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, 5118 fragP->fr_offset, 0, RELAX_RELOC_ABS32); 5119 fragP->fr_fix += 4; 5120 } 5121 else 5122 { 5123 /* This cannot happen, because jbsr and jbra are the only two 5124 unconditional branches. */ 5125 abort (); 5126 } 5127 break; 5128 case TAB (BRABSJCOND, LONG): 5129 if (flag_keep_pcrel) 5130 as_bad_where (fragP->fr_file, fragP->fr_line, 5131 _("Conversion of PC relative conditional branch to absolute jump")); 5132 5133 /* Only Bcc 68000 instructions can come here 5134 Change bcc into b!cc/jmp absl long. */ 5135 fragP->fr_opcode[0] ^= 0x01; /* Invert bcc. */ 5136 fragP->fr_opcode[1] = 0x06; /* Branch offset = 6. */ 5137 5138 /* JF: these used to be fr_opcode[2,3], but they may be in a 5139 different frag, in which case referring to them is a no-no. 5140 Only fr_opcode[0,1] are guaranteed to work. */ 5141 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */ 5142 *buffer_address++ = (char) 0xf9; 5143 fragP->fr_fix += 2; /* Account for jmp instruction. */ 5144 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, 5145 fragP->fr_offset, 0, RELAX_RELOC_ABS32); 5146 fragP->fr_fix += 4; 5147 break; 5148 case TAB (FBRANCH, SHORT): 5149 know ((fragP->fr_opcode[1] & 0x40) == 0); 5150 fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, 5151 fragP->fr_offset, 1, RELAX_RELOC_PC16); 5152 fragP->fr_fix += 2; 5153 break; 5154 case TAB (FBRANCH, LONG): 5155 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit. */ 5156 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, 5157 fragP->fr_offset, 1, RELAX_RELOC_PC32); 5158 fragP->fr_fix += 4; 5159 break; 5160 case TAB (DBCCLBR, SHORT): 5161 case TAB (DBCCABSJ, SHORT): 5162 fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, 5163 fragP->fr_offset, 1, RELAX_RELOC_PC16); 5164 fragP->fr_fix += 2; 5165 break; 5166 case TAB (DBCCLBR, LONG): 5167 /* Only DBcc instructions can come here. 5168 Change dbcc into dbcc/bral. 5169 JF: these used to be fr_opcode[2-7], but that's wrong. */ 5170 *buffer_address++ = 0x00; /* Branch offset = 4. */ 5171 *buffer_address++ = 0x04; 5172 *buffer_address++ = 0x60; /* Put in bra pc+6. */ 5173 *buffer_address++ = 0x06; 5174 *buffer_address++ = 0x60; /* Put in bral (0x60ff). */ 5175 *buffer_address++ = (char) 0xff; 5176 5177 fragP->fr_fix += 6; /* Account for bra/jmp instructions. */ 5178 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, 5179 fragP->fr_offset, 1, RELAX_RELOC_PC32); 5180 fragP->fr_fix += 4; 5181 break; 5182 case TAB (DBCCABSJ, LONG): 5183 /* Only DBcc instructions can come here. 5184 Change dbcc into dbcc/jmp. 5185 JF: these used to be fr_opcode[2-7], but that's wrong. */ 5186 if (flag_keep_pcrel) 5187 as_bad_where (fragP->fr_file, fragP->fr_line, 5188 _("Conversion of PC relative conditional branch to absolute jump")); 5189 5190 *buffer_address++ = 0x00; /* Branch offset = 4. */ 5191 *buffer_address++ = 0x04; 5192 *buffer_address++ = 0x60; /* Put in bra pc + 6. */ 5193 *buffer_address++ = 0x06; 5194 *buffer_address++ = 0x4e; /* Put in jmp long (0x4ef9). */ 5195 *buffer_address++ = (char) 0xf9; 5196 5197 fragP->fr_fix += 6; /* Account for bra/jmp instructions. */ 5198 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, 5199 fragP->fr_offset, 0, RELAX_RELOC_ABS32); 5200 fragP->fr_fix += 4; 5201 break; 5202 case TAB (PCREL1632, SHORT): 5203 fragP->fr_opcode[1] &= ~0x3F; 5204 fragP->fr_opcode[1] |= 0x3A; /* 072 - mode 7.2 */ 5205 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol, 5206 fragP->fr_offset, 1, RELAX_RELOC_PC16); 5207 fragP->fr_fix += 2; 5208 break; 5209 case TAB (PCREL1632, LONG): 5210 /* Already set to mode 7.3; this indicates: PC indirect with 5211 suppressed index, 32-bit displacement. */ 5212 *buffer_address++ = 0x01; 5213 *buffer_address++ = 0x70; 5214 fragP->fr_fix += 2; 5215 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol, 5216 fragP->fr_offset, 1, RELAX_RELOC_PC32); 5217 fixP->fx_pcrel_adjust = 2; 5218 fragP->fr_fix += 4; 5219 break; 5220 case TAB (PCINDEX, BYTE): 5221 gas_assert (fragP->fr_fix >= 2); 5222 buffer_address[-2] &= ~1; 5223 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol, 5224 fragP->fr_offset, 1, RELAX_RELOC_PC8); 5225 fixP->fx_pcrel_adjust = 1; 5226 break; 5227 case TAB (PCINDEX, SHORT): 5228 gas_assert (fragP->fr_fix >= 2); 5229 buffer_address[-2] |= 0x1; 5230 buffer_address[-1] = 0x20; 5231 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol, 5232 fragP->fr_offset, 1, RELAX_RELOC_PC16); 5233 fixP->fx_pcrel_adjust = 2; 5234 fragP->fr_fix += 2; 5235 break; 5236 case TAB (PCINDEX, LONG): 5237 gas_assert (fragP->fr_fix >= 2); 5238 buffer_address[-2] |= 0x1; 5239 buffer_address[-1] = 0x30; 5240 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol, 5241 fragP->fr_offset, 1, RELAX_RELOC_PC32); 5242 fixP->fx_pcrel_adjust = 2; 5243 fragP->fr_fix += 4; 5244 break; 5245 case TAB (ABSTOPCREL, SHORT): 5246 fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, 5247 fragP->fr_offset, 1, RELAX_RELOC_PC16); 5248 fragP->fr_fix += 2; 5249 break; 5250 case TAB (ABSTOPCREL, LONG): 5251 if (flag_keep_pcrel) 5252 as_bad_where (fragP->fr_file, fragP->fr_line, 5253 _("Conversion of PC relative displacement to absolute")); 5254 /* The thing to do here is force it to ABSOLUTE LONG, since 5255 ABSTOPCREL is really trying to shorten an ABSOLUTE address anyway. */ 5256 if ((fragP->fr_opcode[1] & 0x3F) != 0x3A) 5257 abort (); 5258 fragP->fr_opcode[1] &= ~0x3F; 5259 fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */ 5260 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, 5261 fragP->fr_offset, 0, RELAX_RELOC_ABS32); 5262 fragP->fr_fix += 4; 5263 break; 5264 } 5265 if (fixP) 5266 { 5267 fixP->fx_file = fragP->fr_file; 5268 fixP->fx_line = fragP->fr_line; 5269 } 5270 } 5271 5272 void 5273 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, 5274 segT sec ATTRIBUTE_UNUSED, 5275 fragS *fragP) 5276 { 5277 md_convert_frag_1 (fragP); 5278 } 5279 5280 /* Force truly undefined symbols to their maximum size, and generally set up 5281 the frag list to be relaxed 5282 */ 5283 int 5284 md_estimate_size_before_relax (fragS *fragP, segT segment) 5285 { 5286 /* Handle SZ_UNDEF first, it can be changed to BYTE or SHORT. */ 5287 switch (fragP->fr_subtype) 5288 { 5289 case TAB (BRANCHBWL, SZ_UNDEF): 5290 case TAB (BRANCHBWPL, SZ_UNDEF): 5291 case TAB (BRABSJUNC, SZ_UNDEF): 5292 case TAB (BRABSJCOND, SZ_UNDEF): 5293 { 5294 if (S_GET_SEGMENT (fragP->fr_symbol) == segment 5295 && relaxable_symbol (fragP->fr_symbol)) 5296 { 5297 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE); 5298 } 5299 else if (flag_short_refs) 5300 { 5301 /* Symbol is undefined and we want short ref. */ 5302 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT); 5303 } 5304 else 5305 { 5306 /* Symbol is still undefined. Make it LONG. */ 5307 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG); 5308 } 5309 break; 5310 } 5311 5312 case TAB (BRANCHBW, SZ_UNDEF): 5313 { 5314 if (S_GET_SEGMENT (fragP->fr_symbol) == segment 5315 && relaxable_symbol (fragP->fr_symbol)) 5316 { 5317 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE); 5318 } 5319 else 5320 { 5321 /* Symbol is undefined and we don't have long branches. */ 5322 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT); 5323 } 5324 break; 5325 } 5326 5327 case TAB (FBRANCH, SZ_UNDEF): 5328 case TAB (DBCCLBR, SZ_UNDEF): 5329 case TAB (DBCCABSJ, SZ_UNDEF): 5330 case TAB (PCREL1632, SZ_UNDEF): 5331 { 5332 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment 5333 && relaxable_symbol (fragP->fr_symbol)) 5334 || flag_short_refs) 5335 { 5336 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT); 5337 } 5338 else 5339 { 5340 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG); 5341 } 5342 break; 5343 } 5344 5345 case TAB (PCINDEX, SZ_UNDEF): 5346 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment 5347 && relaxable_symbol (fragP->fr_symbol))) 5348 { 5349 fragP->fr_subtype = TAB (PCINDEX, BYTE); 5350 } 5351 else 5352 { 5353 fragP->fr_subtype = TAB (PCINDEX, LONG); 5354 } 5355 break; 5356 5357 case TAB (ABSTOPCREL, SZ_UNDEF): 5358 { 5359 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment 5360 && relaxable_symbol (fragP->fr_symbol))) 5361 { 5362 fragP->fr_subtype = TAB (ABSTOPCREL, SHORT); 5363 } 5364 else 5365 { 5366 fragP->fr_subtype = TAB (ABSTOPCREL, LONG); 5367 } 5368 break; 5369 } 5370 5371 default: 5372 break; 5373 } 5374 5375 /* Now that SZ_UNDEF are taken care of, check others. */ 5376 switch (fragP->fr_subtype) 5377 { 5378 case TAB (BRANCHBWL, BYTE): 5379 case TAB (BRABSJUNC, BYTE): 5380 case TAB (BRABSJCOND, BYTE): 5381 case TAB (BRANCHBW, BYTE): 5382 /* We can't do a short jump to the next instruction, so in that 5383 case we force word mode. If the symbol is at the start of a 5384 frag, and it is the next frag with any data in it (usually 5385 this is just the next frag, but assembler listings may 5386 introduce empty frags), we must use word mode. */ 5387 if (fragP->fr_symbol) 5388 { 5389 fragS *sym_frag; 5390 5391 sym_frag = symbol_get_frag (fragP->fr_symbol); 5392 if (S_GET_VALUE (fragP->fr_symbol) == sym_frag->fr_address) 5393 { 5394 fragS *l; 5395 5396 for (l = fragP->fr_next; l && l != sym_frag; l = l->fr_next) 5397 if (l->fr_fix != 0) 5398 break; 5399 if (l == sym_frag) 5400 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT); 5401 } 5402 } 5403 break; 5404 default: 5405 break; 5406 } 5407 return md_relax_table[fragP->fr_subtype].rlx_length; 5408 } 5409 5410 #if defined(OBJ_AOUT) | defined(OBJ_BOUT) 5411 /* the bit-field entries in the relocation_info struct plays hell 5412 with the byte-order problems of cross-assembly. So as a hack, 5413 I added this mach. dependent ri twiddler. Ugly, but it gets 5414 you there. -KWK */ 5415 /* on m68k: first 4 bytes are normal unsigned long, next three bytes 5416 are symbolnum, most sig. byte first. Last byte is broken up with 5417 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower 5418 nibble as nuthin. (on Sun 3 at least) */ 5419 /* Translate the internal relocation information into target-specific 5420 format. */ 5421 #ifdef comment 5422 void 5423 md_ri_to_chars (char *the_bytes, struct reloc_info_generic *ri) 5424 { 5425 /* This is easy. */ 5426 md_number_to_chars (the_bytes, ri->r_address, 4); 5427 /* Now the fun stuff. */ 5428 the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff; 5429 the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff; 5430 the_bytes[6] = ri->r_symbolnum & 0x0ff; 5431 the_bytes[7] = (((ri->r_pcrel << 7) & 0x80) 5432 | ((ri->r_length << 5) & 0x60) 5433 | ((ri->r_extern << 4) & 0x10)); 5434 } 5435 5436 #endif 5437 5438 #endif /* OBJ_AOUT or OBJ_BOUT */ 5439 5440 #ifndef WORKING_DOT_WORD 5441 int md_short_jump_size = 4; 5442 int md_long_jump_size = 6; 5443 5444 void 5445 md_create_short_jump (char *ptr, addressT from_addr, addressT to_addr, 5446 fragS *frag ATTRIBUTE_UNUSED, 5447 symbolS *to_symbol ATTRIBUTE_UNUSED) 5448 { 5449 valueT offset; 5450 5451 offset = to_addr - (from_addr + 2); 5452 5453 md_number_to_chars (ptr, (valueT) 0x6000, 2); 5454 md_number_to_chars (ptr + 2, (valueT) offset, 2); 5455 } 5456 5457 void 5458 md_create_long_jump (char *ptr, addressT from_addr, addressT to_addr, 5459 fragS *frag, symbolS *to_symbol) 5460 { 5461 valueT offset; 5462 5463 if (!HAVE_LONG_BRANCH (current_architecture)) 5464 { 5465 if (flag_keep_pcrel) 5466 as_fatal (_("Tried to convert PC relative branch to absolute jump")); 5467 offset = to_addr - S_GET_VALUE (to_symbol); 5468 md_number_to_chars (ptr, (valueT) 0x4EF9, 2); 5469 md_number_to_chars (ptr + 2, (valueT) offset, 4); 5470 fix_new (frag, (ptr + 2) - frag->fr_literal, 4, to_symbol, (offsetT) 0, 5471 0, NO_RELOC); 5472 } 5473 else 5474 { 5475 offset = to_addr - (from_addr + 2); 5476 md_number_to_chars (ptr, (valueT) 0x60ff, 2); 5477 md_number_to_chars (ptr + 2, (valueT) offset, 4); 5478 } 5479 } 5480 5481 #endif 5482 5483 /* Different values of OK tell what its OK to return. Things that 5484 aren't OK are an error (what a shock, no?) 5485 5486 0: Everything is OK 5487 10: Absolute 1:8 only 5488 20: Absolute 0:7 only 5489 30: absolute 0:15 only 5490 40: Absolute 0:31 only 5491 50: absolute 0:127 only 5492 55: absolute -64:63 only 5493 60: absolute -128:127 only 5494 65: absolute 0:511 only 5495 70: absolute 0:4095 only 5496 80: absolute -1, 1:7 only 5497 90: No bignums. */ 5498 5499 static int 5500 get_num (struct m68k_exp *exp, int ok) 5501 { 5502 if (exp->exp.X_op == O_absent) 5503 { 5504 /* Do the same thing the VAX asm does. */ 5505 op (exp) = O_constant; 5506 adds (exp) = 0; 5507 subs (exp) = 0; 5508 offs (exp) = 0; 5509 if (ok == 10) 5510 { 5511 as_warn (_("expression out of range: defaulting to 1")); 5512 offs (exp) = 1; 5513 } 5514 } 5515 else if (exp->exp.X_op == O_constant) 5516 { 5517 switch (ok) 5518 { 5519 case 10: 5520 if ((valueT) TRUNC (offs (exp)) - 1 > 7) 5521 { 5522 as_warn (_("expression out of range: defaulting to 1")); 5523 offs (exp) = 1; 5524 } 5525 break; 5526 case 20: 5527 if ((valueT) TRUNC (offs (exp)) > 7) 5528 goto outrange; 5529 break; 5530 case 30: 5531 if ((valueT) TRUNC (offs (exp)) > 15) 5532 goto outrange; 5533 break; 5534 case 40: 5535 if ((valueT) TRUNC (offs (exp)) > 32) 5536 goto outrange; 5537 break; 5538 case 50: 5539 if ((valueT) TRUNC (offs (exp)) > 127) 5540 goto outrange; 5541 break; 5542 case 55: 5543 if ((valueT) SEXT (offs (exp)) + 64 > 127) 5544 goto outrange; 5545 break; 5546 case 60: 5547 if ((valueT) SEXT (offs (exp)) + 128 > 255) 5548 goto outrange; 5549 break; 5550 case 65: 5551 if ((valueT) TRUNC (offs (exp)) > 511) 5552 goto outrange; 5553 break; 5554 case 70: 5555 if ((valueT) TRUNC (offs (exp)) > 4095) 5556 { 5557 outrange: 5558 as_warn (_("expression out of range: defaulting to 0")); 5559 offs (exp) = 0; 5560 } 5561 break; 5562 case 80: 5563 if ((valueT) TRUNC (offs (exp)) != 0xffffffff 5564 && (valueT) TRUNC (offs (exp)) - 1 > 6) 5565 { 5566 as_warn (_("expression out of range: defaulting to 1")); 5567 offs (exp) = 1; 5568 } 5569 break; 5570 default: 5571 break; 5572 } 5573 } 5574 else if (exp->exp.X_op == O_big) 5575 { 5576 if (offs (exp) <= 0 /* flonum. */ 5577 && (ok == 90 /* no bignums */ 5578 || (ok > 10 /* Small-int ranges including 0 ok. */ 5579 /* If we have a flonum zero, a zero integer should 5580 do as well (e.g., in moveq). */ 5581 && generic_floating_point_number.exponent == 0 5582 && generic_floating_point_number.low[0] == 0))) 5583 { 5584 /* HACK! Turn it into a long. */ 5585 LITTLENUM_TYPE words[6]; 5586 5587 gen_to_words (words, 2, 8L); /* These numbers are magic! */ 5588 op (exp) = O_constant; 5589 adds (exp) = 0; 5590 subs (exp) = 0; 5591 offs (exp) = words[1] | (words[0] << 16); 5592 } 5593 else if (ok != 0) 5594 { 5595 op (exp) = O_constant; 5596 adds (exp) = 0; 5597 subs (exp) = 0; 5598 offs (exp) = (ok == 10) ? 1 : 0; 5599 as_warn (_("Can't deal with expression; defaulting to %ld"), 5600 (long) offs (exp)); 5601 } 5602 } 5603 else 5604 { 5605 if (ok >= 10 && ok <= 80) 5606 { 5607 op (exp) = O_constant; 5608 adds (exp) = 0; 5609 subs (exp) = 0; 5610 offs (exp) = (ok == 10) ? 1 : 0; 5611 as_warn (_("Can't deal with expression; defaulting to %ld"), 5612 (long) offs (exp)); 5613 } 5614 } 5615 5616 if (exp->size != SIZE_UNSPEC) 5617 { 5618 switch (exp->size) 5619 { 5620 case SIZE_UNSPEC: 5621 case SIZE_LONG: 5622 break; 5623 case SIZE_BYTE: 5624 if (!isbyte (offs (exp))) 5625 as_warn (_("expression doesn't fit in BYTE")); 5626 break; 5627 case SIZE_WORD: 5628 if (!isword (offs (exp))) 5629 as_warn (_("expression doesn't fit in WORD")); 5630 break; 5631 } 5632 } 5633 5634 return offs (exp); 5635 } 5636 5637 /* These are the back-ends for the various machine dependent pseudo-ops. */ 5638 5639 static void 5640 s_data1 (int ignore ATTRIBUTE_UNUSED) 5641 { 5642 subseg_set (data_section, 1); 5643 demand_empty_rest_of_line (); 5644 } 5645 5646 static void 5647 s_data2 (int ignore ATTRIBUTE_UNUSED) 5648 { 5649 subseg_set (data_section, 2); 5650 demand_empty_rest_of_line (); 5651 } 5652 5653 static void 5654 s_bss (int ignore ATTRIBUTE_UNUSED) 5655 { 5656 /* We don't support putting frags in the BSS segment, we fake it 5657 by marking in_bss, then looking at s_skip for clues. */ 5658 5659 subseg_set (bss_section, 0); 5660 demand_empty_rest_of_line (); 5661 } 5662 5663 static void 5664 s_even (int ignore ATTRIBUTE_UNUSED) 5665 { 5666 int temp; 5667 long temp_fill; 5668 5669 temp = 1; /* JF should be 2? */ 5670 temp_fill = get_absolute_expression (); 5671 if (!need_pass_2) /* Never make frag if expect extra pass. */ 5672 frag_align (temp, (int) temp_fill, 0); 5673 demand_empty_rest_of_line (); 5674 record_alignment (now_seg, temp); 5675 } 5676 5677 static void 5678 s_proc (int ignore ATTRIBUTE_UNUSED) 5679 { 5680 demand_empty_rest_of_line (); 5681 } 5682 5683 /* Pseudo-ops handled for MRI compatibility. */ 5685 5686 /* This function returns non-zero if the argument is a conditional 5687 pseudo-op. This is called when checking whether a pending 5688 alignment is needed. */ 5689 5690 int 5691 m68k_conditional_pseudoop (pseudo_typeS *pop) 5692 { 5693 return (pop->poc_handler == s_mri_if 5694 || pop->poc_handler == s_mri_else); 5695 } 5696 5697 /* Handle an MRI style chip specification. */ 5698 5699 static void 5700 mri_chip (void) 5701 { 5702 char *s; 5703 char c; 5704 int i; 5705 5706 s = input_line_pointer; 5707 /* We can't use get_symbol_name since the processor names are not proper 5708 symbols. */ 5709 while (is_part_of_name (c = *input_line_pointer++)) 5710 ; 5711 *--input_line_pointer = 0; 5712 for (i = 0; m68k_cpus[i].name; i++) 5713 if (strcasecmp (s, m68k_cpus[i].name) == 0) 5714 break; 5715 if (!m68k_cpus[i].name) 5716 { 5717 as_bad (_("%s: unrecognized processor name"), s); 5718 *input_line_pointer = c; 5719 ignore_rest_of_line (); 5720 return; 5721 } 5722 *input_line_pointer = c; 5723 5724 if (*input_line_pointer == '/') 5725 current_architecture = 0; 5726 else 5727 current_architecture &= m68881 | m68851; 5728 current_architecture |= m68k_cpus[i].arch & ~(m68881 | m68851); 5729 control_regs = m68k_cpus[i].control_regs; 5730 5731 while (*input_line_pointer == '/') 5732 { 5733 ++input_line_pointer; 5734 s = input_line_pointer; 5735 /* We can't use get_symbol_name since the processor names are not 5736 proper symbols. */ 5737 while (is_part_of_name (c = *input_line_pointer++)) 5738 ; 5739 *--input_line_pointer = 0; 5740 if (strcmp (s, "68881") == 0) 5741 current_architecture |= m68881; 5742 else if (strcmp (s, "68851") == 0) 5743 current_architecture |= m68851; 5744 *input_line_pointer = c; 5745 } 5746 } 5747 5748 /* The MRI CHIP pseudo-op. */ 5749 5750 static void 5751 s_chip (int ignore ATTRIBUTE_UNUSED) 5752 { 5753 char *stop = NULL; 5754 char stopc; 5755 5756 if (flag_mri) 5757 stop = mri_comment_field (&stopc); 5758 mri_chip (); 5759 if (flag_mri) 5760 mri_comment_end (stop, stopc); 5761 demand_empty_rest_of_line (); 5762 } 5763 5764 /* The MRI FOPT pseudo-op. */ 5765 5766 static void 5767 s_fopt (int ignore ATTRIBUTE_UNUSED) 5768 { 5769 SKIP_WHITESPACE (); 5770 5771 if (strncasecmp (input_line_pointer, "ID=", 3) == 0) 5772 { 5773 int temp; 5774 5775 input_line_pointer += 3; 5776 temp = get_absolute_expression (); 5777 if (temp < 0 || temp > 7) 5778 as_bad (_("bad coprocessor id")); 5779 else 5780 m68k_float_copnum = COP0 + temp; 5781 } 5782 else 5783 { 5784 as_bad (_("unrecognized fopt option")); 5785 ignore_rest_of_line (); 5786 return; 5787 } 5788 5789 demand_empty_rest_of_line (); 5790 } 5791 5792 /* The structure used to handle the MRI OPT pseudo-op. */ 5793 5794 struct opt_action 5795 { 5796 /* The name of the option. */ 5797 const char *name; 5798 5799 /* If this is not NULL, just call this function. The first argument 5800 is the ARG field of this structure, the second argument is 5801 whether the option was negated. */ 5802 void (*pfn) (int arg, int on); 5803 5804 /* If this is not NULL, and the PFN field is NULL, set the variable 5805 this points to. Set it to the ARG field if the option was not 5806 negated, and the NOTARG field otherwise. */ 5807 int *pvar; 5808 5809 /* The value to pass to PFN or to assign to *PVAR. */ 5810 int arg; 5811 5812 /* The value to assign to *PVAR if the option is negated. If PFN is 5813 NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then 5814 the option may not be negated. */ 5815 int notarg; 5816 }; 5817 5818 /* The table used to handle the MRI OPT pseudo-op. */ 5819 5820 static void skip_to_comma (int, int); 5821 static void opt_nest (int, int); 5822 static void opt_chip (int, int); 5823 static void opt_list (int, int); 5824 static void opt_list_symbols (int, int); 5825 5826 static const struct opt_action opt_table[] = 5827 { 5828 { "abspcadd", 0, &m68k_abspcadd, 1, 0 }, 5829 5830 /* We do relaxing, so there is little use for these options. */ 5831 { "b", 0, 0, 0, 0 }, 5832 { "brs", 0, 0, 0, 0 }, 5833 { "brb", 0, 0, 0, 0 }, 5834 { "brl", 0, 0, 0, 0 }, 5835 { "brw", 0, 0, 0, 0 }, 5836 5837 { "c", 0, 0, 0, 0 }, 5838 { "cex", 0, 0, 0, 0 }, 5839 { "case", 0, &symbols_case_sensitive, 1, 0 }, 5840 { "cl", 0, 0, 0, 0 }, 5841 { "cre", 0, 0, 0, 0 }, 5842 { "d", 0, &flag_keep_locals, 1, 0 }, 5843 { "e", 0, 0, 0, 0 }, 5844 { "f", 0, &flag_short_refs, 1, 0 }, 5845 { "frs", 0, &flag_short_refs, 1, 0 }, 5846 { "frl", 0, &flag_short_refs, 0, 1 }, 5847 { "g", 0, 0, 0, 0 }, 5848 { "i", 0, 0, 0, 0 }, 5849 { "m", 0, 0, 0, 0 }, 5850 { "mex", 0, 0, 0, 0 }, 5851 { "mc", 0, 0, 0, 0 }, 5852 { "md", 0, 0, 0, 0 }, 5853 { "nest", opt_nest, 0, 0, 0 }, 5854 { "next", skip_to_comma, 0, 0, 0 }, 5855 { "o", 0, 0, 0, 0 }, 5856 { "old", 0, 0, 0, 0 }, 5857 { "op", skip_to_comma, 0, 0, 0 }, 5858 { "pco", 0, 0, 0, 0 }, 5859 { "p", opt_chip, 0, 0, 0 }, 5860 { "pcr", 0, 0, 0, 0 }, 5861 { "pcs", 0, 0, 0, 0 }, 5862 { "r", 0, 0, 0, 0 }, 5863 { "quick", 0, &m68k_quick, 1, 0 }, 5864 { "rel32", 0, &m68k_rel32, 1, 0 }, 5865 { "s", opt_list, 0, 0, 0 }, 5866 { "t", opt_list_symbols, 0, 0, 0 }, 5867 { "w", 0, &flag_no_warnings, 0, 1 }, 5868 { "x", 0, 0, 0, 0 } 5869 }; 5870 5871 #define OPTCOUNT ((int) (sizeof opt_table / sizeof opt_table[0])) 5872 5873 /* The MRI OPT pseudo-op. */ 5874 5875 static void 5876 s_opt (int ignore ATTRIBUTE_UNUSED) 5877 { 5878 do 5879 { 5880 int t; 5881 char *s; 5882 char c; 5883 int i; 5884 const struct opt_action *o; 5885 5886 SKIP_WHITESPACE (); 5887 5888 t = 1; 5889 if (*input_line_pointer == '-') 5890 { 5891 ++input_line_pointer; 5892 t = 0; 5893 } 5894 else if (strncasecmp (input_line_pointer, "NO", 2) == 0) 5895 { 5896 input_line_pointer += 2; 5897 t = 0; 5898 } 5899 5900 c = get_symbol_name (&s); 5901 5902 for (i = 0, o = opt_table; i < OPTCOUNT; i++, o++) 5903 { 5904 if (strcasecmp (s, o->name) == 0) 5905 { 5906 if (o->pfn) 5907 { 5908 /* Restore input_line_pointer now in case the option 5909 takes arguments. */ 5910 (void) restore_line_pointer (c); 5911 (*o->pfn) (o->arg, t); 5912 } 5913 else if (o->pvar != NULL) 5914 { 5915 if (! t && o->arg == o->notarg) 5916 as_bad (_("option `%s' may not be negated"), s); 5917 restore_line_pointer (c); 5918 *o->pvar = t ? o->arg : o->notarg; 5919 } 5920 else 5921 *input_line_pointer = c; 5922 break; 5923 } 5924 } 5925 if (i >= OPTCOUNT) 5926 { 5927 as_bad (_("option `%s' not recognized"), s); 5928 restore_line_pointer (c); 5929 } 5930 } 5931 while (*input_line_pointer++ == ','); 5932 5933 /* Move back to terminating character. */ 5934 --input_line_pointer; 5935 demand_empty_rest_of_line (); 5936 } 5937 5938 /* Skip ahead to a comma. This is used for OPT options which we do 5939 not support and which take arguments. */ 5940 5941 static void 5942 skip_to_comma (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED) 5943 { 5944 while (*input_line_pointer != ',' 5945 && ! is_end_of_line[(unsigned char) *input_line_pointer]) 5946 ++input_line_pointer; 5947 } 5948 5949 /* Handle the OPT NEST=depth option. */ 5950 5951 static void 5952 opt_nest (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED) 5953 { 5954 if (*input_line_pointer != '=') 5955 { 5956 as_bad (_("bad format of OPT NEST=depth")); 5957 return; 5958 } 5959 5960 ++input_line_pointer; 5961 max_macro_nest = get_absolute_expression (); 5962 } 5963 5964 /* Handle the OPT P=chip option. */ 5965 5966 static void 5967 opt_chip (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED) 5968 { 5969 if (*input_line_pointer != '=') 5970 { 5971 /* This is just OPT P, which we do not support. */ 5972 return; 5973 } 5974 5975 ++input_line_pointer; 5976 mri_chip (); 5977 } 5978 5979 /* Handle the OPT S option. */ 5980 5981 static void 5982 opt_list (int arg ATTRIBUTE_UNUSED, int on) 5983 { 5984 listing_list (on); 5985 } 5986 5987 /* Handle the OPT T option. */ 5988 5989 static void 5990 opt_list_symbols (int arg ATTRIBUTE_UNUSED, int on) 5991 { 5992 if (on) 5993 listing |= LISTING_SYMBOLS; 5994 else 5995 listing &= ~LISTING_SYMBOLS; 5996 } 5997 5998 /* Handle the MRI REG pseudo-op. */ 5999 6000 static void 6001 s_reg (int ignore ATTRIBUTE_UNUSED) 6002 { 6003 char *s; 6004 int c; 6005 struct m68k_op rop; 6006 int mask; 6007 char *stop = NULL; 6008 char stopc; 6009 6010 if (line_label == NULL) 6011 { 6012 as_bad (_("missing label")); 6013 ignore_rest_of_line (); 6014 return; 6015 } 6016 6017 if (flag_mri) 6018 stop = mri_comment_field (&stopc); 6019 6020 SKIP_WHITESPACE (); 6021 6022 s = input_line_pointer; 6023 while (ISALNUM (*input_line_pointer) 6024 #ifdef REGISTER_PREFIX 6025 || *input_line_pointer == REGISTER_PREFIX 6026 #endif 6027 || *input_line_pointer == '/' 6028 || *input_line_pointer == '-') 6029 ++input_line_pointer; 6030 c = *input_line_pointer; 6031 *input_line_pointer = '\0'; 6032 6033 if (m68k_ip_op (s, &rop) != 0) 6034 { 6035 if (rop.error == NULL) 6036 as_bad (_("bad register list")); 6037 else 6038 as_bad (_("bad register list: %s"), rop.error); 6039 *input_line_pointer = c; 6040 ignore_rest_of_line (); 6041 return; 6042 } 6043 6044 *input_line_pointer = c; 6045 6046 if (rop.mode == REGLST) 6047 mask = rop.mask; 6048 else if (rop.mode == DREG) 6049 mask = 1 << (rop.reg - DATA0); 6050 else if (rop.mode == AREG) 6051 mask = 1 << (rop.reg - ADDR0 + 8); 6052 else if (rop.mode == FPREG) 6053 mask = 1 << (rop.reg - FP0 + 16); 6054 else if (rop.mode == CONTROL 6055 && rop.reg == FPI) 6056 mask = 1 << 24; 6057 else if (rop.mode == CONTROL 6058 && rop.reg == FPS) 6059 mask = 1 << 25; 6060 else if (rop.mode == CONTROL 6061 && rop.reg == FPC) 6062 mask = 1 << 26; 6063 else 6064 { 6065 as_bad (_("bad register list")); 6066 ignore_rest_of_line (); 6067 return; 6068 } 6069 6070 S_SET_SEGMENT (line_label, reg_section); 6071 S_SET_VALUE (line_label, ~mask); 6072 symbol_set_frag (line_label, &zero_address_frag); 6073 6074 if (flag_mri) 6075 mri_comment_end (stop, stopc); 6076 6077 demand_empty_rest_of_line (); 6078 } 6079 6080 /* This structure is used for the MRI SAVE and RESTORE pseudo-ops. */ 6081 6082 struct save_opts 6083 { 6084 struct save_opts *next; 6085 int abspcadd; 6086 int symbols_case_sensitive; 6087 int keep_locals; 6088 int short_refs; 6089 int architecture; 6090 const enum m68k_register *control_regs; 6091 int quick; 6092 int rel32; 6093 int listing; 6094 int no_warnings; 6095 /* FIXME: We don't save OPT S. */ 6096 }; 6097 6098 /* This variable holds the stack of saved options. */ 6099 6100 static struct save_opts *save_stack; 6101 6102 /* The MRI SAVE pseudo-op. */ 6103 6104 static void 6105 s_save (int ignore ATTRIBUTE_UNUSED) 6106 { 6107 struct save_opts *s; 6108 6109 s = XNEW (struct save_opts); 6110 s->abspcadd = m68k_abspcadd; 6111 s->symbols_case_sensitive = symbols_case_sensitive; 6112 s->keep_locals = flag_keep_locals; 6113 s->short_refs = flag_short_refs; 6114 s->architecture = current_architecture; 6115 s->control_regs = control_regs; 6116 s->quick = m68k_quick; 6117 s->rel32 = m68k_rel32; 6118 s->listing = listing; 6119 s->no_warnings = flag_no_warnings; 6120 6121 s->next = save_stack; 6122 save_stack = s; 6123 6124 demand_empty_rest_of_line (); 6125 } 6126 6127 /* The MRI RESTORE pseudo-op. */ 6128 6129 static void 6130 s_restore (int ignore ATTRIBUTE_UNUSED) 6131 { 6132 struct save_opts *s; 6133 6134 if (save_stack == NULL) 6135 { 6136 as_bad (_("restore without save")); 6137 ignore_rest_of_line (); 6138 return; 6139 } 6140 6141 s = save_stack; 6142 save_stack = s->next; 6143 6144 m68k_abspcadd = s->abspcadd; 6145 symbols_case_sensitive = s->symbols_case_sensitive; 6146 flag_keep_locals = s->keep_locals; 6147 flag_short_refs = s->short_refs; 6148 current_architecture = s->architecture; 6149 control_regs = s->control_regs; 6150 m68k_quick = s->quick; 6151 m68k_rel32 = s->rel32; 6152 listing = s->listing; 6153 flag_no_warnings = s->no_warnings; 6154 6155 free (s); 6156 6157 demand_empty_rest_of_line (); 6158 } 6159 6160 /* Types of MRI structured control directives. */ 6161 6162 enum mri_control_type 6163 { 6164 mri_for, 6165 mri_if, 6166 mri_repeat, 6167 mri_while 6168 }; 6169 6170 /* This structure is used to stack the MRI structured control 6171 directives. */ 6172 6173 struct mri_control_info 6174 { 6175 /* The directive within which this one is enclosed. */ 6176 struct mri_control_info *outer; 6177 6178 /* The type of directive. */ 6179 enum mri_control_type type; 6180 6181 /* Whether an ELSE has been in an IF. */ 6182 int else_seen; 6183 6184 /* The add or sub statement at the end of a FOR. */ 6185 char *incr; 6186 6187 /* The label of the top of a FOR or REPEAT loop. */ 6188 char *top; 6189 6190 /* The label to jump to for the next iteration, or the else 6191 expression of a conditional. */ 6192 char *next; 6193 6194 /* The label to jump to to break out of the loop, or the label past 6195 the end of a conditional. */ 6196 char *bottom; 6197 }; 6198 6199 /* The stack of MRI structured control directives. */ 6200 6201 static struct mri_control_info *mri_control_stack; 6202 6203 /* The current MRI structured control directive index number, used to 6204 generate label names. */ 6205 6206 static int mri_control_index; 6207 6208 /* Assemble an instruction for an MRI structured control directive. */ 6209 6210 static void 6211 mri_assemble (char *str) 6212 { 6213 char *s; 6214 6215 /* md_assemble expects the opcode to be in lower case. */ 6216 for (s = str; *s != ' ' && *s != '\0'; s++) 6217 *s = TOLOWER (*s); 6218 6219 md_assemble (str); 6220 } 6221 6222 /* Generate a new MRI label structured control directive label name. */ 6223 6224 static char * 6225 mri_control_label (void) 6226 { 6227 char *n; 6228 6229 n = XNEWVEC (char, 20); 6230 sprintf (n, "%smc%d", FAKE_LABEL_NAME, mri_control_index); 6231 ++mri_control_index; 6232 return n; 6233 } 6234 6235 /* Create a new MRI structured control directive. */ 6236 6237 static struct mri_control_info * 6238 push_mri_control (enum mri_control_type type) 6239 { 6240 struct mri_control_info *n; 6241 6242 n = XNEW (struct mri_control_info); 6243 6244 n->type = type; 6245 n->else_seen = 0; 6246 if (type == mri_if || type == mri_while) 6247 n->top = NULL; 6248 else 6249 n->top = mri_control_label (); 6250 n->next = mri_control_label (); 6251 n->bottom = mri_control_label (); 6252 6253 n->outer = mri_control_stack; 6254 mri_control_stack = n; 6255 6256 return n; 6257 } 6258 6259 /* Pop off the stack of MRI structured control directives. */ 6260 6261 static void 6262 pop_mri_control (void) 6263 { 6264 struct mri_control_info *n; 6265 6266 n = mri_control_stack; 6267 mri_control_stack = n->outer; 6268 if (n->top != NULL) 6269 free (n->top); 6270 free (n->next); 6271 free (n->bottom); 6272 free (n); 6273 } 6274 6275 /* Recognize a condition code in an MRI structured control expression. */ 6276 6277 static int 6278 parse_mri_condition (int *pcc) 6279 { 6280 char c1, c2; 6281 6282 know (*input_line_pointer == '<'); 6283 6284 ++input_line_pointer; 6285 c1 = *input_line_pointer++; 6286 c2 = *input_line_pointer++; 6287 6288 if (*input_line_pointer != '>') 6289 { 6290 as_bad (_("syntax error in structured control directive")); 6291 return 0; 6292 } 6293 6294 ++input_line_pointer; 6295 SKIP_WHITESPACE (); 6296 6297 c1 = TOLOWER (c1); 6298 c2 = TOLOWER (c2); 6299 6300 *pcc = (c1 << 8) | c2; 6301 6302 return 1; 6303 } 6304 6305 /* Parse a single operand in an MRI structured control expression. */ 6306 6307 static int 6308 parse_mri_control_operand (int *pcc, char **leftstart, char **leftstop, 6309 char **rightstart, char **rightstop) 6310 { 6311 char *s; 6312 6313 SKIP_WHITESPACE (); 6314 6315 *pcc = -1; 6316 *leftstart = NULL; 6317 *leftstop = NULL; 6318 *rightstart = NULL; 6319 *rightstop = NULL; 6320 6321 if (*input_line_pointer == '<') 6322 { 6323 /* It's just a condition code. */ 6324 return parse_mri_condition (pcc); 6325 } 6326 6327 /* Look ahead for the condition code. */ 6328 for (s = input_line_pointer; *s != '\0'; ++s) 6329 { 6330 if (*s == '<' && s[1] != '\0' && s[2] != '\0' && s[3] == '>') 6331 break; 6332 } 6333 if (*s == '\0') 6334 { 6335 as_bad (_("missing condition code in structured control directive")); 6336 return 0; 6337 } 6338 6339 *leftstart = input_line_pointer; 6340 *leftstop = s; 6341 if (*leftstop > *leftstart 6342 && ((*leftstop)[-1] == ' ' || (*leftstop)[-1] == '\t')) 6343 --*leftstop; 6344 6345 input_line_pointer = s; 6346 if (! parse_mri_condition (pcc)) 6347 return 0; 6348 6349 /* Look ahead for AND or OR or end of line. */ 6350 for (s = input_line_pointer; *s != '\0'; ++s) 6351 { 6352 /* We must make sure we don't misinterpret AND/OR at the end of labels! 6353 if d0 <eq> #FOOAND and d1 <ne> #BAROR then 6354 ^^^ ^^ */ 6355 if ((s == input_line_pointer 6356 || *(s-1) == ' ' 6357 || *(s-1) == '\t') 6358 && ((strncasecmp (s, "AND", 3) == 0 6359 && (s[3] == '.' || ! is_part_of_name (s[3]))) 6360 || (strncasecmp (s, "OR", 2) == 0 6361 && (s[2] == '.' || ! is_part_of_name (s[2]))))) 6362 break; 6363 } 6364 6365 *rightstart = input_line_pointer; 6366 *rightstop = s; 6367 if (*rightstop > *rightstart 6368 && ((*rightstop)[-1] == ' ' || (*rightstop)[-1] == '\t')) 6369 --*rightstop; 6370 6371 input_line_pointer = s; 6372 6373 return 1; 6374 } 6375 6376 #define MCC(b1, b2) (((b1) << 8) | (b2)) 6377 6378 /* Swap the sense of a condition. This changes the condition so that 6379 it generates the same result when the operands are swapped. */ 6380 6381 static int 6382 swap_mri_condition (int cc) 6383 { 6384 switch (cc) 6385 { 6386 case MCC ('h', 'i'): return MCC ('c', 's'); 6387 case MCC ('l', 's'): return MCC ('c', 'c'); 6388 /* <HS> is an alias for <CC>. */ 6389 case MCC ('h', 's'): 6390 case MCC ('c', 'c'): return MCC ('l', 's'); 6391 /* <LO> is an alias for <CS>. */ 6392 case MCC ('l', 'o'): 6393 case MCC ('c', 's'): return MCC ('h', 'i'); 6394 case MCC ('p', 'l'): return MCC ('m', 'i'); 6395 case MCC ('m', 'i'): return MCC ('p', 'l'); 6396 case MCC ('g', 'e'): return MCC ('l', 'e'); 6397 case MCC ('l', 't'): return MCC ('g', 't'); 6398 case MCC ('g', 't'): return MCC ('l', 't'); 6399 case MCC ('l', 'e'): return MCC ('g', 'e'); 6400 /* Issue a warning for conditions we can not swap. */ 6401 case MCC ('n', 'e'): return MCC ('n', 'e'); /* no problem here */ 6402 case MCC ('e', 'q'): return MCC ('e', 'q'); /* also no problem */ 6403 case MCC ('v', 'c'): 6404 case MCC ('v', 's'): 6405 default : 6406 as_warn (_("Condition <%c%c> in structured control directive can not be encoded correctly"), 6407 (char) (cc >> 8), (char) (cc)); 6408 break; 6409 } 6410 return cc; 6411 } 6412 6413 /* Reverse the sense of a condition. */ 6414 6415 static int 6416 reverse_mri_condition (int cc) 6417 { 6418 switch (cc) 6419 { 6420 case MCC ('h', 'i'): return MCC ('l', 's'); 6421 case MCC ('l', 's'): return MCC ('h', 'i'); 6422 /* <HS> is an alias for <CC> */ 6423 case MCC ('h', 's'): return MCC ('l', 'o'); 6424 case MCC ('c', 'c'): return MCC ('c', 's'); 6425 /* <LO> is an alias for <CS> */ 6426 case MCC ('l', 'o'): return MCC ('h', 's'); 6427 case MCC ('c', 's'): return MCC ('c', 'c'); 6428 case MCC ('n', 'e'): return MCC ('e', 'q'); 6429 case MCC ('e', 'q'): return MCC ('n', 'e'); 6430 case MCC ('v', 'c'): return MCC ('v', 's'); 6431 case MCC ('v', 's'): return MCC ('v', 'c'); 6432 case MCC ('p', 'l'): return MCC ('m', 'i'); 6433 case MCC ('m', 'i'): return MCC ('p', 'l'); 6434 case MCC ('g', 'e'): return MCC ('l', 't'); 6435 case MCC ('l', 't'): return MCC ('g', 'e'); 6436 case MCC ('g', 't'): return MCC ('l', 'e'); 6437 case MCC ('l', 'e'): return MCC ('g', 't'); 6438 } 6439 return cc; 6440 } 6441 6442 /* Build an MRI structured control expression. This generates test 6443 and branch instructions. It goes to TRUELAB if the condition is 6444 true, and to FALSELAB if the condition is false. Exactly one of 6445 TRUELAB and FALSELAB will be NULL, meaning to fall through. QUAL 6446 is the size qualifier for the expression. EXTENT is the size to 6447 use for the branch. */ 6448 6449 static void 6450 build_mri_control_operand (int qual, int cc, char *leftstart, char *leftstop, 6451 char *rightstart, char *rightstop, 6452 const char *truelab, const char *falselab, 6453 int extent) 6454 { 6455 char *buf; 6456 char *s; 6457 6458 if (leftstart != NULL) 6459 { 6460 struct m68k_op leftop, rightop; 6461 char c; 6462 6463 /* Swap the compare operands, if necessary, to produce a legal 6464 m68k compare instruction. Comparing a register operand with 6465 a non-register operand requires the register to be on the 6466 right (cmp, cmpa). Comparing an immediate value with 6467 anything requires the immediate value to be on the left 6468 (cmpi). */ 6469 6470 c = *leftstop; 6471 *leftstop = '\0'; 6472 (void) m68k_ip_op (leftstart, &leftop); 6473 *leftstop = c; 6474 6475 c = *rightstop; 6476 *rightstop = '\0'; 6477 (void) m68k_ip_op (rightstart, &rightop); 6478 *rightstop = c; 6479 6480 if (rightop.mode == IMMED 6481 || ((leftop.mode == DREG || leftop.mode == AREG) 6482 && (rightop.mode != DREG && rightop.mode != AREG))) 6483 { 6484 char *temp; 6485 6486 /* Correct conditional handling: 6487 if #1 <lt> d0 then ;means if (1 < d0) 6488 ... 6489 endi 6490 6491 should assemble to: 6492 6493 cmp #1,d0 if we do *not* swap the operands 6494 bgt true we need the swapped condition! 6495 ble false 6496 true: 6497 ... 6498 false: 6499 */ 6500 temp = leftstart; 6501 leftstart = rightstart; 6502 rightstart = temp; 6503 temp = leftstop; 6504 leftstop = rightstop; 6505 rightstop = temp; 6506 } 6507 else 6508 { 6509 cc = swap_mri_condition (cc); 6510 } 6511 } 6512 6513 if (truelab == NULL) 6514 { 6515 cc = reverse_mri_condition (cc); 6516 truelab = falselab; 6517 } 6518 6519 if (leftstart != NULL) 6520 { 6521 buf = XNEWVEC (char, (20 6522 + (leftstop - leftstart) 6523 + (rightstop - rightstart))); 6524 s = buf; 6525 *s++ = 'c'; 6526 *s++ = 'm'; 6527 *s++ = 'p'; 6528 if (qual != '\0') 6529 *s++ = TOLOWER (qual); 6530 *s++ = ' '; 6531 memcpy (s, leftstart, leftstop - leftstart); 6532 s += leftstop - leftstart; 6533 *s++ = ','; 6534 memcpy (s, rightstart, rightstop - rightstart); 6535 s += rightstop - rightstart; 6536 *s = '\0'; 6537 mri_assemble (buf); 6538 free (buf); 6539 } 6540 6541 buf = XNEWVEC (char, 20 + strlen (truelab)); 6542 s = buf; 6543 *s++ = 'b'; 6544 *s++ = cc >> 8; 6545 *s++ = cc & 0xff; 6546 if (extent != '\0') 6547 *s++ = TOLOWER (extent); 6548 *s++ = ' '; 6549 strcpy (s, truelab); 6550 mri_assemble (buf); 6551 free (buf); 6552 } 6553 6554 /* Parse an MRI structured control expression. This generates test 6555 and branch instructions. STOP is where the expression ends. It 6556 goes to TRUELAB if the condition is true, and to FALSELAB if the 6557 condition is false. Exactly one of TRUELAB and FALSELAB will be 6558 NULL, meaning to fall through. QUAL is the size qualifier for the 6559 expression. EXTENT is the size to use for the branch. */ 6560 6561 static void 6562 parse_mri_control_expression (char *stop, int qual, const char *truelab, 6563 const char *falselab, int extent) 6564 { 6565 int c; 6566 int cc; 6567 char *leftstart; 6568 char *leftstop; 6569 char *rightstart; 6570 char *rightstop; 6571 6572 c = *stop; 6573 *stop = '\0'; 6574 6575 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop, 6576 &rightstart, &rightstop)) 6577 { 6578 *stop = c; 6579 return; 6580 } 6581 6582 if (strncasecmp (input_line_pointer, "AND", 3) == 0) 6583 { 6584 const char *flab; 6585 6586 if (falselab != NULL) 6587 flab = falselab; 6588 else 6589 flab = mri_control_label (); 6590 6591 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart, 6592 rightstop, (const char *) NULL, flab, extent); 6593 6594 input_line_pointer += 3; 6595 if (*input_line_pointer != '.' 6596 || input_line_pointer[1] == '\0') 6597 qual = '\0'; 6598 else 6599 { 6600 qual = input_line_pointer[1]; 6601 input_line_pointer += 2; 6602 } 6603 6604 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop, 6605 &rightstart, &rightstop)) 6606 { 6607 *stop = c; 6608 return; 6609 } 6610 6611 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart, 6612 rightstop, truelab, falselab, extent); 6613 6614 if (falselab == NULL) 6615 colon (flab); 6616 } 6617 else if (strncasecmp (input_line_pointer, "OR", 2) == 0) 6618 { 6619 const char *tlab; 6620 6621 if (truelab != NULL) 6622 tlab = truelab; 6623 else 6624 tlab = mri_control_label (); 6625 6626 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart, 6627 rightstop, tlab, (const char *) NULL, extent); 6628 6629 input_line_pointer += 2; 6630 if (*input_line_pointer != '.' 6631 || input_line_pointer[1] == '\0') 6632 qual = '\0'; 6633 else 6634 { 6635 qual = input_line_pointer[1]; 6636 input_line_pointer += 2; 6637 } 6638 6639 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop, 6640 &rightstart, &rightstop)) 6641 { 6642 *stop = c; 6643 return; 6644 } 6645 6646 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart, 6647 rightstop, truelab, falselab, extent); 6648 6649 if (truelab == NULL) 6650 colon (tlab); 6651 } 6652 else 6653 { 6654 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart, 6655 rightstop, truelab, falselab, extent); 6656 } 6657 6658 *stop = c; 6659 if (input_line_pointer != stop) 6660 as_bad (_("syntax error in structured control directive")); 6661 } 6662 6663 /* Handle the MRI IF pseudo-op. This may be a structured control 6664 directive, or it may be a regular assembler conditional, depending 6665 on its operands. */ 6666 6667 static void 6668 s_mri_if (int qual) 6669 { 6670 char *s; 6671 int c; 6672 struct mri_control_info *n; 6673 6674 /* A structured control directive must end with THEN with an 6675 optional qualifier. */ 6676 s = input_line_pointer; 6677 /* We only accept '*' as introduction of comments if preceded by white space 6678 or at first column of a line (I think this can't actually happen here?) 6679 This is important when assembling: 6680 if d0 <ne> 12(a0,d0*2) then 6681 if d0 <ne> #CONST*20 then. */ 6682 while (! (is_end_of_line[(unsigned char) *s] 6683 || (flag_mri 6684 && *s == '*' 6685 && (s == input_line_pointer 6686 || *(s-1) == ' ' 6687 || *(s-1) == '\t')))) 6688 ++s; 6689 --s; 6690 while (s > input_line_pointer && (*s == ' ' || *s == '\t')) 6691 --s; 6692 6693 if (s - input_line_pointer > 1 6694 && s[-1] == '.') 6695 s -= 2; 6696 6697 if (s - input_line_pointer < 3 6698 || strncasecmp (s - 3, "THEN", 4) != 0) 6699 { 6700 if (qual != '\0') 6701 { 6702 as_bad (_("missing then")); 6703 ignore_rest_of_line (); 6704 return; 6705 } 6706 6707 /* It's a conditional. */ 6708 s_if (O_ne); 6709 return; 6710 } 6711 6712 /* Since this might be a conditional if, this pseudo-op will be 6713 called even if we are supported to be ignoring input. Double 6714 check now. Clobber *input_line_pointer so that ignore_input 6715 thinks that this is not a special pseudo-op. */ 6716 c = *input_line_pointer; 6717 *input_line_pointer = 0; 6718 if (ignore_input ()) 6719 { 6720 *input_line_pointer = c; 6721 while (! is_end_of_line[(unsigned char) *input_line_pointer]) 6722 ++input_line_pointer; 6723 demand_empty_rest_of_line (); 6724 return; 6725 } 6726 *input_line_pointer = c; 6727 6728 n = push_mri_control (mri_if); 6729 6730 parse_mri_control_expression (s - 3, qual, (const char *) NULL, 6731 n->next, s[1] == '.' ? s[2] : '\0'); 6732 6733 if (s[1] == '.') 6734 input_line_pointer = s + 3; 6735 else 6736 input_line_pointer = s + 1; 6737 6738 if (flag_mri) 6739 { 6740 while (! is_end_of_line[(unsigned char) *input_line_pointer]) 6741 ++input_line_pointer; 6742 } 6743 6744 demand_empty_rest_of_line (); 6745 } 6746 6747 /* Handle the MRI else pseudo-op. If we are currently doing an MRI 6748 structured IF, associate the ELSE with the IF. Otherwise, assume 6749 it is a conditional else. */ 6750 6751 static void 6752 s_mri_else (int qual) 6753 { 6754 int c; 6755 char *buf; 6756 char q[2]; 6757 6758 if (qual == '\0' 6759 && (mri_control_stack == NULL 6760 || mri_control_stack->type != mri_if 6761 || mri_control_stack->else_seen)) 6762 { 6763 s_else (0); 6764 return; 6765 } 6766 6767 c = *input_line_pointer; 6768 *input_line_pointer = 0; 6769 if (ignore_input ()) 6770 { 6771 *input_line_pointer = c; 6772 while (! is_end_of_line[(unsigned char) *input_line_pointer]) 6773 ++input_line_pointer; 6774 demand_empty_rest_of_line (); 6775 return; 6776 } 6777 *input_line_pointer = c; 6778 6779 if (mri_control_stack == NULL 6780 || mri_control_stack->type != mri_if 6781 || mri_control_stack->else_seen) 6782 { 6783 as_bad (_("else without matching if")); 6784 ignore_rest_of_line (); 6785 return; 6786 } 6787 6788 mri_control_stack->else_seen = 1; 6789 6790 buf = XNEWVEC (char, 20 + strlen (mri_control_stack->bottom)); 6791 q[0] = TOLOWER (qual); 6792 q[1] = '\0'; 6793 sprintf (buf, "bra%s %s", q, mri_control_stack->bottom); 6794 mri_assemble (buf); 6795 free (buf); 6796 6797 colon (mri_control_stack->next); 6798 6799 if (flag_mri) 6800 { 6801 while (! is_end_of_line[(unsigned char) *input_line_pointer]) 6802 ++input_line_pointer; 6803 } 6804 6805 demand_empty_rest_of_line (); 6806 } 6807 6808 /* Handle the MRI ENDI pseudo-op. */ 6809 6810 static void 6811 s_mri_endi (int ignore ATTRIBUTE_UNUSED) 6812 { 6813 if (mri_control_stack == NULL 6814 || mri_control_stack->type != mri_if) 6815 { 6816 as_bad (_("endi without matching if")); 6817 ignore_rest_of_line (); 6818 return; 6819 } 6820 6821 /* ignore_input will not return true for ENDI, so we don't need to 6822 worry about checking it again here. */ 6823 6824 if (! mri_control_stack->else_seen) 6825 colon (mri_control_stack->next); 6826 colon (mri_control_stack->bottom); 6827 6828 pop_mri_control (); 6829 6830 if (flag_mri) 6831 { 6832 while (! is_end_of_line[(unsigned char) *input_line_pointer]) 6833 ++input_line_pointer; 6834 } 6835 6836 demand_empty_rest_of_line (); 6837 } 6838 6839 /* Handle the MRI BREAK pseudo-op. */ 6840 6841 static void 6842 s_mri_break (int extent) 6843 { 6844 struct mri_control_info *n; 6845 char *buf; 6846 char ex[2]; 6847 6848 n = mri_control_stack; 6849 while (n != NULL 6850 && n->type != mri_for 6851 && n->type != mri_repeat 6852 && n->type != mri_while) 6853 n = n->outer; 6854 if (n == NULL) 6855 { 6856 as_bad (_("break outside of structured loop")); 6857 ignore_rest_of_line (); 6858 return; 6859 } 6860 6861 buf = XNEWVEC (char, 20 + strlen (n->bottom)); 6862 ex[0] = TOLOWER (extent); 6863 ex[1] = '\0'; 6864 sprintf (buf, "bra%s %s", ex, n->bottom); 6865 mri_assemble (buf); 6866 free (buf); 6867 6868 if (flag_mri) 6869 { 6870 while (! is_end_of_line[(unsigned char) *input_line_pointer]) 6871 ++input_line_pointer; 6872 } 6873 6874 demand_empty_rest_of_line (); 6875 } 6876 6877 /* Handle the MRI NEXT pseudo-op. */ 6878 6879 static void 6880 s_mri_next (int extent) 6881 { 6882 struct mri_control_info *n; 6883 char *buf; 6884 char ex[2]; 6885 6886 n = mri_control_stack; 6887 while (n != NULL 6888 && n->type != mri_for 6889 && n->type != mri_repeat 6890 && n->type != mri_while) 6891 n = n->outer; 6892 if (n == NULL) 6893 { 6894 as_bad (_("next outside of structured loop")); 6895 ignore_rest_of_line (); 6896 return; 6897 } 6898 6899 buf = XNEWVEC (char, 20 + strlen (n->next)); 6900 ex[0] = TOLOWER (extent); 6901 ex[1] = '\0'; 6902 sprintf (buf, "bra%s %s", ex, n->next); 6903 mri_assemble (buf); 6904 free (buf); 6905 6906 if (flag_mri) 6907 { 6908 while (! is_end_of_line[(unsigned char) *input_line_pointer]) 6909 ++input_line_pointer; 6910 } 6911 6912 demand_empty_rest_of_line (); 6913 } 6914 6915 /* Handle the MRI FOR pseudo-op. */ 6916 6917 static void 6918 s_mri_for (int qual) 6919 { 6920 const char *varstart, *varstop; 6921 const char *initstart, *initstop; 6922 const char *endstart, *endstop; 6923 const char *bystart, *bystop; 6924 int up; 6925 int by; 6926 int extent; 6927 struct mri_control_info *n; 6928 char *buf; 6929 char *s; 6930 char ex[2]; 6931 6932 /* The syntax is 6933 FOR.q var = init { TO | DOWNTO } end [ BY by ] DO.e 6934 */ 6935 6936 SKIP_WHITESPACE (); 6937 varstart = input_line_pointer; 6938 6939 /* Look for the '='. */ 6940 while (! is_end_of_line[(unsigned char) *input_line_pointer] 6941 && *input_line_pointer != '=') 6942 ++input_line_pointer; 6943 if (*input_line_pointer != '=') 6944 { 6945 as_bad (_("missing =")); 6946 ignore_rest_of_line (); 6947 return; 6948 } 6949 6950 varstop = input_line_pointer; 6951 if (varstop > varstart 6952 && (varstop[-1] == ' ' || varstop[-1] == '\t')) 6953 --varstop; 6954 6955 ++input_line_pointer; 6956 6957 initstart = input_line_pointer; 6958 6959 /* Look for TO or DOWNTO. */ 6960 up = 1; 6961 initstop = NULL; 6962 while (! is_end_of_line[(unsigned char) *input_line_pointer]) 6963 { 6964 if (strncasecmp (input_line_pointer, "TO", 2) == 0 6965 && ! is_part_of_name (input_line_pointer[2])) 6966 { 6967 initstop = input_line_pointer; 6968 input_line_pointer += 2; 6969 break; 6970 } 6971 if (strncasecmp (input_line_pointer, "DOWNTO", 6) == 0 6972 && ! is_part_of_name (input_line_pointer[6])) 6973 { 6974 initstop = input_line_pointer; 6975 up = 0; 6976 input_line_pointer += 6; 6977 break; 6978 } 6979 ++input_line_pointer; 6980 } 6981 if (initstop == NULL) 6982 { 6983 as_bad (_("missing to or downto")); 6984 ignore_rest_of_line (); 6985 return; 6986 } 6987 if (initstop > initstart 6988 && (initstop[-1] == ' ' || initstop[-1] == '\t')) 6989 --initstop; 6990 6991 SKIP_WHITESPACE (); 6992 endstart = input_line_pointer; 6993 6994 /* Look for BY or DO. */ 6995 by = 0; 6996 endstop = NULL; 6997 while (! is_end_of_line[(unsigned char) *input_line_pointer]) 6998 { 6999 if (strncasecmp (input_line_pointer, "BY", 2) == 0 7000 && ! is_part_of_name (input_line_pointer[2])) 7001 { 7002 endstop = input_line_pointer; 7003 by = 1; 7004 input_line_pointer += 2; 7005 break; 7006 } 7007 if (strncasecmp (input_line_pointer, "DO", 2) == 0 7008 && (input_line_pointer[2] == '.' 7009 || ! is_part_of_name (input_line_pointer[2]))) 7010 { 7011 endstop = input_line_pointer; 7012 input_line_pointer += 2; 7013 break; 7014 } 7015 ++input_line_pointer; 7016 } 7017 if (endstop == NULL) 7018 { 7019 as_bad (_("missing do")); 7020 ignore_rest_of_line (); 7021 return; 7022 } 7023 if (endstop > endstart 7024 && (endstop[-1] == ' ' || endstop[-1] == '\t')) 7025 --endstop; 7026 7027 if (! by) 7028 { 7029 bystart = "#1"; 7030 bystop = bystart + 2; 7031 } 7032 else 7033 { 7034 SKIP_WHITESPACE (); 7035 bystart = input_line_pointer; 7036 7037 /* Look for DO. */ 7038 bystop = NULL; 7039 while (! is_end_of_line[(unsigned char) *input_line_pointer]) 7040 { 7041 if (strncasecmp (input_line_pointer, "DO", 2) == 0 7042 && (input_line_pointer[2] == '.' 7043 || ! is_part_of_name (input_line_pointer[2]))) 7044 { 7045 bystop = input_line_pointer; 7046 input_line_pointer += 2; 7047 break; 7048 } 7049 ++input_line_pointer; 7050 } 7051 if (bystop == NULL) 7052 { 7053 as_bad (_("missing do")); 7054 ignore_rest_of_line (); 7055 return; 7056 } 7057 if (bystop > bystart 7058 && (bystop[-1] == ' ' || bystop[-1] == '\t')) 7059 --bystop; 7060 } 7061 7062 if (*input_line_pointer != '.') 7063 extent = '\0'; 7064 else 7065 { 7066 extent = input_line_pointer[1]; 7067 input_line_pointer += 2; 7068 } 7069 7070 /* We have fully parsed the FOR operands. Now build the loop. */ 7071 n = push_mri_control (mri_for); 7072 7073 buf = XNEWVEC (char, 50 + (input_line_pointer - varstart)); 7074 7075 /* Move init,var. */ 7076 s = buf; 7077 *s++ = 'm'; 7078 *s++ = 'o'; 7079 *s++ = 'v'; 7080 *s++ = 'e'; 7081 if (qual != '\0') 7082 *s++ = TOLOWER (qual); 7083 *s++ = ' '; 7084 memcpy (s, initstart, initstop - initstart); 7085 s += initstop - initstart; 7086 *s++ = ','; 7087 memcpy (s, varstart, varstop - varstart); 7088 s += varstop - varstart; 7089 *s = '\0'; 7090 mri_assemble (buf); 7091 7092 colon (n->top); 7093 7094 /* cmp end,var. */ 7095 s = buf; 7096 *s++ = 'c'; 7097 *s++ = 'm'; 7098 *s++ = 'p'; 7099 if (qual != '\0') 7100 *s++ = TOLOWER (qual); 7101 *s++ = ' '; 7102 memcpy (s, endstart, endstop - endstart); 7103 s += endstop - endstart; 7104 *s++ = ','; 7105 memcpy (s, varstart, varstop - varstart); 7106 s += varstop - varstart; 7107 *s = '\0'; 7108 mri_assemble (buf); 7109 7110 /* bcc bottom. */ 7111 ex[0] = TOLOWER (extent); 7112 ex[1] = '\0'; 7113 if (up) 7114 sprintf (buf, "blt%s %s", ex, n->bottom); 7115 else 7116 sprintf (buf, "bgt%s %s", ex, n->bottom); 7117 mri_assemble (buf); 7118 7119 /* Put together the add or sub instruction used by ENDF. */ 7120 s = buf; 7121 if (up) 7122 strcpy (s, "add"); 7123 else 7124 strcpy (s, "sub"); 7125 s += 3; 7126 if (qual != '\0') 7127 *s++ = TOLOWER (qual); 7128 *s++ = ' '; 7129 memcpy (s, bystart, bystop - bystart); 7130 s += bystop - bystart; 7131 *s++ = ','; 7132 memcpy (s, varstart, varstop - varstart); 7133 s += varstop - varstart; 7134 *s = '\0'; 7135 n->incr = buf; 7136 7137 if (flag_mri) 7138 { 7139 while (! is_end_of_line[(unsigned char) *input_line_pointer]) 7140 ++input_line_pointer; 7141 } 7142 7143 demand_empty_rest_of_line (); 7144 } 7145 7146 /* Handle the MRI ENDF pseudo-op. */ 7147 7148 static void 7149 s_mri_endf (int ignore ATTRIBUTE_UNUSED) 7150 { 7151 if (mri_control_stack == NULL 7152 || mri_control_stack->type != mri_for) 7153 { 7154 as_bad (_("endf without for")); 7155 ignore_rest_of_line (); 7156 return; 7157 } 7158 7159 colon (mri_control_stack->next); 7160 7161 mri_assemble (mri_control_stack->incr); 7162 7163 sprintf (mri_control_stack->incr, "bra %s", mri_control_stack->top); 7164 mri_assemble (mri_control_stack->incr); 7165 7166 free (mri_control_stack->incr); 7167 7168 colon (mri_control_stack->bottom); 7169 7170 pop_mri_control (); 7171 7172 if (flag_mri) 7173 { 7174 while (! is_end_of_line[(unsigned char) *input_line_pointer]) 7175 ++input_line_pointer; 7176 } 7177 7178 demand_empty_rest_of_line (); 7179 } 7180 7181 /* Handle the MRI REPEAT pseudo-op. */ 7182 7183 static void 7184 s_mri_repeat (int ignore ATTRIBUTE_UNUSED) 7185 { 7186 struct mri_control_info *n; 7187 7188 n = push_mri_control (mri_repeat); 7189 colon (n->top); 7190 if (flag_mri) 7191 { 7192 while (! is_end_of_line[(unsigned char) *input_line_pointer]) 7193 ++input_line_pointer; 7194 } 7195 demand_empty_rest_of_line (); 7196 } 7197 7198 /* Handle the MRI UNTIL pseudo-op. */ 7199 7200 static void 7201 s_mri_until (int qual) 7202 { 7203 char *s; 7204 7205 if (mri_control_stack == NULL 7206 || mri_control_stack->type != mri_repeat) 7207 { 7208 as_bad (_("until without repeat")); 7209 ignore_rest_of_line (); 7210 return; 7211 } 7212 7213 colon (mri_control_stack->next); 7214 7215 for (s = input_line_pointer; ! is_end_of_line[(unsigned char) *s]; s++) 7216 ; 7217 7218 parse_mri_control_expression (s, qual, (const char *) NULL, 7219 mri_control_stack->top, '\0'); 7220 7221 colon (mri_control_stack->bottom); 7222 7223 input_line_pointer = s; 7224 7225 pop_mri_control (); 7226 7227 if (flag_mri) 7228 { 7229 while (! is_end_of_line[(unsigned char) *input_line_pointer]) 7230 ++input_line_pointer; 7231 } 7232 7233 demand_empty_rest_of_line (); 7234 } 7235 7236 /* Handle the MRI WHILE pseudo-op. */ 7237 7238 static void 7239 s_mri_while (int qual) 7240 { 7241 char *s; 7242 7243 struct mri_control_info *n; 7244 7245 s = input_line_pointer; 7246 /* We only accept '*' as introduction of comments if preceded by white space 7247 or at first column of a line (I think this can't actually happen here?) 7248 This is important when assembling: 7249 while d0 <ne> 12(a0,d0*2) do 7250 while d0 <ne> #CONST*20 do. */ 7251 while (! (is_end_of_line[(unsigned char) *s] 7252 || (flag_mri 7253 && *s == '*' 7254 && (s == input_line_pointer 7255 || *(s-1) == ' ' 7256 || *(s-1) == '\t')))) 7257 s++; 7258 --s; 7259 while (*s == ' ' || *s == '\t') 7260 --s; 7261 if (s - input_line_pointer > 1 7262 && s[-1] == '.') 7263 s -= 2; 7264 if (s - input_line_pointer < 2 7265 || strncasecmp (s - 1, "DO", 2) != 0) 7266 { 7267 as_bad (_("missing do")); 7268 ignore_rest_of_line (); 7269 return; 7270 } 7271 7272 n = push_mri_control (mri_while); 7273 7274 colon (n->next); 7275 7276 parse_mri_control_expression (s - 1, qual, (const char *) NULL, n->bottom, 7277 s[1] == '.' ? s[2] : '\0'); 7278 7279 input_line_pointer = s + 1; 7280 if (*input_line_pointer == '.') 7281 input_line_pointer += 2; 7282 7283 if (flag_mri) 7284 { 7285 while (! is_end_of_line[(unsigned char) *input_line_pointer]) 7286 ++input_line_pointer; 7287 } 7288 7289 demand_empty_rest_of_line (); 7290 } 7291 7292 /* Handle the MRI ENDW pseudo-op. */ 7293 7294 static void 7295 s_mri_endw (int ignore ATTRIBUTE_UNUSED) 7296 { 7297 char *buf; 7298 7299 if (mri_control_stack == NULL 7300 || mri_control_stack->type != mri_while) 7301 { 7302 as_bad (_("endw without while")); 7303 ignore_rest_of_line (); 7304 return; 7305 } 7306 7307 buf = XNEWVEC (char, 20 + strlen (mri_control_stack->next)); 7308 sprintf (buf, "bra %s", mri_control_stack->next); 7309 mri_assemble (buf); 7310 free (buf); 7311 7312 colon (mri_control_stack->bottom); 7313 7314 pop_mri_control (); 7315 7316 if (flag_mri) 7317 { 7318 while (! is_end_of_line[(unsigned char) *input_line_pointer]) 7319 ++input_line_pointer; 7320 } 7321 7322 demand_empty_rest_of_line (); 7323 } 7324 7325 /* Parse a .cpu directive. */ 7327 7328 static void 7329 s_m68k_cpu (int ignored ATTRIBUTE_UNUSED) 7330 { 7331 char saved_char; 7332 char *name; 7333 7334 if (initialized) 7335 { 7336 as_bad (_("already assembled instructions")); 7337 ignore_rest_of_line (); 7338 return; 7339 } 7340 7341 name = input_line_pointer; 7342 while (*input_line_pointer && !ISSPACE(*input_line_pointer)) 7343 input_line_pointer++; 7344 saved_char = *input_line_pointer; 7345 *input_line_pointer = 0; 7346 7347 m68k_set_cpu (name, 1, 0); 7348 7349 *input_line_pointer = saved_char; 7350 demand_empty_rest_of_line (); 7351 return; 7352 } 7353 7354 /* Parse a .arch directive. */ 7355 7356 static void 7357 s_m68k_arch (int ignored ATTRIBUTE_UNUSED) 7358 { 7359 char saved_char; 7360 char *name; 7361 7362 if (initialized) 7363 { 7364 as_bad (_("already assembled instructions")); 7365 ignore_rest_of_line (); 7366 return; 7367 } 7368 7369 name = input_line_pointer; 7370 while (*input_line_pointer && *input_line_pointer != ',' 7371 && !ISSPACE (*input_line_pointer)) 7372 input_line_pointer++; 7373 saved_char = *input_line_pointer; 7374 *input_line_pointer = 0; 7375 7376 if (m68k_set_arch (name, 1, 0)) 7377 { 7378 /* Scan extensions. */ 7379 do 7380 { 7381 *input_line_pointer++ = saved_char; 7382 if (!*input_line_pointer || ISSPACE (*input_line_pointer)) 7383 break; 7384 name = input_line_pointer; 7385 while (*input_line_pointer && *input_line_pointer != ',' 7386 && !ISSPACE (*input_line_pointer)) 7387 input_line_pointer++; 7388 saved_char = *input_line_pointer; 7389 *input_line_pointer = 0; 7390 } 7391 while (m68k_set_extension (name, 1, 0)); 7392 } 7393 7394 *input_line_pointer = saved_char; 7395 demand_empty_rest_of_line (); 7396 return; 7397 } 7398 7399 /* Lookup a cpu name in TABLE and return the slot found. Return NULL 7401 if none is found, the caller is responsible for emitting an error 7402 message. If ALLOW_M is non-zero, we allow an initial 'm' on the 7403 cpu name, if it begins with a '6' (possibly skipping an intervening 7404 'c'. We also allow a 'c' in the same place. if NEGATED is 7405 non-zero, we accept a leading 'no-' and *NEGATED is set to true, if 7406 the option is indeed negated. */ 7407 7408 static const struct m68k_cpu * 7409 m68k_lookup_cpu (const char *arg, const struct m68k_cpu *table, 7410 int allow_m, int *negated) 7411 { 7412 /* allow negated value? */ 7413 if (negated) 7414 { 7415 *negated = 0; 7416 7417 if (arg[0] == 'n' && arg[1] == 'o' && arg[2] == '-') 7418 { 7419 arg += 3; 7420 *negated = 1; 7421 } 7422 } 7423 7424 /* Remove 'm' or 'mc' prefix from 68k variants. */ 7425 if (allow_m) 7426 { 7427 if (arg[0] == 'm') 7428 { 7429 if (arg[1] == '6') 7430 arg += 1; 7431 else if (arg[1] == 'c' && arg[2] == '6') 7432 arg += 2; 7433 } 7434 } 7435 else if (arg[0] == 'c' && arg[1] == '6') 7436 arg += 1; 7437 7438 for (; table->name; table++) 7439 if (!strcmp (arg, table->name)) 7440 { 7441 if (table->alias < -1 || table->alias > 1) 7442 as_bad (_("`%s' is deprecated, use `%s'"), 7443 table->name, table[table->alias < 0 ? 1 : -1].name); 7444 return table; 7445 } 7446 return 0; 7447 } 7448 7449 /* Set the cpu, issuing errors if it is unrecognized. */ 7450 7451 static int 7452 m68k_set_cpu (char const *name, int allow_m, int silent) 7453 { 7454 const struct m68k_cpu *cpu; 7455 7456 cpu = m68k_lookup_cpu (name, m68k_cpus, allow_m, NULL); 7457 7458 if (!cpu) 7459 { 7460 if (!silent) 7461 as_bad (_("cpu `%s' unrecognized"), name); 7462 return 0; 7463 } 7464 selected_cpu = cpu; 7465 return 1; 7466 } 7467 7468 /* Set the architecture, issuing errors if it is unrecognized. */ 7469 7470 static int 7471 m68k_set_arch (char const *name, int allow_m, int silent) 7472 { 7473 const struct m68k_cpu *arch; 7474 7475 arch = m68k_lookup_cpu (name, m68k_archs, allow_m, NULL); 7476 7477 if (!arch) 7478 { 7479 if (!silent) 7480 as_bad (_("architecture `%s' unrecognized"), name); 7481 return 0; 7482 } 7483 selected_arch = arch; 7484 return 1; 7485 } 7486 7487 /* Set the architecture extension, issuing errors if it is 7488 unrecognized, or invalid */ 7489 7490 static int 7491 m68k_set_extension (char const *name, int allow_m, int silent) 7492 { 7493 int negated; 7494 const struct m68k_cpu *ext; 7495 7496 ext = m68k_lookup_cpu (name, m68k_extensions, allow_m, &negated); 7497 7498 if (!ext) 7499 { 7500 if (!silent) 7501 as_bad (_("extension `%s' unrecognized"), name); 7502 return 0; 7503 } 7504 7505 if (negated) 7506 not_current_architecture |= (ext->control_regs 7507 ? *(unsigned *)ext->control_regs: ext->arch); 7508 else 7509 current_architecture |= ext->arch; 7510 return 1; 7511 } 7512 7513 /* md_parse_option 7514 Invocation line includes a switch not recognized by the base assembler. 7515 */ 7516 7517 #ifdef OBJ_ELF 7518 const char *md_shortopts = "lSA:m:kQ:V"; 7519 #else 7520 const char *md_shortopts = "lSA:m:k"; 7521 #endif 7522 7523 struct option md_longopts[] = { 7524 #define OPTION_PIC (OPTION_MD_BASE) 7525 {"pic", no_argument, NULL, OPTION_PIC}, 7526 #define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1) 7527 {"register-prefix-optional", no_argument, NULL, 7528 OPTION_REGISTER_PREFIX_OPTIONAL}, 7529 #define OPTION_BITWISE_OR (OPTION_MD_BASE + 2) 7530 {"bitwise-or", no_argument, NULL, OPTION_BITWISE_OR}, 7531 #define OPTION_BASE_SIZE_DEFAULT_16 (OPTION_MD_BASE + 3) 7532 {"base-size-default-16", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_16}, 7533 #define OPTION_BASE_SIZE_DEFAULT_32 (OPTION_MD_BASE + 4) 7534 {"base-size-default-32", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_32}, 7535 #define OPTION_DISP_SIZE_DEFAULT_16 (OPTION_MD_BASE + 5) 7536 {"disp-size-default-16", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_16}, 7537 #define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 6) 7538 {"disp-size-default-32", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_32}, 7539 #define OPTION_PCREL (OPTION_MD_BASE + 7) 7540 {"pcrel", no_argument, NULL, OPTION_PCREL}, 7541 {NULL, no_argument, NULL, 0} 7542 }; 7543 size_t md_longopts_size = sizeof (md_longopts); 7544 7545 int 7546 md_parse_option (int c, const char *arg) 7547 { 7548 switch (c) 7549 { 7550 case 'l': /* -l means keep external to 2 bit offset 7551 rather than 16 bit one. */ 7552 flag_short_refs = 1; 7553 break; 7554 7555 case 'S': /* -S means that jbsr's always turn into 7556 jsr's. */ 7557 flag_long_jumps = 1; 7558 break; 7559 7560 case OPTION_PCREL: /* --pcrel means never turn PC-relative 7561 branches into absolute jumps. */ 7562 flag_keep_pcrel = 1; 7563 break; 7564 7565 case OPTION_PIC: 7566 case 'k': 7567 flag_want_pic = 1; 7568 break; /* -pic, Position Independent Code. */ 7569 7570 case OPTION_REGISTER_PREFIX_OPTIONAL: 7571 flag_reg_prefix_optional = 1; 7572 reg_prefix_optional_seen = 1; 7573 break; 7574 7575 /* -V: SVR4 argument to print version ID. */ 7576 case 'V': 7577 print_version_id (); 7578 break; 7579 7580 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section 7581 should be emitted or not. FIXME: Not implemented. */ 7582 case 'Q': 7583 break; 7584 7585 case OPTION_BITWISE_OR: 7586 { 7587 char *n, *t; 7588 const char *s; 7589 7590 n = XNEWVEC (char, strlen (m68k_comment_chars) + 1); 7591 t = n; 7592 for (s = m68k_comment_chars; *s != '\0'; s++) 7593 if (*s != '|') 7594 *t++ = *s; 7595 *t = '\0'; 7596 m68k_comment_chars = n; 7597 } 7598 break; 7599 7600 case OPTION_BASE_SIZE_DEFAULT_16: 7601 m68k_index_width_default = SIZE_WORD; 7602 break; 7603 7604 case OPTION_BASE_SIZE_DEFAULT_32: 7605 m68k_index_width_default = SIZE_LONG; 7606 break; 7607 7608 case OPTION_DISP_SIZE_DEFAULT_16: 7609 m68k_rel32 = 0; 7610 m68k_rel32_from_cmdline = 1; 7611 break; 7612 7613 case OPTION_DISP_SIZE_DEFAULT_32: 7614 m68k_rel32 = 1; 7615 m68k_rel32_from_cmdline = 1; 7616 break; 7617 7618 case 'A': 7619 #if WARN_DEPRECATED 7620 as_tsktsk (_ ("option `-A%s' is deprecated: use `-%s'", 7621 arg, arg)); 7622 #endif 7623 /* Intentional fall-through. */ 7624 case 'm': 7625 if (!strncmp (arg, "arch=", 5)) 7626 m68k_set_arch (arg + 5, 1, 0); 7627 else if (!strncmp (arg, "cpu=", 4)) 7628 m68k_set_cpu (arg + 4, 1, 0); 7629 else if (m68k_set_extension (arg, 0, 1)) 7630 ; 7631 else if (m68k_set_arch (arg, 0, 1)) 7632 ; 7633 else if (m68k_set_cpu (arg, 0, 1)) 7634 ; 7635 else 7636 return 0; 7637 break; 7638 7639 default: 7640 return 0; 7641 } 7642 7643 return 1; 7644 } 7645 7646 /* Setup tables from the selected arch and/or cpu */ 7647 7648 static void 7649 m68k_init_arch (void) 7650 { 7651 if (not_current_architecture & current_architecture) 7652 { 7653 as_bad (_("architecture features both enabled and disabled")); 7654 not_current_architecture &= ~current_architecture; 7655 } 7656 if (selected_arch) 7657 { 7658 current_architecture |= selected_arch->arch; 7659 control_regs = selected_arch->control_regs; 7660 } 7661 else 7662 current_architecture |= selected_cpu->arch; 7663 7664 current_architecture &= ~not_current_architecture; 7665 7666 if ((current_architecture & (cfloat | m68881)) == (cfloat | m68881)) 7667 { 7668 /* Determine which float is really meant. */ 7669 if (current_architecture & (m68k_mask & ~m68881)) 7670 current_architecture ^= cfloat; 7671 else 7672 current_architecture ^= m68881; 7673 } 7674 7675 if (selected_cpu) 7676 { 7677 control_regs = selected_cpu->control_regs; 7678 if (current_architecture & ~selected_cpu->arch) 7679 { 7680 as_bad (_("selected processor does not have all features of selected architecture")); 7681 current_architecture 7682 = selected_cpu->arch & ~not_current_architecture; 7683 } 7684 } 7685 7686 if ((current_architecture & m68k_mask) 7687 && (current_architecture & ~m68k_mask)) 7688 { 7689 as_bad (_ ("m68k and cf features both selected")); 7690 if (current_architecture & m68k_mask) 7691 current_architecture &= m68k_mask; 7692 else 7693 current_architecture &= ~m68k_mask; 7694 } 7695 7696 /* Permit m68881 specification with all cpus; those that can't work 7697 with a coprocessor could be doing emulation. */ 7698 if (current_architecture & m68851) 7699 { 7700 if (current_architecture & m68040) 7701 as_warn (_("68040 and 68851 specified; mmu instructions may assemble incorrectly")); 7702 } 7703 /* What other incompatibilities could we check for? */ 7704 7705 if (cpu_of_arch (current_architecture) < m68020 7706 || arch_coldfire_p (current_architecture)) 7707 md_relax_table[TAB (PCINDEX, BYTE)].rlx_more = 0; 7708 7709 initialized = 1; 7710 } 7711 7712 void 7713 md_show_usage (FILE *stream) 7714 { 7715 const char *default_cpu = TARGET_CPU; 7716 int i; 7717 7718 /* Get the canonical name for the default target CPU. */ 7719 if (*default_cpu == 'm') 7720 default_cpu++; 7721 for (i = 0; m68k_cpus[i].name; i++) 7722 { 7723 if (strcasecmp (default_cpu, m68k_cpus[i].name) == 0) 7724 { 7725 while (m68k_cpus[i].alias > 0) 7726 i--; 7727 while (m68k_cpus[i].alias < 0) 7728 i++; 7729 default_cpu = m68k_cpus[i].name; 7730 } 7731 } 7732 7733 fprintf (stream, _("\ 7734 -march=<arch> set architecture\n\ 7735 -mcpu=<cpu> set cpu [default %s]\n\ 7736 "), default_cpu); 7737 for (i = 0; m68k_extensions[i].name; i++) 7738 fprintf (stream, _("\ 7739 -m[no-]%-16s enable/disable%s architecture extension\n\ 7740 "), m68k_extensions[i].name, 7741 m68k_extensions[i].alias > 0 ? " ColdFire" 7742 : m68k_extensions[i].alias < 0 ? " m68k" : ""); 7743 7744 fprintf (stream, _("\ 7745 -l use 1 word for refs to undefined symbols [default 2]\n\ 7746 -pic, -k generate position independent code\n\ 7747 -S turn jbsr into jsr\n\ 7748 --pcrel never turn PC-relative branches into absolute jumps\n\ 7749 --register-prefix-optional\n\ 7750 recognize register names without prefix character\n\ 7751 --bitwise-or do not treat `|' as a comment character\n\ 7752 --base-size-default-16 base reg without size is 16 bits\n\ 7753 --base-size-default-32 base reg without size is 32 bits (default)\n\ 7754 --disp-size-default-16 displacement with unknown size is 16 bits\n\ 7755 --disp-size-default-32 displacement with unknown size is 32 bits (default)\n\ 7756 ")); 7757 7758 fprintf (stream, _("Architecture variants are: ")); 7759 for (i = 0; m68k_archs[i].name; i++) 7760 { 7761 if (i) 7762 fprintf (stream, " | "); 7763 fprintf (stream, "%s", m68k_archs[i].name); 7764 } 7765 fprintf (stream, "\n"); 7766 7767 fprintf (stream, _("Processor variants are: ")); 7768 for (i = 0; m68k_cpus[i].name; i++) 7769 { 7770 if (i) 7771 fprintf (stream, " | "); 7772 fprintf (stream, "%s", m68k_cpus[i].name); 7773 } 7774 fprintf (stream, _("\n")); 7775 } 7776 7777 #ifdef TEST2 7779 7780 /* TEST2: Test md_assemble() */ 7781 /* Warning, this routine probably doesn't work anymore. */ 7782 int 7783 main (void) 7784 { 7785 struct m68k_it the_ins; 7786 char buf[120]; 7787 char *cp; 7788 int n; 7789 7790 m68k_ip_begin (); 7791 for (;;) 7792 { 7793 if (!gets (buf) || !*buf) 7794 break; 7795 if (buf[0] == '|' || buf[1] == '.') 7796 continue; 7797 for (cp = buf; *cp; cp++) 7798 if (*cp == '\t') 7799 *cp = ' '; 7800 if (is_label (buf)) 7801 continue; 7802 memset (&the_ins, '\0', sizeof (the_ins)); 7803 m68k_ip (&the_ins, buf); 7804 if (the_ins.error) 7805 { 7806 printf (_("Error %s in %s\n"), the_ins.error, buf); 7807 } 7808 else 7809 { 7810 printf (_("Opcode(%d.%s): "), the_ins.numo, the_ins.args); 7811 for (n = 0; n < the_ins.numo; n++) 7812 printf (" 0x%x", the_ins.opcode[n] & 0xffff); 7813 printf (" "); 7814 print_the_insn (&the_ins.opcode[0], stdout); 7815 (void) putchar ('\n'); 7816 } 7817 for (n = 0; n < strlen (the_ins.args) / 2; n++) 7818 { 7819 if (the_ins.operands[n].error) 7820 { 7821 printf ("op%d Error %s in %s\n", n, the_ins.operands[n].error, buf); 7822 continue; 7823 } 7824 printf ("mode %d, reg %d, ", the_ins.operands[n].mode, 7825 the_ins.operands[n].reg); 7826 if (the_ins.operands[n].b_const) 7827 printf ("Constant: '%.*s', ", 7828 1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const, 7829 the_ins.operands[n].b_const); 7830 printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg, 7831 the_ins.operands[n].isiz, the_ins.operands[n].imul); 7832 if (the_ins.operands[n].b_iadd) 7833 printf ("Iadd: '%.*s',", 7834 1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd, 7835 the_ins.operands[n].b_iadd); 7836 putchar ('\n'); 7837 } 7838 } 7839 m68k_ip_end (); 7840 return 0; 7841 } 7842 7843 int 7844 is_label (char *str) 7845 { 7846 while (*str == ' ') 7847 str++; 7848 while (*str && *str != ' ') 7849 str++; 7850 if (str[-1] == ':' || str[1] == '=') 7851 return 1; 7852 return 0; 7853 } 7854 7855 #endif 7856 7857 /* Possible states for relaxation: 7858 7859 0 0 branch offset byte (bra, etc) 7860 0 1 word 7861 0 2 long 7862 7863 1 0 indexed offsets byte a0@(32,d4:w:1) etc 7864 1 1 word 7865 1 2 long 7866 7867 2 0 two-offset index word-word a0@(32,d4)@(45) etc 7868 2 1 word-long 7869 2 2 long-word 7870 2 3 long-long 7871 7872 */ 7873 7874 /* We have no need to default values of symbols. */ 7875 7876 symbolS * 7877 md_undefined_symbol (char *name ATTRIBUTE_UNUSED) 7878 { 7879 return 0; 7880 } 7881 7882 /* Round up a section size to the appropriate boundary. */ 7883 valueT 7884 md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size) 7885 { 7886 #ifdef OBJ_AOUT 7887 /* For a.out, force the section size to be aligned. If we don't do 7888 this, BFD will align it for us, but it will not write out the 7889 final bytes of the section. This may be a bug in BFD, but it is 7890 easier to fix it here since that is how the other a.out targets 7891 work. */ 7892 int align; 7893 7894 align = bfd_get_section_alignment (stdoutput, segment); 7895 size = ((size + (1 << align) - 1) & (-((valueT) 1 << align))); 7896 #endif 7897 7898 return size; 7899 } 7900 7901 /* Exactly what point is a PC-relative offset relative TO? 7902 On the 68k, it is relative to the address of the first extension 7903 word. The difference between the addresses of the offset and the 7904 first extension word is stored in fx_pcrel_adjust. */ 7905 long 7906 md_pcrel_from (fixS *fixP) 7907 { 7908 int adjust; 7909 7910 adjust = fixP->fx_pcrel_adjust; 7911 if (adjust == 64) 7912 adjust = -1; 7913 return fixP->fx_where + fixP->fx_frag->fr_address - adjust; 7914 } 7915 7916 #ifdef OBJ_ELF 7917 void 7918 m68k_elf_final_processing (void) 7919 { 7920 unsigned flags = 0; 7921 7922 if (arch_coldfire_fpu (current_architecture)) 7923 flags |= EF_M68K_CFV4E; 7924 /* Set file-specific flags if this is a cpu32 processor. */ 7925 if (cpu_of_arch (current_architecture) & cpu32) 7926 flags |= EF_M68K_CPU32; 7927 else if (cpu_of_arch (current_architecture) & fido_a) 7928 flags |= EF_M68K_FIDO; 7929 else if ((cpu_of_arch (current_architecture) & m68000up) 7930 && !(cpu_of_arch (current_architecture) & m68020up)) 7931 flags |= EF_M68K_M68000; 7932 7933 if (current_architecture & mcfisa_a) 7934 { 7935 static const unsigned isa_features[][2] = 7936 { 7937 {EF_M68K_CF_ISA_A_NODIV,mcfisa_a}, 7938 {EF_M68K_CF_ISA_A, mcfisa_a|mcfhwdiv}, 7939 {EF_M68K_CF_ISA_A_PLUS, mcfisa_a|mcfisa_aa|mcfhwdiv|mcfusp}, 7940 {EF_M68K_CF_ISA_B_NOUSP,mcfisa_a|mcfisa_b|mcfhwdiv}, 7941 {EF_M68K_CF_ISA_B, mcfisa_a|mcfisa_b|mcfhwdiv|mcfusp}, 7942 {EF_M68K_CF_ISA_C, mcfisa_a|mcfisa_c|mcfhwdiv|mcfusp}, 7943 {EF_M68K_CF_ISA_C_NODIV,mcfisa_a|mcfisa_c|mcfusp}, 7944 {0,0}, 7945 }; 7946 static const unsigned mac_features[][2] = 7947 { 7948 {EF_M68K_CF_MAC, mcfmac}, 7949 {EF_M68K_CF_EMAC, mcfemac}, 7950 {0,0}, 7951 }; 7952 unsigned ix; 7953 unsigned pattern; 7954 7955 pattern = (current_architecture 7956 & (mcfisa_a|mcfisa_aa|mcfisa_b|mcfisa_c|mcfhwdiv|mcfusp)); 7957 for (ix = 0; isa_features[ix][1]; ix++) 7958 { 7959 if (pattern == isa_features[ix][1]) 7960 { 7961 flags |= isa_features[ix][0]; 7962 break; 7963 } 7964 } 7965 if (!isa_features[ix][1]) 7966 { 7967 cf_bad: 7968 as_warn (_("Not a defined coldfire architecture")); 7969 } 7970 else 7971 { 7972 if (current_architecture & cfloat) 7973 flags |= EF_M68K_CF_FLOAT | EF_M68K_CFV4E; 7974 7975 pattern = current_architecture & (mcfmac|mcfemac); 7976 if (pattern) 7977 { 7978 for (ix = 0; mac_features[ix][1]; ix++) 7979 { 7980 if (pattern == mac_features[ix][1]) 7981 { 7982 flags |= mac_features[ix][0]; 7983 break; 7984 } 7985 } 7986 if (!mac_features[ix][1]) 7987 goto cf_bad; 7988 } 7989 } 7990 } 7991 elf_elfheader (stdoutput)->e_flags |= flags; 7992 } 7993 7994 /* Parse @TLSLDO and return the desired relocation. */ 7995 static bfd_reloc_code_real_type 7996 m68k_elf_suffix (char **str_p, expressionS *exp_p) 7997 { 7998 char ident[20]; 7999 char *str = *str_p; 8000 char *str2; 8001 int ch; 8002 int len; 8003 8004 if (*str++ != '@') 8005 return BFD_RELOC_UNUSED; 8006 8007 for (ch = *str, str2 = ident; 8008 (str2 < ident + sizeof (ident) - 1 8009 && (ISALNUM (ch) || ch == '@')); 8010 ch = *++str) 8011 { 8012 *str2++ = ch; 8013 } 8014 8015 *str2 = '\0'; 8016 len = str2 - ident; 8017 8018 if (strncmp (ident, "TLSLDO", 6) == 0 8019 && len == 6) 8020 { 8021 /* Now check for identifier@suffix+constant. */ 8022 if (*str == '-' || *str == '+') 8023 { 8024 char *orig_line = input_line_pointer; 8025 expressionS new_exp; 8026 8027 input_line_pointer = str; 8028 expression (&new_exp); 8029 if (new_exp.X_op == O_constant) 8030 { 8031 exp_p->X_add_number += new_exp.X_add_number; 8032 str = input_line_pointer; 8033 } 8034 8035 if (&input_line_pointer != str_p) 8036 input_line_pointer = orig_line; 8037 } 8038 *str_p = str; 8039 8040 return BFD_RELOC_68K_TLS_LDO32; 8041 } 8042 8043 return BFD_RELOC_UNUSED; 8044 } 8045 8046 /* Handles .long <tls_symbol>+0x8000 debug info. 8047 Clobbers input_line_pointer, checks end-of-line. 8048 Adapted from tc-ppc.c:ppc_elf_cons. */ 8049 static void 8050 m68k_elf_cons (int nbytes /* 4=.long */) 8051 { 8052 if (is_it_end_of_statement ()) 8053 { 8054 demand_empty_rest_of_line (); 8055 return; 8056 } 8057 8058 do 8059 { 8060 expressionS exp; 8061 bfd_reloc_code_real_type reloc; 8062 8063 expression (&exp); 8064 if (exp.X_op == O_symbol 8065 && *input_line_pointer == '@' 8066 && (reloc = m68k_elf_suffix (&input_line_pointer, 8067 &exp)) != BFD_RELOC_UNUSED) 8068 { 8069 reloc_howto_type *reloc_howto; 8070 int size; 8071 8072 reloc_howto = bfd_reloc_type_lookup (stdoutput, reloc); 8073 size = bfd_get_reloc_size (reloc_howto); 8074 8075 if (size > nbytes) 8076 { 8077 as_bad (_("%s relocations do not fit in %d bytes\n"), 8078 reloc_howto->name, nbytes); 8079 } 8080 else 8081 { 8082 char *p; 8083 int offset; 8084 8085 p = frag_more (nbytes); 8086 offset = 0; 8087 if (target_big_endian) 8088 offset = nbytes - size; 8089 fix_new_exp (frag_now, p - frag_now->fr_literal + offset, size, 8090 &exp, 0, reloc); 8091 } 8092 } 8093 else 8094 emit_expr (&exp, (unsigned int) nbytes); 8095 } 8096 while (*input_line_pointer++ == ','); 8097 8098 /* Put terminator back into stream. */ 8099 input_line_pointer--; 8100 demand_empty_rest_of_line (); 8101 } 8102 #endif 8103 8104 int 8105 tc_m68k_regname_to_dw2regnum (const char *regname) 8106 { 8107 unsigned int regnum; 8108 static const char *const regnames[] = 8109 { 8110 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", 8111 "a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp", 8112 "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7", 8113 "pc" 8114 }; 8115 8116 for (regnum = 0; regnum < ARRAY_SIZE (regnames); regnum++) 8117 if (strcmp (regname, regnames[regnum]) == 0) 8118 return regnum; 8119 8120 return -1; 8121 } 8122 8123 void 8124 tc_m68k_frame_initial_instructions (void) 8125 { 8126 static int sp_regno = -1; 8127 8128 if (sp_regno < 0) 8129 sp_regno = tc_m68k_regname_to_dw2regnum ("sp"); 8130 8131 cfi_add_CFA_def_cfa (sp_regno, -DWARF2_CIE_DATA_ALIGNMENT); 8132 cfi_add_CFA_offset (DWARF2_DEFAULT_RETURN_COLUMN, DWARF2_CIE_DATA_ALIGNMENT); 8133 } 8134 8135 /* Check and emit error if broken-word handling has failed to fix up a 8136 case-table. This is called from write.c, after doing everything it 8137 knows about how to handle broken words. */ 8138 8139 void 8140 tc_m68k_check_adjusted_broken_word (offsetT new_offset, struct broken_word *brokwP) 8141 { 8142 if (new_offset > 32767 || new_offset < -32768) 8143 as_bad_where (brokwP->frag->fr_file, brokwP->frag->fr_line, 8144 _("Adjusted signed .word (%#lx) overflows: `switch'-statement too large."), 8145 (long) new_offset); 8146 } 8147 8148
