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      1 /* Print i386 instructions for GDB, the GNU debugger.
      2    Copyright (C) 1988-2016 Free Software Foundation, Inc.
      3 
      4    This file is part of the GNU opcodes library.
      5 
      6    This library is free software; you can redistribute it and/or modify
      7    it under the terms of the GNU General Public License as published by
      8    the Free Software Foundation; either version 3, or (at your option)
      9    any later version.
     10 
     11    It is distributed in the hope that it will be useful, but WITHOUT
     12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
     13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
     14    License for more details.
     15 
     16    You should have received a copy of the GNU General Public License
     17    along with this program; if not, write to the Free Software
     18    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
     19    MA 02110-1301, USA.  */
     20 
     21 
     22 /* 80386 instruction printer by Pace Willisson (pace (at) prep.ai.mit.edu)
     23    July 1988
     24     modified by John Hassey (hassey (at) dg-rtp.dg.com)
     25     x86-64 support added by Jan Hubicka (jh (at) suse.cz)
     26     VIA PadLock support by Michal Ludvig (mludvig (at) suse.cz).  */
     27 
     28 /* The main tables describing the instructions is essentially a copy
     29    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
     30    Programmers Manual.  Usually, there is a capital letter, followed
     31    by a small letter.  The capital letter tell the addressing mode,
     32    and the small letter tells about the operand size.  Refer to
     33    the Intel manual for details.  */
     34 
     35 #include "sysdep.h"
     36 #include "dis-asm.h"
     37 #include "opintl.h"
     38 #include "opcode/i386.h"
     39 #include "libiberty.h"
     40 
     41 #include <setjmp.h>
     42 
     43 static int print_insn (bfd_vma, disassemble_info *);
     44 static void dofloat (int);
     45 static void OP_ST (int, int);
     46 static void OP_STi (int, int);
     47 static int putop (const char *, int);
     48 static void oappend (const char *);
     49 static void append_seg (void);
     50 static void OP_indirE (int, int);
     51 static void print_operand_value (char *, int, bfd_vma);
     52 static void OP_E_register (int, int);
     53 static void OP_E_memory (int, int);
     54 static void print_displacement (char *, bfd_vma);
     55 static void OP_E (int, int);
     56 static void OP_G (int, int);
     57 static bfd_vma get64 (void);
     58 static bfd_signed_vma get32 (void);
     59 static bfd_signed_vma get32s (void);
     60 static int get16 (void);
     61 static void set_op (bfd_vma, int);
     62 static void OP_Skip_MODRM (int, int);
     63 static void OP_REG (int, int);
     64 static void OP_IMREG (int, int);
     65 static void OP_I (int, int);
     66 static void OP_I64 (int, int);
     67 static void OP_sI (int, int);
     68 static void OP_J (int, int);
     69 static void OP_SEG (int, int);
     70 static void OP_DIR (int, int);
     71 static void OP_OFF (int, int);
     72 static void OP_OFF64 (int, int);
     73 static void ptr_reg (int, int);
     74 static void OP_ESreg (int, int);
     75 static void OP_DSreg (int, int);
     76 static void OP_C (int, int);
     77 static void OP_D (int, int);
     78 static void OP_T (int, int);
     79 static void OP_R (int, int);
     80 static void OP_MMX (int, int);
     81 static void OP_XMM (int, int);
     82 static void OP_EM (int, int);
     83 static void OP_EX (int, int);
     84 static void OP_EMC (int,int);
     85 static void OP_MXC (int,int);
     86 static void OP_MS (int, int);
     87 static void OP_XS (int, int);
     88 static void OP_M (int, int);
     89 static void OP_VEX (int, int);
     90 static void OP_EX_Vex (int, int);
     91 static void OP_EX_VexW (int, int);
     92 static void OP_EX_VexImmW (int, int);
     93 static void OP_XMM_Vex (int, int);
     94 static void OP_XMM_VexW (int, int);
     95 static void OP_Rounding (int, int);
     96 static void OP_REG_VexI4 (int, int);
     97 static void PCLMUL_Fixup (int, int);
     98 static void VEXI4_Fixup (int, int);
     99 static void VZERO_Fixup (int, int);
    100 static void VCMP_Fixup (int, int);
    101 static void VPCMP_Fixup (int, int);
    102 static void OP_0f07 (int, int);
    103 static void OP_Monitor (int, int);
    104 static void OP_Mwait (int, int);
    105 static void OP_Mwaitx (int, int);
    106 static void NOP_Fixup1 (int, int);
    107 static void NOP_Fixup2 (int, int);
    108 static void OP_3DNowSuffix (int, int);
    109 static void CMP_Fixup (int, int);
    110 static void BadOp (void);
    111 static void REP_Fixup (int, int);
    112 static void BND_Fixup (int, int);
    113 static void HLE_Fixup1 (int, int);
    114 static void HLE_Fixup2 (int, int);
    115 static void HLE_Fixup3 (int, int);
    116 static void CMPXCHG8B_Fixup (int, int);
    117 static void XMM_Fixup (int, int);
    118 static void CRC32_Fixup (int, int);
    119 static void FXSAVE_Fixup (int, int);
    120 static void OP_LWPCB_E (int, int);
    121 static void OP_LWP_E (int, int);
    122 static void OP_Vex_2src_1 (int, int);
    123 static void OP_Vex_2src_2 (int, int);
    124 
    125 static void MOVBE_Fixup (int, int);
    126 
    127 static void OP_Mask (int, int);
    128 
    129 struct dis_private {
    130   /* Points to first byte not fetched.  */
    131   bfd_byte *max_fetched;
    132   bfd_byte the_buffer[MAX_MNEM_SIZE];
    133   bfd_vma insn_start;
    134   int orig_sizeflag;
    135   OPCODES_SIGJMP_BUF bailout;
    136 };
    137 
    138 enum address_mode
    139 {
    140   mode_16bit,
    141   mode_32bit,
    142   mode_64bit
    143 };
    144 
    145 enum address_mode address_mode;
    146 
    147 /* Flags for the prefixes for the current instruction.  See below.  */
    148 static int prefixes;
    149 
    150 /* REX prefix the current instruction.  See below.  */
    151 static int rex;
    152 /* Bits of REX we've already used.  */
    153 static int rex_used;
    154 /* REX bits in original REX prefix ignored.  */
    155 static int rex_ignored;
    156 /* Mark parts used in the REX prefix.  When we are testing for
    157    empty prefix (for 8bit register REX extension), just mask it
    158    out.  Otherwise test for REX bit is excuse for existence of REX
    159    only in case value is nonzero.  */
    160 #define USED_REX(value)					\
    161   {							\
    162     if (value)						\
    163       {							\
    164 	if ((rex & value))				\
    165 	  rex_used |= (value) | REX_OPCODE;		\
    166       }							\
    167     else						\
    168       rex_used |= REX_OPCODE;				\
    169   }
    170 
    171 /* Flags for prefixes which we somehow handled when printing the
    172    current instruction.  */
    173 static int used_prefixes;
    174 
    175 /* Flags stored in PREFIXES.  */
    176 #define PREFIX_REPZ 1
    177 #define PREFIX_REPNZ 2
    178 #define PREFIX_LOCK 4
    179 #define PREFIX_CS 8
    180 #define PREFIX_SS 0x10
    181 #define PREFIX_DS 0x20
    182 #define PREFIX_ES 0x40
    183 #define PREFIX_FS 0x80
    184 #define PREFIX_GS 0x100
    185 #define PREFIX_DATA 0x200
    186 #define PREFIX_ADDR 0x400
    187 #define PREFIX_FWAIT 0x800
    188 
    189 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
    190    to ADDR (exclusive) are valid.  Returns 1 for success, longjmps
    191    on error.  */
    192 #define FETCH_DATA(info, addr) \
    193   ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
    194    ? 1 : fetch_data ((info), (addr)))
    195 
    196 static int
    197 fetch_data (struct disassemble_info *info, bfd_byte *addr)
    198 {
    199   int status;
    200   struct dis_private *priv = (struct dis_private *) info->private_data;
    201   bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
    202 
    203   if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
    204     status = (*info->read_memory_func) (start,
    205 					priv->max_fetched,
    206 					addr - priv->max_fetched,
    207 					info);
    208   else
    209     status = -1;
    210   if (status != 0)
    211     {
    212       /* If we did manage to read at least one byte, then
    213 	 print_insn_i386 will do something sensible.  Otherwise, print
    214 	 an error.  We do that here because this is where we know
    215 	 STATUS.  */
    216       if (priv->max_fetched == priv->the_buffer)
    217 	(*info->memory_error_func) (status, start, info);
    218       OPCODES_SIGLONGJMP (priv->bailout, 1);
    219     }
    220   else
    221     priv->max_fetched = addr;
    222   return 1;
    223 }
    224 
    225 /* Possible values for prefix requirement.  */
    226 #define PREFIX_IGNORED_SHIFT	16
    227 #define PREFIX_IGNORED_REPZ	(PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
    228 #define PREFIX_IGNORED_REPNZ	(PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
    229 #define PREFIX_IGNORED_DATA	(PREFIX_DATA << PREFIX_IGNORED_SHIFT)
    230 #define PREFIX_IGNORED_ADDR	(PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
    231 #define PREFIX_IGNORED_LOCK	(PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
    232 
    233 /* Opcode prefixes.  */
    234 #define PREFIX_OPCODE		(PREFIX_REPZ \
    235 				 | PREFIX_REPNZ \
    236 				 | PREFIX_DATA)
    237 
    238 /* Prefixes ignored.  */
    239 #define PREFIX_IGNORED		(PREFIX_IGNORED_REPZ \
    240 				 | PREFIX_IGNORED_REPNZ \
    241 				 | PREFIX_IGNORED_DATA)
    242 
    243 #define XX { NULL, 0 }
    244 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
    245 
    246 #define Eb { OP_E, b_mode }
    247 #define Ebnd { OP_E, bnd_mode }
    248 #define EbS { OP_E, b_swap_mode }
    249 #define Ev { OP_E, v_mode }
    250 #define Ev_bnd { OP_E, v_bnd_mode }
    251 #define EvS { OP_E, v_swap_mode }
    252 #define Ed { OP_E, d_mode }
    253 #define Edq { OP_E, dq_mode }
    254 #define Edqw { OP_E, dqw_mode }
    255 #define EdqwS { OP_E, dqw_swap_mode }
    256 #define Edqb { OP_E, dqb_mode }
    257 #define Edb { OP_E, db_mode }
    258 #define Edw { OP_E, dw_mode }
    259 #define Edqd { OP_E, dqd_mode }
    260 #define Eq { OP_E, q_mode }
    261 #define indirEv { OP_indirE, indir_v_mode }
    262 #define indirEp { OP_indirE, f_mode }
    263 #define stackEv { OP_E, stack_v_mode }
    264 #define Em { OP_E, m_mode }
    265 #define Ew { OP_E, w_mode }
    266 #define M { OP_M, 0 }		/* lea, lgdt, etc. */
    267 #define Ma { OP_M, a_mode }
    268 #define Mb { OP_M, b_mode }
    269 #define Md { OP_M, d_mode }
    270 #define Mo { OP_M, o_mode }
    271 #define Mp { OP_M, f_mode }		/* 32 or 48 bit memory operand for LDS, LES etc */
    272 #define Mq { OP_M, q_mode }
    273 #define Mx { OP_M, x_mode }
    274 #define Mxmm { OP_M, xmm_mode }
    275 #define Gb { OP_G, b_mode }
    276 #define Gbnd { OP_G, bnd_mode }
    277 #define Gv { OP_G, v_mode }
    278 #define Gd { OP_G, d_mode }
    279 #define Gdq { OP_G, dq_mode }
    280 #define Gm { OP_G, m_mode }
    281 #define Gw { OP_G, w_mode }
    282 #define Rd { OP_R, d_mode }
    283 #define Rdq { OP_R, dq_mode }
    284 #define Rm { OP_R, m_mode }
    285 #define Ib { OP_I, b_mode }
    286 #define sIb { OP_sI, b_mode }	/* sign extened byte */
    287 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
    288 #define Iv { OP_I, v_mode }
    289 #define sIv { OP_sI, v_mode }
    290 #define Iq { OP_I, q_mode }
    291 #define Iv64 { OP_I64, v_mode }
    292 #define Iw { OP_I, w_mode }
    293 #define I1 { OP_I, const_1_mode }
    294 #define Jb { OP_J, b_mode }
    295 #define Jv { OP_J, v_mode }
    296 #define Cm { OP_C, m_mode }
    297 #define Dm { OP_D, m_mode }
    298 #define Td { OP_T, d_mode }
    299 #define Skip_MODRM { OP_Skip_MODRM, 0 }
    300 
    301 #define RMeAX { OP_REG, eAX_reg }
    302 #define RMeBX { OP_REG, eBX_reg }
    303 #define RMeCX { OP_REG, eCX_reg }
    304 #define RMeDX { OP_REG, eDX_reg }
    305 #define RMeSP { OP_REG, eSP_reg }
    306 #define RMeBP { OP_REG, eBP_reg }
    307 #define RMeSI { OP_REG, eSI_reg }
    308 #define RMeDI { OP_REG, eDI_reg }
    309 #define RMrAX { OP_REG, rAX_reg }
    310 #define RMrBX { OP_REG, rBX_reg }
    311 #define RMrCX { OP_REG, rCX_reg }
    312 #define RMrDX { OP_REG, rDX_reg }
    313 #define RMrSP { OP_REG, rSP_reg }
    314 #define RMrBP { OP_REG, rBP_reg }
    315 #define RMrSI { OP_REG, rSI_reg }
    316 #define RMrDI { OP_REG, rDI_reg }
    317 #define RMAL { OP_REG, al_reg }
    318 #define RMCL { OP_REG, cl_reg }
    319 #define RMDL { OP_REG, dl_reg }
    320 #define RMBL { OP_REG, bl_reg }
    321 #define RMAH { OP_REG, ah_reg }
    322 #define RMCH { OP_REG, ch_reg }
    323 #define RMDH { OP_REG, dh_reg }
    324 #define RMBH { OP_REG, bh_reg }
    325 #define RMAX { OP_REG, ax_reg }
    326 #define RMDX { OP_REG, dx_reg }
    327 
    328 #define eAX { OP_IMREG, eAX_reg }
    329 #define eBX { OP_IMREG, eBX_reg }
    330 #define eCX { OP_IMREG, eCX_reg }
    331 #define eDX { OP_IMREG, eDX_reg }
    332 #define eSP { OP_IMREG, eSP_reg }
    333 #define eBP { OP_IMREG, eBP_reg }
    334 #define eSI { OP_IMREG, eSI_reg }
    335 #define eDI { OP_IMREG, eDI_reg }
    336 #define AL { OP_IMREG, al_reg }
    337 #define CL { OP_IMREG, cl_reg }
    338 #define DL { OP_IMREG, dl_reg }
    339 #define BL { OP_IMREG, bl_reg }
    340 #define AH { OP_IMREG, ah_reg }
    341 #define CH { OP_IMREG, ch_reg }
    342 #define DH { OP_IMREG, dh_reg }
    343 #define BH { OP_IMREG, bh_reg }
    344 #define AX { OP_IMREG, ax_reg }
    345 #define DX { OP_IMREG, dx_reg }
    346 #define zAX { OP_IMREG, z_mode_ax_reg }
    347 #define indirDX { OP_IMREG, indir_dx_reg }
    348 
    349 #define Sw { OP_SEG, w_mode }
    350 #define Sv { OP_SEG, v_mode }
    351 #define Ap { OP_DIR, 0 }
    352 #define Ob { OP_OFF64, b_mode }
    353 #define Ov { OP_OFF64, v_mode }
    354 #define Xb { OP_DSreg, eSI_reg }
    355 #define Xv { OP_DSreg, eSI_reg }
    356 #define Xz { OP_DSreg, eSI_reg }
    357 #define Yb { OP_ESreg, eDI_reg }
    358 #define Yv { OP_ESreg, eDI_reg }
    359 #define DSBX { OP_DSreg, eBX_reg }
    360 
    361 #define es { OP_REG, es_reg }
    362 #define ss { OP_REG, ss_reg }
    363 #define cs { OP_REG, cs_reg }
    364 #define ds { OP_REG, ds_reg }
    365 #define fs { OP_REG, fs_reg }
    366 #define gs { OP_REG, gs_reg }
    367 
    368 #define MX { OP_MMX, 0 }
    369 #define XM { OP_XMM, 0 }
    370 #define XMScalar { OP_XMM, scalar_mode }
    371 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
    372 #define XMM { OP_XMM, xmm_mode }
    373 #define XMxmmq { OP_XMM, xmmq_mode }
    374 #define EM { OP_EM, v_mode }
    375 #define EMS { OP_EM, v_swap_mode }
    376 #define EMd { OP_EM, d_mode }
    377 #define EMx { OP_EM, x_mode }
    378 #define EXw { OP_EX, w_mode }
    379 #define EXd { OP_EX, d_mode }
    380 #define EXdScalar { OP_EX, d_scalar_mode }
    381 #define EXdS { OP_EX, d_swap_mode }
    382 #define EXdScalarS { OP_EX, d_scalar_swap_mode }
    383 #define EXq { OP_EX, q_mode }
    384 #define EXqScalar { OP_EX, q_scalar_mode }
    385 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
    386 #define EXqS { OP_EX, q_swap_mode }
    387 #define EXx { OP_EX, x_mode }
    388 #define EXxS { OP_EX, x_swap_mode }
    389 #define EXxmm { OP_EX, xmm_mode }
    390 #define EXymm { OP_EX, ymm_mode }
    391 #define EXxmmq { OP_EX, xmmq_mode }
    392 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
    393 #define EXxmm_mb { OP_EX, xmm_mb_mode }
    394 #define EXxmm_mw { OP_EX, xmm_mw_mode }
    395 #define EXxmm_md { OP_EX, xmm_md_mode }
    396 #define EXxmm_mq { OP_EX, xmm_mq_mode }
    397 #define EXxmm_mdq { OP_EX, xmm_mdq_mode }
    398 #define EXxmmdw { OP_EX, xmmdw_mode }
    399 #define EXxmmqd { OP_EX, xmmqd_mode }
    400 #define EXymmq { OP_EX, ymmq_mode }
    401 #define EXVexWdq { OP_EX, vex_w_dq_mode }
    402 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
    403 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
    404 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
    405 #define MS { OP_MS, v_mode }
    406 #define XS { OP_XS, v_mode }
    407 #define EMCq { OP_EMC, q_mode }
    408 #define MXC { OP_MXC, 0 }
    409 #define OPSUF { OP_3DNowSuffix, 0 }
    410 #define CMP { CMP_Fixup, 0 }
    411 #define XMM0 { XMM_Fixup, 0 }
    412 #define FXSAVE { FXSAVE_Fixup, 0 }
    413 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
    414 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
    415 
    416 #define Vex { OP_VEX, vex_mode }
    417 #define VexScalar { OP_VEX, vex_scalar_mode }
    418 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
    419 #define Vex128 { OP_VEX, vex128_mode }
    420 #define Vex256 { OP_VEX, vex256_mode }
    421 #define VexGdq { OP_VEX, dq_mode }
    422 #define VexI4 { VEXI4_Fixup, 0}
    423 #define EXdVex { OP_EX_Vex, d_mode }
    424 #define EXdVexS { OP_EX_Vex, d_swap_mode }
    425 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
    426 #define EXqVex { OP_EX_Vex, q_mode }
    427 #define EXqVexS { OP_EX_Vex, q_swap_mode }
    428 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
    429 #define EXVexW { OP_EX_VexW, x_mode }
    430 #define EXdVexW { OP_EX_VexW, d_mode }
    431 #define EXqVexW { OP_EX_VexW, q_mode }
    432 #define EXVexImmW { OP_EX_VexImmW, x_mode }
    433 #define XMVex { OP_XMM_Vex, 0 }
    434 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
    435 #define XMVexW { OP_XMM_VexW, 0 }
    436 #define XMVexI4 { OP_REG_VexI4, x_mode }
    437 #define PCLMUL { PCLMUL_Fixup, 0 }
    438 #define VZERO { VZERO_Fixup, 0 }
    439 #define VCMP { VCMP_Fixup, 0 }
    440 #define VPCMP { VPCMP_Fixup, 0 }
    441 
    442 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
    443 #define EXxEVexS { OP_Rounding, evex_sae_mode }
    444 
    445 #define XMask { OP_Mask, mask_mode }
    446 #define MaskG { OP_G, mask_mode }
    447 #define MaskE { OP_E, mask_mode }
    448 #define MaskBDE { OP_E, mask_bd_mode }
    449 #define MaskR { OP_R, mask_mode }
    450 #define MaskVex { OP_VEX, mask_mode }
    451 
    452 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
    453 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
    454 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
    455 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
    456 
    457 /* Used handle "rep" prefix for string instructions.  */
    458 #define Xbr { REP_Fixup, eSI_reg }
    459 #define Xvr { REP_Fixup, eSI_reg }
    460 #define Ybr { REP_Fixup, eDI_reg }
    461 #define Yvr { REP_Fixup, eDI_reg }
    462 #define Yzr { REP_Fixup, eDI_reg }
    463 #define indirDXr { REP_Fixup, indir_dx_reg }
    464 #define ALr { REP_Fixup, al_reg }
    465 #define eAXr { REP_Fixup, eAX_reg }
    466 
    467 /* Used handle HLE prefix for lockable instructions.  */
    468 #define Ebh1 { HLE_Fixup1, b_mode }
    469 #define Evh1 { HLE_Fixup1, v_mode }
    470 #define Ebh2 { HLE_Fixup2, b_mode }
    471 #define Evh2 { HLE_Fixup2, v_mode }
    472 #define Ebh3 { HLE_Fixup3, b_mode }
    473 #define Evh3 { HLE_Fixup3, v_mode }
    474 
    475 #define BND { BND_Fixup, 0 }
    476 
    477 #define cond_jump_flag { NULL, cond_jump_mode }
    478 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
    479 
    480 /* bits in sizeflag */
    481 #define SUFFIX_ALWAYS 4
    482 #define AFLAG 2
    483 #define DFLAG 1
    484 
    485 enum
    486 {
    487   /* byte operand */
    488   b_mode = 1,
    489   /* byte operand with operand swapped */
    490   b_swap_mode,
    491   /* byte operand, sign extend like 'T' suffix */
    492   b_T_mode,
    493   /* operand size depends on prefixes */
    494   v_mode,
    495   /* operand size depends on prefixes with operand swapped */
    496   v_swap_mode,
    497   /* word operand */
    498   w_mode,
    499   /* double word operand  */
    500   d_mode,
    501   /* double word operand with operand swapped */
    502   d_swap_mode,
    503   /* quad word operand */
    504   q_mode,
    505   /* quad word operand with operand swapped */
    506   q_swap_mode,
    507   /* ten-byte operand */
    508   t_mode,
    509   /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand.  In EVEX with
    510      broadcast enabled.  */
    511   x_mode,
    512   /* Similar to x_mode, but with different EVEX mem shifts.  */
    513   evex_x_gscat_mode,
    514   /* Similar to x_mode, but with disabled broadcast.  */
    515   evex_x_nobcst_mode,
    516   /* Similar to x_mode, but with operands swapped and disabled broadcast
    517      in EVEX.  */
    518   x_swap_mode,
    519   /* 16-byte XMM operand */
    520   xmm_mode,
    521   /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
    522      memory operand (depending on vector length).  Broadcast isn't
    523      allowed.  */
    524   xmmq_mode,
    525   /* Same as xmmq_mode, but broadcast is allowed.  */
    526   evex_half_bcst_xmmq_mode,
    527   /* XMM register or byte memory operand */
    528   xmm_mb_mode,
    529   /* XMM register or word memory operand */
    530   xmm_mw_mode,
    531   /* XMM register or double word memory operand */
    532   xmm_md_mode,
    533   /* XMM register or quad word memory operand */
    534   xmm_mq_mode,
    535   /* XMM register or double/quad word memory operand, depending on
    536      VEX.W.  */
    537   xmm_mdq_mode,
    538   /* 16-byte XMM, word, double word or quad word operand.  */
    539   xmmdw_mode,
    540   /* 16-byte XMM, double word, quad word operand or xmm word operand.  */
    541   xmmqd_mode,
    542   /* 32-byte YMM operand */
    543   ymm_mode,
    544   /* quad word, ymmword or zmmword memory operand.  */
    545   ymmq_mode,
    546   /* 32-byte YMM or 16-byte word operand */
    547   ymmxmm_mode,
    548   /* d_mode in 32bit, q_mode in 64bit mode.  */
    549   m_mode,
    550   /* pair of v_mode operands */
    551   a_mode,
    552   cond_jump_mode,
    553   loop_jcxz_mode,
    554   v_bnd_mode,
    555   /* operand size depends on REX prefixes.  */
    556   dq_mode,
    557   /* registers like dq_mode, memory like w_mode.  */
    558   dqw_mode,
    559   dqw_swap_mode,
    560   bnd_mode,
    561   /* 4- or 6-byte pointer operand */
    562   f_mode,
    563   const_1_mode,
    564   /* v_mode for indirect branch opcodes.  */
    565   indir_v_mode,
    566   /* v_mode for stack-related opcodes.  */
    567   stack_v_mode,
    568   /* non-quad operand size depends on prefixes */
    569   z_mode,
    570   /* 16-byte operand */
    571   o_mode,
    572   /* registers like dq_mode, memory like b_mode.  */
    573   dqb_mode,
    574   /* registers like d_mode, memory like b_mode.  */
    575   db_mode,
    576   /* registers like d_mode, memory like w_mode.  */
    577   dw_mode,
    578   /* registers like dq_mode, memory like d_mode.  */
    579   dqd_mode,
    580   /* normal vex mode */
    581   vex_mode,
    582   /* 128bit vex mode */
    583   vex128_mode,
    584   /* 256bit vex mode */
    585   vex256_mode,
    586   /* operand size depends on the VEX.W bit.  */
    587   vex_w_dq_mode,
    588 
    589   /* Similar to vex_w_dq_mode, with VSIB dword indices.  */
    590   vex_vsib_d_w_dq_mode,
    591   /* Similar to vex_vsib_d_w_dq_mode, with smaller memory.  */
    592   vex_vsib_d_w_d_mode,
    593   /* Similar to vex_w_dq_mode, with VSIB qword indices.  */
    594   vex_vsib_q_w_dq_mode,
    595   /* Similar to vex_vsib_q_w_dq_mode, with smaller memory.  */
    596   vex_vsib_q_w_d_mode,
    597 
    598   /* scalar, ignore vector length.  */
    599   scalar_mode,
    600   /* like d_mode, ignore vector length.  */
    601   d_scalar_mode,
    602   /* like d_swap_mode, ignore vector length.  */
    603   d_scalar_swap_mode,
    604   /* like q_mode, ignore vector length.  */
    605   q_scalar_mode,
    606   /* like q_swap_mode, ignore vector length.  */
    607   q_scalar_swap_mode,
    608   /* like vex_mode, ignore vector length.  */
    609   vex_scalar_mode,
    610   /* like vex_w_dq_mode, ignore vector length.  */
    611   vex_scalar_w_dq_mode,
    612 
    613   /* Static rounding.  */
    614   evex_rounding_mode,
    615   /* Supress all exceptions.  */
    616   evex_sae_mode,
    617 
    618   /* Mask register operand.  */
    619   mask_mode,
    620   /* Mask register operand.  */
    621   mask_bd_mode,
    622 
    623   es_reg,
    624   cs_reg,
    625   ss_reg,
    626   ds_reg,
    627   fs_reg,
    628   gs_reg,
    629 
    630   eAX_reg,
    631   eCX_reg,
    632   eDX_reg,
    633   eBX_reg,
    634   eSP_reg,
    635   eBP_reg,
    636   eSI_reg,
    637   eDI_reg,
    638 
    639   al_reg,
    640   cl_reg,
    641   dl_reg,
    642   bl_reg,
    643   ah_reg,
    644   ch_reg,
    645   dh_reg,
    646   bh_reg,
    647 
    648   ax_reg,
    649   cx_reg,
    650   dx_reg,
    651   bx_reg,
    652   sp_reg,
    653   bp_reg,
    654   si_reg,
    655   di_reg,
    656 
    657   rAX_reg,
    658   rCX_reg,
    659   rDX_reg,
    660   rBX_reg,
    661   rSP_reg,
    662   rBP_reg,
    663   rSI_reg,
    664   rDI_reg,
    665 
    666   z_mode_ax_reg,
    667   indir_dx_reg
    668 };
    669 
    670 enum
    671 {
    672   FLOATCODE = 1,
    673   USE_REG_TABLE,
    674   USE_MOD_TABLE,
    675   USE_RM_TABLE,
    676   USE_PREFIX_TABLE,
    677   USE_X86_64_TABLE,
    678   USE_3BYTE_TABLE,
    679   USE_XOP_8F_TABLE,
    680   USE_VEX_C4_TABLE,
    681   USE_VEX_C5_TABLE,
    682   USE_VEX_LEN_TABLE,
    683   USE_VEX_W_TABLE,
    684   USE_EVEX_TABLE
    685 };
    686 
    687 #define FLOAT			NULL, { { NULL, FLOATCODE } }, 0
    688 
    689 #define DIS386(T, I)		NULL, { { NULL, (T)}, { NULL,  (I) } }, 0
    690 #define DIS386_PREFIX(T, I, P)		NULL, { { NULL, (T)}, { NULL,  (I) } }, P
    691 #define REG_TABLE(I)		DIS386 (USE_REG_TABLE, (I))
    692 #define MOD_TABLE(I)		DIS386 (USE_MOD_TABLE, (I))
    693 #define RM_TABLE(I)		DIS386 (USE_RM_TABLE, (I))
    694 #define PREFIX_TABLE(I)		DIS386 (USE_PREFIX_TABLE, (I))
    695 #define X86_64_TABLE(I)		DIS386 (USE_X86_64_TABLE, (I))
    696 #define THREE_BYTE_TABLE(I)	DIS386 (USE_3BYTE_TABLE, (I))
    697 #define THREE_BYTE_TABLE_PREFIX(I, P)	DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
    698 #define XOP_8F_TABLE(I)		DIS386 (USE_XOP_8F_TABLE, (I))
    699 #define VEX_C4_TABLE(I)		DIS386 (USE_VEX_C4_TABLE, (I))
    700 #define VEX_C5_TABLE(I)		DIS386 (USE_VEX_C5_TABLE, (I))
    701 #define VEX_LEN_TABLE(I)	DIS386 (USE_VEX_LEN_TABLE, (I))
    702 #define VEX_W_TABLE(I)		DIS386 (USE_VEX_W_TABLE, (I))
    703 #define EVEX_TABLE(I)		DIS386 (USE_EVEX_TABLE, (I))
    704 
    705 enum
    706 {
    707   REG_80 = 0,
    708   REG_81,
    709   REG_82,
    710   REG_8F,
    711   REG_C0,
    712   REG_C1,
    713   REG_C6,
    714   REG_C7,
    715   REG_D0,
    716   REG_D1,
    717   REG_D2,
    718   REG_D3,
    719   REG_F6,
    720   REG_F7,
    721   REG_FE,
    722   REG_FF,
    723   REG_0F00,
    724   REG_0F01,
    725   REG_0F0D,
    726   REG_0F18,
    727   REG_0F71,
    728   REG_0F72,
    729   REG_0F73,
    730   REG_0FA6,
    731   REG_0FA7,
    732   REG_0FAE,
    733   REG_0FBA,
    734   REG_0FC7,
    735   REG_VEX_0F71,
    736   REG_VEX_0F72,
    737   REG_VEX_0F73,
    738   REG_VEX_0FAE,
    739   REG_VEX_0F38F3,
    740   REG_XOP_LWPCB,
    741   REG_XOP_LWP,
    742   REG_XOP_TBM_01,
    743   REG_XOP_TBM_02,
    744 
    745   REG_EVEX_0F71,
    746   REG_EVEX_0F72,
    747   REG_EVEX_0F73,
    748   REG_EVEX_0F38C6,
    749   REG_EVEX_0F38C7
    750 };
    751 
    752 enum
    753 {
    754   MOD_8D = 0,
    755   MOD_C6_REG_7,
    756   MOD_C7_REG_7,
    757   MOD_FF_REG_3,
    758   MOD_FF_REG_5,
    759   MOD_0F01_REG_0,
    760   MOD_0F01_REG_1,
    761   MOD_0F01_REG_2,
    762   MOD_0F01_REG_3,
    763   MOD_0F01_REG_5,
    764   MOD_0F01_REG_7,
    765   MOD_0F12_PREFIX_0,
    766   MOD_0F13,
    767   MOD_0F16_PREFIX_0,
    768   MOD_0F17,
    769   MOD_0F18_REG_0,
    770   MOD_0F18_REG_1,
    771   MOD_0F18_REG_2,
    772   MOD_0F18_REG_3,
    773   MOD_0F18_REG_4,
    774   MOD_0F18_REG_5,
    775   MOD_0F18_REG_6,
    776   MOD_0F18_REG_7,
    777   MOD_0F1A_PREFIX_0,
    778   MOD_0F1B_PREFIX_0,
    779   MOD_0F1B_PREFIX_1,
    780   MOD_0F24,
    781   MOD_0F26,
    782   MOD_0F2B_PREFIX_0,
    783   MOD_0F2B_PREFIX_1,
    784   MOD_0F2B_PREFIX_2,
    785   MOD_0F2B_PREFIX_3,
    786   MOD_0F51,
    787   MOD_0F71_REG_2,
    788   MOD_0F71_REG_4,
    789   MOD_0F71_REG_6,
    790   MOD_0F72_REG_2,
    791   MOD_0F72_REG_4,
    792   MOD_0F72_REG_6,
    793   MOD_0F73_REG_2,
    794   MOD_0F73_REG_3,
    795   MOD_0F73_REG_6,
    796   MOD_0F73_REG_7,
    797   MOD_0FAE_REG_0,
    798   MOD_0FAE_REG_1,
    799   MOD_0FAE_REG_2,
    800   MOD_0FAE_REG_3,
    801   MOD_0FAE_REG_4,
    802   MOD_0FAE_REG_5,
    803   MOD_0FAE_REG_6,
    804   MOD_0FAE_REG_7,
    805   MOD_0FB2,
    806   MOD_0FB4,
    807   MOD_0FB5,
    808   MOD_0FC3,
    809   MOD_0FC7_REG_3,
    810   MOD_0FC7_REG_4,
    811   MOD_0FC7_REG_5,
    812   MOD_0FC7_REG_6,
    813   MOD_0FC7_REG_7,
    814   MOD_0FD7,
    815   MOD_0FE7_PREFIX_2,
    816   MOD_0FF0_PREFIX_3,
    817   MOD_0F382A_PREFIX_2,
    818   MOD_62_32BIT,
    819   MOD_C4_32BIT,
    820   MOD_C5_32BIT,
    821   MOD_VEX_0F12_PREFIX_0,
    822   MOD_VEX_0F13,
    823   MOD_VEX_0F16_PREFIX_0,
    824   MOD_VEX_0F17,
    825   MOD_VEX_0F2B,
    826   MOD_VEX_W_0_0F41_P_0_LEN_1,
    827   MOD_VEX_W_1_0F41_P_0_LEN_1,
    828   MOD_VEX_W_0_0F41_P_2_LEN_1,
    829   MOD_VEX_W_1_0F41_P_2_LEN_1,
    830   MOD_VEX_W_0_0F42_P_0_LEN_1,
    831   MOD_VEX_W_1_0F42_P_0_LEN_1,
    832   MOD_VEX_W_0_0F42_P_2_LEN_1,
    833   MOD_VEX_W_1_0F42_P_2_LEN_1,
    834   MOD_VEX_W_0_0F44_P_0_LEN_1,
    835   MOD_VEX_W_1_0F44_P_0_LEN_1,
    836   MOD_VEX_W_0_0F44_P_2_LEN_1,
    837   MOD_VEX_W_1_0F44_P_2_LEN_1,
    838   MOD_VEX_W_0_0F45_P_0_LEN_1,
    839   MOD_VEX_W_1_0F45_P_0_LEN_1,
    840   MOD_VEX_W_0_0F45_P_2_LEN_1,
    841   MOD_VEX_W_1_0F45_P_2_LEN_1,
    842   MOD_VEX_W_0_0F46_P_0_LEN_1,
    843   MOD_VEX_W_1_0F46_P_0_LEN_1,
    844   MOD_VEX_W_0_0F46_P_2_LEN_1,
    845   MOD_VEX_W_1_0F46_P_2_LEN_1,
    846   MOD_VEX_W_0_0F47_P_0_LEN_1,
    847   MOD_VEX_W_1_0F47_P_0_LEN_1,
    848   MOD_VEX_W_0_0F47_P_2_LEN_1,
    849   MOD_VEX_W_1_0F47_P_2_LEN_1,
    850   MOD_VEX_W_0_0F4A_P_0_LEN_1,
    851   MOD_VEX_W_1_0F4A_P_0_LEN_1,
    852   MOD_VEX_W_0_0F4A_P_2_LEN_1,
    853   MOD_VEX_W_1_0F4A_P_2_LEN_1,
    854   MOD_VEX_W_0_0F4B_P_0_LEN_1,
    855   MOD_VEX_W_1_0F4B_P_0_LEN_1,
    856   MOD_VEX_W_0_0F4B_P_2_LEN_1,
    857   MOD_VEX_0F50,
    858   MOD_VEX_0F71_REG_2,
    859   MOD_VEX_0F71_REG_4,
    860   MOD_VEX_0F71_REG_6,
    861   MOD_VEX_0F72_REG_2,
    862   MOD_VEX_0F72_REG_4,
    863   MOD_VEX_0F72_REG_6,
    864   MOD_VEX_0F73_REG_2,
    865   MOD_VEX_0F73_REG_3,
    866   MOD_VEX_0F73_REG_6,
    867   MOD_VEX_0F73_REG_7,
    868   MOD_VEX_W_0_0F91_P_0_LEN_0,
    869   MOD_VEX_W_1_0F91_P_0_LEN_0,
    870   MOD_VEX_W_0_0F91_P_2_LEN_0,
    871   MOD_VEX_W_1_0F91_P_2_LEN_0,
    872   MOD_VEX_W_0_0F92_P_0_LEN_0,
    873   MOD_VEX_W_0_0F92_P_2_LEN_0,
    874   MOD_VEX_W_0_0F92_P_3_LEN_0,
    875   MOD_VEX_W_1_0F92_P_3_LEN_0,
    876   MOD_VEX_W_0_0F93_P_0_LEN_0,
    877   MOD_VEX_W_0_0F93_P_2_LEN_0,
    878   MOD_VEX_W_0_0F93_P_3_LEN_0,
    879   MOD_VEX_W_1_0F93_P_3_LEN_0,
    880   MOD_VEX_W_0_0F98_P_0_LEN_0,
    881   MOD_VEX_W_1_0F98_P_0_LEN_0,
    882   MOD_VEX_W_0_0F98_P_2_LEN_0,
    883   MOD_VEX_W_1_0F98_P_2_LEN_0,
    884   MOD_VEX_W_0_0F99_P_0_LEN_0,
    885   MOD_VEX_W_1_0F99_P_0_LEN_0,
    886   MOD_VEX_W_0_0F99_P_2_LEN_0,
    887   MOD_VEX_W_1_0F99_P_2_LEN_0,
    888   MOD_VEX_0FAE_REG_2,
    889   MOD_VEX_0FAE_REG_3,
    890   MOD_VEX_0FD7_PREFIX_2,
    891   MOD_VEX_0FE7_PREFIX_2,
    892   MOD_VEX_0FF0_PREFIX_3,
    893   MOD_VEX_0F381A_PREFIX_2,
    894   MOD_VEX_0F382A_PREFIX_2,
    895   MOD_VEX_0F382C_PREFIX_2,
    896   MOD_VEX_0F382D_PREFIX_2,
    897   MOD_VEX_0F382E_PREFIX_2,
    898   MOD_VEX_0F382F_PREFIX_2,
    899   MOD_VEX_0F385A_PREFIX_2,
    900   MOD_VEX_0F388C_PREFIX_2,
    901   MOD_VEX_0F388E_PREFIX_2,
    902   MOD_VEX_W_0_0F3A30_P_2_LEN_0,
    903   MOD_VEX_W_1_0F3A30_P_2_LEN_0,
    904   MOD_VEX_W_0_0F3A31_P_2_LEN_0,
    905   MOD_VEX_W_1_0F3A31_P_2_LEN_0,
    906   MOD_VEX_W_0_0F3A32_P_2_LEN_0,
    907   MOD_VEX_W_1_0F3A32_P_2_LEN_0,
    908   MOD_VEX_W_0_0F3A33_P_2_LEN_0,
    909   MOD_VEX_W_1_0F3A33_P_2_LEN_0,
    910 
    911   MOD_EVEX_0F10_PREFIX_1,
    912   MOD_EVEX_0F10_PREFIX_3,
    913   MOD_EVEX_0F11_PREFIX_1,
    914   MOD_EVEX_0F11_PREFIX_3,
    915   MOD_EVEX_0F12_PREFIX_0,
    916   MOD_EVEX_0F16_PREFIX_0,
    917   MOD_EVEX_0F38C6_REG_1,
    918   MOD_EVEX_0F38C6_REG_2,
    919   MOD_EVEX_0F38C6_REG_5,
    920   MOD_EVEX_0F38C6_REG_6,
    921   MOD_EVEX_0F38C7_REG_1,
    922   MOD_EVEX_0F38C7_REG_2,
    923   MOD_EVEX_0F38C7_REG_5,
    924   MOD_EVEX_0F38C7_REG_6
    925 };
    926 
    927 enum
    928 {
    929   RM_C6_REG_7 = 0,
    930   RM_C7_REG_7,
    931   RM_0F01_REG_0,
    932   RM_0F01_REG_1,
    933   RM_0F01_REG_2,
    934   RM_0F01_REG_3,
    935   RM_0F01_REG_5,
    936   RM_0F01_REG_7,
    937   RM_0FAE_REG_5,
    938   RM_0FAE_REG_6,
    939   RM_0FAE_REG_7
    940 };
    941 
    942 enum
    943 {
    944   PREFIX_90 = 0,
    945   PREFIX_0F10,
    946   PREFIX_0F11,
    947   PREFIX_0F12,
    948   PREFIX_0F16,
    949   PREFIX_0F1A,
    950   PREFIX_0F1B,
    951   PREFIX_0F2A,
    952   PREFIX_0F2B,
    953   PREFIX_0F2C,
    954   PREFIX_0F2D,
    955   PREFIX_0F2E,
    956   PREFIX_0F2F,
    957   PREFIX_0F51,
    958   PREFIX_0F52,
    959   PREFIX_0F53,
    960   PREFIX_0F58,
    961   PREFIX_0F59,
    962   PREFIX_0F5A,
    963   PREFIX_0F5B,
    964   PREFIX_0F5C,
    965   PREFIX_0F5D,
    966   PREFIX_0F5E,
    967   PREFIX_0F5F,
    968   PREFIX_0F60,
    969   PREFIX_0F61,
    970   PREFIX_0F62,
    971   PREFIX_0F6C,
    972   PREFIX_0F6D,
    973   PREFIX_0F6F,
    974   PREFIX_0F70,
    975   PREFIX_0F73_REG_3,
    976   PREFIX_0F73_REG_7,
    977   PREFIX_0F78,
    978   PREFIX_0F79,
    979   PREFIX_0F7C,
    980   PREFIX_0F7D,
    981   PREFIX_0F7E,
    982   PREFIX_0F7F,
    983   PREFIX_0FAE_REG_0,
    984   PREFIX_0FAE_REG_1,
    985   PREFIX_0FAE_REG_2,
    986   PREFIX_0FAE_REG_3,
    987   PREFIX_0FAE_REG_6,
    988   PREFIX_0FAE_REG_7,
    989   PREFIX_RM_0_0FAE_REG_7,
    990   PREFIX_0FB8,
    991   PREFIX_0FBC,
    992   PREFIX_0FBD,
    993   PREFIX_0FC2,
    994   PREFIX_MOD_0_0FC3,
    995   PREFIX_MOD_0_0FC7_REG_6,
    996   PREFIX_MOD_3_0FC7_REG_6,
    997   PREFIX_MOD_3_0FC7_REG_7,
    998   PREFIX_0FD0,
    999   PREFIX_0FD6,
   1000   PREFIX_0FE6,
   1001   PREFIX_0FE7,
   1002   PREFIX_0FF0,
   1003   PREFIX_0FF7,
   1004   PREFIX_0F3810,
   1005   PREFIX_0F3814,
   1006   PREFIX_0F3815,
   1007   PREFIX_0F3817,
   1008   PREFIX_0F3820,
   1009   PREFIX_0F3821,
   1010   PREFIX_0F3822,
   1011   PREFIX_0F3823,
   1012   PREFIX_0F3824,
   1013   PREFIX_0F3825,
   1014   PREFIX_0F3828,
   1015   PREFIX_0F3829,
   1016   PREFIX_0F382A,
   1017   PREFIX_0F382B,
   1018   PREFIX_0F3830,
   1019   PREFIX_0F3831,
   1020   PREFIX_0F3832,
   1021   PREFIX_0F3833,
   1022   PREFIX_0F3834,
   1023   PREFIX_0F3835,
   1024   PREFIX_0F3837,
   1025   PREFIX_0F3838,
   1026   PREFIX_0F3839,
   1027   PREFIX_0F383A,
   1028   PREFIX_0F383B,
   1029   PREFIX_0F383C,
   1030   PREFIX_0F383D,
   1031   PREFIX_0F383E,
   1032   PREFIX_0F383F,
   1033   PREFIX_0F3840,
   1034   PREFIX_0F3841,
   1035   PREFIX_0F3880,
   1036   PREFIX_0F3881,
   1037   PREFIX_0F3882,
   1038   PREFIX_0F38C8,
   1039   PREFIX_0F38C9,
   1040   PREFIX_0F38CA,
   1041   PREFIX_0F38CB,
   1042   PREFIX_0F38CC,
   1043   PREFIX_0F38CD,
   1044   PREFIX_0F38DB,
   1045   PREFIX_0F38DC,
   1046   PREFIX_0F38DD,
   1047   PREFIX_0F38DE,
   1048   PREFIX_0F38DF,
   1049   PREFIX_0F38F0,
   1050   PREFIX_0F38F1,
   1051   PREFIX_0F38F6,
   1052   PREFIX_0F3A08,
   1053   PREFIX_0F3A09,
   1054   PREFIX_0F3A0A,
   1055   PREFIX_0F3A0B,
   1056   PREFIX_0F3A0C,
   1057   PREFIX_0F3A0D,
   1058   PREFIX_0F3A0E,
   1059   PREFIX_0F3A14,
   1060   PREFIX_0F3A15,
   1061   PREFIX_0F3A16,
   1062   PREFIX_0F3A17,
   1063   PREFIX_0F3A20,
   1064   PREFIX_0F3A21,
   1065   PREFIX_0F3A22,
   1066   PREFIX_0F3A40,
   1067   PREFIX_0F3A41,
   1068   PREFIX_0F3A42,
   1069   PREFIX_0F3A44,
   1070   PREFIX_0F3A60,
   1071   PREFIX_0F3A61,
   1072   PREFIX_0F3A62,
   1073   PREFIX_0F3A63,
   1074   PREFIX_0F3ACC,
   1075   PREFIX_0F3ADF,
   1076   PREFIX_VEX_0F10,
   1077   PREFIX_VEX_0F11,
   1078   PREFIX_VEX_0F12,
   1079   PREFIX_VEX_0F16,
   1080   PREFIX_VEX_0F2A,
   1081   PREFIX_VEX_0F2C,
   1082   PREFIX_VEX_0F2D,
   1083   PREFIX_VEX_0F2E,
   1084   PREFIX_VEX_0F2F,
   1085   PREFIX_VEX_0F41,
   1086   PREFIX_VEX_0F42,
   1087   PREFIX_VEX_0F44,
   1088   PREFIX_VEX_0F45,
   1089   PREFIX_VEX_0F46,
   1090   PREFIX_VEX_0F47,
   1091   PREFIX_VEX_0F4A,
   1092   PREFIX_VEX_0F4B,
   1093   PREFIX_VEX_0F51,
   1094   PREFIX_VEX_0F52,
   1095   PREFIX_VEX_0F53,
   1096   PREFIX_VEX_0F58,
   1097   PREFIX_VEX_0F59,
   1098   PREFIX_VEX_0F5A,
   1099   PREFIX_VEX_0F5B,
   1100   PREFIX_VEX_0F5C,
   1101   PREFIX_VEX_0F5D,
   1102   PREFIX_VEX_0F5E,
   1103   PREFIX_VEX_0F5F,
   1104   PREFIX_VEX_0F60,
   1105   PREFIX_VEX_0F61,
   1106   PREFIX_VEX_0F62,
   1107   PREFIX_VEX_0F63,
   1108   PREFIX_VEX_0F64,
   1109   PREFIX_VEX_0F65,
   1110   PREFIX_VEX_0F66,
   1111   PREFIX_VEX_0F67,
   1112   PREFIX_VEX_0F68,
   1113   PREFIX_VEX_0F69,
   1114   PREFIX_VEX_0F6A,
   1115   PREFIX_VEX_0F6B,
   1116   PREFIX_VEX_0F6C,
   1117   PREFIX_VEX_0F6D,
   1118   PREFIX_VEX_0F6E,
   1119   PREFIX_VEX_0F6F,
   1120   PREFIX_VEX_0F70,
   1121   PREFIX_VEX_0F71_REG_2,
   1122   PREFIX_VEX_0F71_REG_4,
   1123   PREFIX_VEX_0F71_REG_6,
   1124   PREFIX_VEX_0F72_REG_2,
   1125   PREFIX_VEX_0F72_REG_4,
   1126   PREFIX_VEX_0F72_REG_6,
   1127   PREFIX_VEX_0F73_REG_2,
   1128   PREFIX_VEX_0F73_REG_3,
   1129   PREFIX_VEX_0F73_REG_6,
   1130   PREFIX_VEX_0F73_REG_7,
   1131   PREFIX_VEX_0F74,
   1132   PREFIX_VEX_0F75,
   1133   PREFIX_VEX_0F76,
   1134   PREFIX_VEX_0F77,
   1135   PREFIX_VEX_0F7C,
   1136   PREFIX_VEX_0F7D,
   1137   PREFIX_VEX_0F7E,
   1138   PREFIX_VEX_0F7F,
   1139   PREFIX_VEX_0F90,
   1140   PREFIX_VEX_0F91,
   1141   PREFIX_VEX_0F92,
   1142   PREFIX_VEX_0F93,
   1143   PREFIX_VEX_0F98,
   1144   PREFIX_VEX_0F99,
   1145   PREFIX_VEX_0FC2,
   1146   PREFIX_VEX_0FC4,
   1147   PREFIX_VEX_0FC5,
   1148   PREFIX_VEX_0FD0,
   1149   PREFIX_VEX_0FD1,
   1150   PREFIX_VEX_0FD2,
   1151   PREFIX_VEX_0FD3,
   1152   PREFIX_VEX_0FD4,
   1153   PREFIX_VEX_0FD5,
   1154   PREFIX_VEX_0FD6,
   1155   PREFIX_VEX_0FD7,
   1156   PREFIX_VEX_0FD8,
   1157   PREFIX_VEX_0FD9,
   1158   PREFIX_VEX_0FDA,
   1159   PREFIX_VEX_0FDB,
   1160   PREFIX_VEX_0FDC,
   1161   PREFIX_VEX_0FDD,
   1162   PREFIX_VEX_0FDE,
   1163   PREFIX_VEX_0FDF,
   1164   PREFIX_VEX_0FE0,
   1165   PREFIX_VEX_0FE1,
   1166   PREFIX_VEX_0FE2,
   1167   PREFIX_VEX_0FE3,
   1168   PREFIX_VEX_0FE4,
   1169   PREFIX_VEX_0FE5,
   1170   PREFIX_VEX_0FE6,
   1171   PREFIX_VEX_0FE7,
   1172   PREFIX_VEX_0FE8,
   1173   PREFIX_VEX_0FE9,
   1174   PREFIX_VEX_0FEA,
   1175   PREFIX_VEX_0FEB,
   1176   PREFIX_VEX_0FEC,
   1177   PREFIX_VEX_0FED,
   1178   PREFIX_VEX_0FEE,
   1179   PREFIX_VEX_0FEF,
   1180   PREFIX_VEX_0FF0,
   1181   PREFIX_VEX_0FF1,
   1182   PREFIX_VEX_0FF2,
   1183   PREFIX_VEX_0FF3,
   1184   PREFIX_VEX_0FF4,
   1185   PREFIX_VEX_0FF5,
   1186   PREFIX_VEX_0FF6,
   1187   PREFIX_VEX_0FF7,
   1188   PREFIX_VEX_0FF8,
   1189   PREFIX_VEX_0FF9,
   1190   PREFIX_VEX_0FFA,
   1191   PREFIX_VEX_0FFB,
   1192   PREFIX_VEX_0FFC,
   1193   PREFIX_VEX_0FFD,
   1194   PREFIX_VEX_0FFE,
   1195   PREFIX_VEX_0F3800,
   1196   PREFIX_VEX_0F3801,
   1197   PREFIX_VEX_0F3802,
   1198   PREFIX_VEX_0F3803,
   1199   PREFIX_VEX_0F3804,
   1200   PREFIX_VEX_0F3805,
   1201   PREFIX_VEX_0F3806,
   1202   PREFIX_VEX_0F3807,
   1203   PREFIX_VEX_0F3808,
   1204   PREFIX_VEX_0F3809,
   1205   PREFIX_VEX_0F380A,
   1206   PREFIX_VEX_0F380B,
   1207   PREFIX_VEX_0F380C,
   1208   PREFIX_VEX_0F380D,
   1209   PREFIX_VEX_0F380E,
   1210   PREFIX_VEX_0F380F,
   1211   PREFIX_VEX_0F3813,
   1212   PREFIX_VEX_0F3816,
   1213   PREFIX_VEX_0F3817,
   1214   PREFIX_VEX_0F3818,
   1215   PREFIX_VEX_0F3819,
   1216   PREFIX_VEX_0F381A,
   1217   PREFIX_VEX_0F381C,
   1218   PREFIX_VEX_0F381D,
   1219   PREFIX_VEX_0F381E,
   1220   PREFIX_VEX_0F3820,
   1221   PREFIX_VEX_0F3821,
   1222   PREFIX_VEX_0F3822,
   1223   PREFIX_VEX_0F3823,
   1224   PREFIX_VEX_0F3824,
   1225   PREFIX_VEX_0F3825,
   1226   PREFIX_VEX_0F3828,
   1227   PREFIX_VEX_0F3829,
   1228   PREFIX_VEX_0F382A,
   1229   PREFIX_VEX_0F382B,
   1230   PREFIX_VEX_0F382C,
   1231   PREFIX_VEX_0F382D,
   1232   PREFIX_VEX_0F382E,
   1233   PREFIX_VEX_0F382F,
   1234   PREFIX_VEX_0F3830,
   1235   PREFIX_VEX_0F3831,
   1236   PREFIX_VEX_0F3832,
   1237   PREFIX_VEX_0F3833,
   1238   PREFIX_VEX_0F3834,
   1239   PREFIX_VEX_0F3835,
   1240   PREFIX_VEX_0F3836,
   1241   PREFIX_VEX_0F3837,
   1242   PREFIX_VEX_0F3838,
   1243   PREFIX_VEX_0F3839,
   1244   PREFIX_VEX_0F383A,
   1245   PREFIX_VEX_0F383B,
   1246   PREFIX_VEX_0F383C,
   1247   PREFIX_VEX_0F383D,
   1248   PREFIX_VEX_0F383E,
   1249   PREFIX_VEX_0F383F,
   1250   PREFIX_VEX_0F3840,
   1251   PREFIX_VEX_0F3841,
   1252   PREFIX_VEX_0F3845,
   1253   PREFIX_VEX_0F3846,
   1254   PREFIX_VEX_0F3847,
   1255   PREFIX_VEX_0F3858,
   1256   PREFIX_VEX_0F3859,
   1257   PREFIX_VEX_0F385A,
   1258   PREFIX_VEX_0F3878,
   1259   PREFIX_VEX_0F3879,
   1260   PREFIX_VEX_0F388C,
   1261   PREFIX_VEX_0F388E,
   1262   PREFIX_VEX_0F3890,
   1263   PREFIX_VEX_0F3891,
   1264   PREFIX_VEX_0F3892,
   1265   PREFIX_VEX_0F3893,
   1266   PREFIX_VEX_0F3896,
   1267   PREFIX_VEX_0F3897,
   1268   PREFIX_VEX_0F3898,
   1269   PREFIX_VEX_0F3899,
   1270   PREFIX_VEX_0F389A,
   1271   PREFIX_VEX_0F389B,
   1272   PREFIX_VEX_0F389C,
   1273   PREFIX_VEX_0F389D,
   1274   PREFIX_VEX_0F389E,
   1275   PREFIX_VEX_0F389F,
   1276   PREFIX_VEX_0F38A6,
   1277   PREFIX_VEX_0F38A7,
   1278   PREFIX_VEX_0F38A8,
   1279   PREFIX_VEX_0F38A9,
   1280   PREFIX_VEX_0F38AA,
   1281   PREFIX_VEX_0F38AB,
   1282   PREFIX_VEX_0F38AC,
   1283   PREFIX_VEX_0F38AD,
   1284   PREFIX_VEX_0F38AE,
   1285   PREFIX_VEX_0F38AF,
   1286   PREFIX_VEX_0F38B6,
   1287   PREFIX_VEX_0F38B7,
   1288   PREFIX_VEX_0F38B8,
   1289   PREFIX_VEX_0F38B9,
   1290   PREFIX_VEX_0F38BA,
   1291   PREFIX_VEX_0F38BB,
   1292   PREFIX_VEX_0F38BC,
   1293   PREFIX_VEX_0F38BD,
   1294   PREFIX_VEX_0F38BE,
   1295   PREFIX_VEX_0F38BF,
   1296   PREFIX_VEX_0F38DB,
   1297   PREFIX_VEX_0F38DC,
   1298   PREFIX_VEX_0F38DD,
   1299   PREFIX_VEX_0F38DE,
   1300   PREFIX_VEX_0F38DF,
   1301   PREFIX_VEX_0F38F2,
   1302   PREFIX_VEX_0F38F3_REG_1,
   1303   PREFIX_VEX_0F38F3_REG_2,
   1304   PREFIX_VEX_0F38F3_REG_3,
   1305   PREFIX_VEX_0F38F5,
   1306   PREFIX_VEX_0F38F6,
   1307   PREFIX_VEX_0F38F7,
   1308   PREFIX_VEX_0F3A00,
   1309   PREFIX_VEX_0F3A01,
   1310   PREFIX_VEX_0F3A02,
   1311   PREFIX_VEX_0F3A04,
   1312   PREFIX_VEX_0F3A05,
   1313   PREFIX_VEX_0F3A06,
   1314   PREFIX_VEX_0F3A08,
   1315   PREFIX_VEX_0F3A09,
   1316   PREFIX_VEX_0F3A0A,
   1317   PREFIX_VEX_0F3A0B,
   1318   PREFIX_VEX_0F3A0C,
   1319   PREFIX_VEX_0F3A0D,
   1320   PREFIX_VEX_0F3A0E,
   1321   PREFIX_VEX_0F3A0F,
   1322   PREFIX_VEX_0F3A14,
   1323   PREFIX_VEX_0F3A15,
   1324   PREFIX_VEX_0F3A16,
   1325   PREFIX_VEX_0F3A17,
   1326   PREFIX_VEX_0F3A18,
   1327   PREFIX_VEX_0F3A19,
   1328   PREFIX_VEX_0F3A1D,
   1329   PREFIX_VEX_0F3A20,
   1330   PREFIX_VEX_0F3A21,
   1331   PREFIX_VEX_0F3A22,
   1332   PREFIX_VEX_0F3A30,
   1333   PREFIX_VEX_0F3A31,
   1334   PREFIX_VEX_0F3A32,
   1335   PREFIX_VEX_0F3A33,
   1336   PREFIX_VEX_0F3A38,
   1337   PREFIX_VEX_0F3A39,
   1338   PREFIX_VEX_0F3A40,
   1339   PREFIX_VEX_0F3A41,
   1340   PREFIX_VEX_0F3A42,
   1341   PREFIX_VEX_0F3A44,
   1342   PREFIX_VEX_0F3A46,
   1343   PREFIX_VEX_0F3A48,
   1344   PREFIX_VEX_0F3A49,
   1345   PREFIX_VEX_0F3A4A,
   1346   PREFIX_VEX_0F3A4B,
   1347   PREFIX_VEX_0F3A4C,
   1348   PREFIX_VEX_0F3A5C,
   1349   PREFIX_VEX_0F3A5D,
   1350   PREFIX_VEX_0F3A5E,
   1351   PREFIX_VEX_0F3A5F,
   1352   PREFIX_VEX_0F3A60,
   1353   PREFIX_VEX_0F3A61,
   1354   PREFIX_VEX_0F3A62,
   1355   PREFIX_VEX_0F3A63,
   1356   PREFIX_VEX_0F3A68,
   1357   PREFIX_VEX_0F3A69,
   1358   PREFIX_VEX_0F3A6A,
   1359   PREFIX_VEX_0F3A6B,
   1360   PREFIX_VEX_0F3A6C,
   1361   PREFIX_VEX_0F3A6D,
   1362   PREFIX_VEX_0F3A6E,
   1363   PREFIX_VEX_0F3A6F,
   1364   PREFIX_VEX_0F3A78,
   1365   PREFIX_VEX_0F3A79,
   1366   PREFIX_VEX_0F3A7A,
   1367   PREFIX_VEX_0F3A7B,
   1368   PREFIX_VEX_0F3A7C,
   1369   PREFIX_VEX_0F3A7D,
   1370   PREFIX_VEX_0F3A7E,
   1371   PREFIX_VEX_0F3A7F,
   1372   PREFIX_VEX_0F3ADF,
   1373   PREFIX_VEX_0F3AF0,
   1374 
   1375   PREFIX_EVEX_0F10,
   1376   PREFIX_EVEX_0F11,
   1377   PREFIX_EVEX_0F12,
   1378   PREFIX_EVEX_0F13,
   1379   PREFIX_EVEX_0F14,
   1380   PREFIX_EVEX_0F15,
   1381   PREFIX_EVEX_0F16,
   1382   PREFIX_EVEX_0F17,
   1383   PREFIX_EVEX_0F28,
   1384   PREFIX_EVEX_0F29,
   1385   PREFIX_EVEX_0F2A,
   1386   PREFIX_EVEX_0F2B,
   1387   PREFIX_EVEX_0F2C,
   1388   PREFIX_EVEX_0F2D,
   1389   PREFIX_EVEX_0F2E,
   1390   PREFIX_EVEX_0F2F,
   1391   PREFIX_EVEX_0F51,
   1392   PREFIX_EVEX_0F54,
   1393   PREFIX_EVEX_0F55,
   1394   PREFIX_EVEX_0F56,
   1395   PREFIX_EVEX_0F57,
   1396   PREFIX_EVEX_0F58,
   1397   PREFIX_EVEX_0F59,
   1398   PREFIX_EVEX_0F5A,
   1399   PREFIX_EVEX_0F5B,
   1400   PREFIX_EVEX_0F5C,
   1401   PREFIX_EVEX_0F5D,
   1402   PREFIX_EVEX_0F5E,
   1403   PREFIX_EVEX_0F5F,
   1404   PREFIX_EVEX_0F60,
   1405   PREFIX_EVEX_0F61,
   1406   PREFIX_EVEX_0F62,
   1407   PREFIX_EVEX_0F63,
   1408   PREFIX_EVEX_0F64,
   1409   PREFIX_EVEX_0F65,
   1410   PREFIX_EVEX_0F66,
   1411   PREFIX_EVEX_0F67,
   1412   PREFIX_EVEX_0F68,
   1413   PREFIX_EVEX_0F69,
   1414   PREFIX_EVEX_0F6A,
   1415   PREFIX_EVEX_0F6B,
   1416   PREFIX_EVEX_0F6C,
   1417   PREFIX_EVEX_0F6D,
   1418   PREFIX_EVEX_0F6E,
   1419   PREFIX_EVEX_0F6F,
   1420   PREFIX_EVEX_0F70,
   1421   PREFIX_EVEX_0F71_REG_2,
   1422   PREFIX_EVEX_0F71_REG_4,
   1423   PREFIX_EVEX_0F71_REG_6,
   1424   PREFIX_EVEX_0F72_REG_0,
   1425   PREFIX_EVEX_0F72_REG_1,
   1426   PREFIX_EVEX_0F72_REG_2,
   1427   PREFIX_EVEX_0F72_REG_4,
   1428   PREFIX_EVEX_0F72_REG_6,
   1429   PREFIX_EVEX_0F73_REG_2,
   1430   PREFIX_EVEX_0F73_REG_3,
   1431   PREFIX_EVEX_0F73_REG_6,
   1432   PREFIX_EVEX_0F73_REG_7,
   1433   PREFIX_EVEX_0F74,
   1434   PREFIX_EVEX_0F75,
   1435   PREFIX_EVEX_0F76,
   1436   PREFIX_EVEX_0F78,
   1437   PREFIX_EVEX_0F79,
   1438   PREFIX_EVEX_0F7A,
   1439   PREFIX_EVEX_0F7B,
   1440   PREFIX_EVEX_0F7E,
   1441   PREFIX_EVEX_0F7F,
   1442   PREFIX_EVEX_0FC2,
   1443   PREFIX_EVEX_0FC4,
   1444   PREFIX_EVEX_0FC5,
   1445   PREFIX_EVEX_0FC6,
   1446   PREFIX_EVEX_0FD1,
   1447   PREFIX_EVEX_0FD2,
   1448   PREFIX_EVEX_0FD3,
   1449   PREFIX_EVEX_0FD4,
   1450   PREFIX_EVEX_0FD5,
   1451   PREFIX_EVEX_0FD6,
   1452   PREFIX_EVEX_0FD8,
   1453   PREFIX_EVEX_0FD9,
   1454   PREFIX_EVEX_0FDA,
   1455   PREFIX_EVEX_0FDB,
   1456   PREFIX_EVEX_0FDC,
   1457   PREFIX_EVEX_0FDD,
   1458   PREFIX_EVEX_0FDE,
   1459   PREFIX_EVEX_0FDF,
   1460   PREFIX_EVEX_0FE0,
   1461   PREFIX_EVEX_0FE1,
   1462   PREFIX_EVEX_0FE2,
   1463   PREFIX_EVEX_0FE3,
   1464   PREFIX_EVEX_0FE4,
   1465   PREFIX_EVEX_0FE5,
   1466   PREFIX_EVEX_0FE6,
   1467   PREFIX_EVEX_0FE7,
   1468   PREFIX_EVEX_0FE8,
   1469   PREFIX_EVEX_0FE9,
   1470   PREFIX_EVEX_0FEA,
   1471   PREFIX_EVEX_0FEB,
   1472   PREFIX_EVEX_0FEC,
   1473   PREFIX_EVEX_0FED,
   1474   PREFIX_EVEX_0FEE,
   1475   PREFIX_EVEX_0FEF,
   1476   PREFIX_EVEX_0FF1,
   1477   PREFIX_EVEX_0FF2,
   1478   PREFIX_EVEX_0FF3,
   1479   PREFIX_EVEX_0FF4,
   1480   PREFIX_EVEX_0FF5,
   1481   PREFIX_EVEX_0FF6,
   1482   PREFIX_EVEX_0FF8,
   1483   PREFIX_EVEX_0FF9,
   1484   PREFIX_EVEX_0FFA,
   1485   PREFIX_EVEX_0FFB,
   1486   PREFIX_EVEX_0FFC,
   1487   PREFIX_EVEX_0FFD,
   1488   PREFIX_EVEX_0FFE,
   1489   PREFIX_EVEX_0F3800,
   1490   PREFIX_EVEX_0F3804,
   1491   PREFIX_EVEX_0F380B,
   1492   PREFIX_EVEX_0F380C,
   1493   PREFIX_EVEX_0F380D,
   1494   PREFIX_EVEX_0F3810,
   1495   PREFIX_EVEX_0F3811,
   1496   PREFIX_EVEX_0F3812,
   1497   PREFIX_EVEX_0F3813,
   1498   PREFIX_EVEX_0F3814,
   1499   PREFIX_EVEX_0F3815,
   1500   PREFIX_EVEX_0F3816,
   1501   PREFIX_EVEX_0F3818,
   1502   PREFIX_EVEX_0F3819,
   1503   PREFIX_EVEX_0F381A,
   1504   PREFIX_EVEX_0F381B,
   1505   PREFIX_EVEX_0F381C,
   1506   PREFIX_EVEX_0F381D,
   1507   PREFIX_EVEX_0F381E,
   1508   PREFIX_EVEX_0F381F,
   1509   PREFIX_EVEX_0F3820,
   1510   PREFIX_EVEX_0F3821,
   1511   PREFIX_EVEX_0F3822,
   1512   PREFIX_EVEX_0F3823,
   1513   PREFIX_EVEX_0F3824,
   1514   PREFIX_EVEX_0F3825,
   1515   PREFIX_EVEX_0F3826,
   1516   PREFIX_EVEX_0F3827,
   1517   PREFIX_EVEX_0F3828,
   1518   PREFIX_EVEX_0F3829,
   1519   PREFIX_EVEX_0F382A,
   1520   PREFIX_EVEX_0F382B,
   1521   PREFIX_EVEX_0F382C,
   1522   PREFIX_EVEX_0F382D,
   1523   PREFIX_EVEX_0F3830,
   1524   PREFIX_EVEX_0F3831,
   1525   PREFIX_EVEX_0F3832,
   1526   PREFIX_EVEX_0F3833,
   1527   PREFIX_EVEX_0F3834,
   1528   PREFIX_EVEX_0F3835,
   1529   PREFIX_EVEX_0F3836,
   1530   PREFIX_EVEX_0F3837,
   1531   PREFIX_EVEX_0F3838,
   1532   PREFIX_EVEX_0F3839,
   1533   PREFIX_EVEX_0F383A,
   1534   PREFIX_EVEX_0F383B,
   1535   PREFIX_EVEX_0F383C,
   1536   PREFIX_EVEX_0F383D,
   1537   PREFIX_EVEX_0F383E,
   1538   PREFIX_EVEX_0F383F,
   1539   PREFIX_EVEX_0F3840,
   1540   PREFIX_EVEX_0F3842,
   1541   PREFIX_EVEX_0F3843,
   1542   PREFIX_EVEX_0F3844,
   1543   PREFIX_EVEX_0F3845,
   1544   PREFIX_EVEX_0F3846,
   1545   PREFIX_EVEX_0F3847,
   1546   PREFIX_EVEX_0F384C,
   1547   PREFIX_EVEX_0F384D,
   1548   PREFIX_EVEX_0F384E,
   1549   PREFIX_EVEX_0F384F,
   1550   PREFIX_EVEX_0F3858,
   1551   PREFIX_EVEX_0F3859,
   1552   PREFIX_EVEX_0F385A,
   1553   PREFIX_EVEX_0F385B,
   1554   PREFIX_EVEX_0F3864,
   1555   PREFIX_EVEX_0F3865,
   1556   PREFIX_EVEX_0F3866,
   1557   PREFIX_EVEX_0F3875,
   1558   PREFIX_EVEX_0F3876,
   1559   PREFIX_EVEX_0F3877,
   1560   PREFIX_EVEX_0F3878,
   1561   PREFIX_EVEX_0F3879,
   1562   PREFIX_EVEX_0F387A,
   1563   PREFIX_EVEX_0F387B,
   1564   PREFIX_EVEX_0F387C,
   1565   PREFIX_EVEX_0F387D,
   1566   PREFIX_EVEX_0F387E,
   1567   PREFIX_EVEX_0F387F,
   1568   PREFIX_EVEX_0F3883,
   1569   PREFIX_EVEX_0F3888,
   1570   PREFIX_EVEX_0F3889,
   1571   PREFIX_EVEX_0F388A,
   1572   PREFIX_EVEX_0F388B,
   1573   PREFIX_EVEX_0F388D,
   1574   PREFIX_EVEX_0F3890,
   1575   PREFIX_EVEX_0F3891,
   1576   PREFIX_EVEX_0F3892,
   1577   PREFIX_EVEX_0F3893,
   1578   PREFIX_EVEX_0F3896,
   1579   PREFIX_EVEX_0F3897,
   1580   PREFIX_EVEX_0F3898,
   1581   PREFIX_EVEX_0F3899,
   1582   PREFIX_EVEX_0F389A,
   1583   PREFIX_EVEX_0F389B,
   1584   PREFIX_EVEX_0F389C,
   1585   PREFIX_EVEX_0F389D,
   1586   PREFIX_EVEX_0F389E,
   1587   PREFIX_EVEX_0F389F,
   1588   PREFIX_EVEX_0F38A0,
   1589   PREFIX_EVEX_0F38A1,
   1590   PREFIX_EVEX_0F38A2,
   1591   PREFIX_EVEX_0F38A3,
   1592   PREFIX_EVEX_0F38A6,
   1593   PREFIX_EVEX_0F38A7,
   1594   PREFIX_EVEX_0F38A8,
   1595   PREFIX_EVEX_0F38A9,
   1596   PREFIX_EVEX_0F38AA,
   1597   PREFIX_EVEX_0F38AB,
   1598   PREFIX_EVEX_0F38AC,
   1599   PREFIX_EVEX_0F38AD,
   1600   PREFIX_EVEX_0F38AE,
   1601   PREFIX_EVEX_0F38AF,
   1602   PREFIX_EVEX_0F38B4,
   1603   PREFIX_EVEX_0F38B5,
   1604   PREFIX_EVEX_0F38B6,
   1605   PREFIX_EVEX_0F38B7,
   1606   PREFIX_EVEX_0F38B8,
   1607   PREFIX_EVEX_0F38B9,
   1608   PREFIX_EVEX_0F38BA,
   1609   PREFIX_EVEX_0F38BB,
   1610   PREFIX_EVEX_0F38BC,
   1611   PREFIX_EVEX_0F38BD,
   1612   PREFIX_EVEX_0F38BE,
   1613   PREFIX_EVEX_0F38BF,
   1614   PREFIX_EVEX_0F38C4,
   1615   PREFIX_EVEX_0F38C6_REG_1,
   1616   PREFIX_EVEX_0F38C6_REG_2,
   1617   PREFIX_EVEX_0F38C6_REG_5,
   1618   PREFIX_EVEX_0F38C6_REG_6,
   1619   PREFIX_EVEX_0F38C7_REG_1,
   1620   PREFIX_EVEX_0F38C7_REG_2,
   1621   PREFIX_EVEX_0F38C7_REG_5,
   1622   PREFIX_EVEX_0F38C7_REG_6,
   1623   PREFIX_EVEX_0F38C8,
   1624   PREFIX_EVEX_0F38CA,
   1625   PREFIX_EVEX_0F38CB,
   1626   PREFIX_EVEX_0F38CC,
   1627   PREFIX_EVEX_0F38CD,
   1628 
   1629   PREFIX_EVEX_0F3A00,
   1630   PREFIX_EVEX_0F3A01,
   1631   PREFIX_EVEX_0F3A03,
   1632   PREFIX_EVEX_0F3A04,
   1633   PREFIX_EVEX_0F3A05,
   1634   PREFIX_EVEX_0F3A08,
   1635   PREFIX_EVEX_0F3A09,
   1636   PREFIX_EVEX_0F3A0A,
   1637   PREFIX_EVEX_0F3A0B,
   1638   PREFIX_EVEX_0F3A0F,
   1639   PREFIX_EVEX_0F3A14,
   1640   PREFIX_EVEX_0F3A15,
   1641   PREFIX_EVEX_0F3A16,
   1642   PREFIX_EVEX_0F3A17,
   1643   PREFIX_EVEX_0F3A18,
   1644   PREFIX_EVEX_0F3A19,
   1645   PREFIX_EVEX_0F3A1A,
   1646   PREFIX_EVEX_0F3A1B,
   1647   PREFIX_EVEX_0F3A1D,
   1648   PREFIX_EVEX_0F3A1E,
   1649   PREFIX_EVEX_0F3A1F,
   1650   PREFIX_EVEX_0F3A20,
   1651   PREFIX_EVEX_0F3A21,
   1652   PREFIX_EVEX_0F3A22,
   1653   PREFIX_EVEX_0F3A23,
   1654   PREFIX_EVEX_0F3A25,
   1655   PREFIX_EVEX_0F3A26,
   1656   PREFIX_EVEX_0F3A27,
   1657   PREFIX_EVEX_0F3A38,
   1658   PREFIX_EVEX_0F3A39,
   1659   PREFIX_EVEX_0F3A3A,
   1660   PREFIX_EVEX_0F3A3B,
   1661   PREFIX_EVEX_0F3A3E,
   1662   PREFIX_EVEX_0F3A3F,
   1663   PREFIX_EVEX_0F3A42,
   1664   PREFIX_EVEX_0F3A43,
   1665   PREFIX_EVEX_0F3A50,
   1666   PREFIX_EVEX_0F3A51,
   1667   PREFIX_EVEX_0F3A54,
   1668   PREFIX_EVEX_0F3A55,
   1669   PREFIX_EVEX_0F3A56,
   1670   PREFIX_EVEX_0F3A57,
   1671   PREFIX_EVEX_0F3A66,
   1672   PREFIX_EVEX_0F3A67
   1673 };
   1674 
   1675 enum
   1676 {
   1677   X86_64_06 = 0,
   1678   X86_64_07,
   1679   X86_64_0D,
   1680   X86_64_16,
   1681   X86_64_17,
   1682   X86_64_1E,
   1683   X86_64_1F,
   1684   X86_64_27,
   1685   X86_64_2F,
   1686   X86_64_37,
   1687   X86_64_3F,
   1688   X86_64_60,
   1689   X86_64_61,
   1690   X86_64_62,
   1691   X86_64_63,
   1692   X86_64_6D,
   1693   X86_64_6F,
   1694   X86_64_9A,
   1695   X86_64_C4,
   1696   X86_64_C5,
   1697   X86_64_CE,
   1698   X86_64_D4,
   1699   X86_64_D5,
   1700   X86_64_E8,
   1701   X86_64_E9,
   1702   X86_64_EA,
   1703   X86_64_0F01_REG_0,
   1704   X86_64_0F01_REG_1,
   1705   X86_64_0F01_REG_2,
   1706   X86_64_0F01_REG_3
   1707 };
   1708 
   1709 enum
   1710 {
   1711   THREE_BYTE_0F38 = 0,
   1712   THREE_BYTE_0F3A,
   1713   THREE_BYTE_0F7A
   1714 };
   1715 
   1716 enum
   1717 {
   1718   XOP_08 = 0,
   1719   XOP_09,
   1720   XOP_0A
   1721 };
   1722 
   1723 enum
   1724 {
   1725   VEX_0F = 0,
   1726   VEX_0F38,
   1727   VEX_0F3A
   1728 };
   1729 
   1730 enum
   1731 {
   1732   EVEX_0F = 0,
   1733   EVEX_0F38,
   1734   EVEX_0F3A
   1735 };
   1736 
   1737 enum
   1738 {
   1739   VEX_LEN_0F10_P_1 = 0,
   1740   VEX_LEN_0F10_P_3,
   1741   VEX_LEN_0F11_P_1,
   1742   VEX_LEN_0F11_P_3,
   1743   VEX_LEN_0F12_P_0_M_0,
   1744   VEX_LEN_0F12_P_0_M_1,
   1745   VEX_LEN_0F12_P_2,
   1746   VEX_LEN_0F13_M_0,
   1747   VEX_LEN_0F16_P_0_M_0,
   1748   VEX_LEN_0F16_P_0_M_1,
   1749   VEX_LEN_0F16_P_2,
   1750   VEX_LEN_0F17_M_0,
   1751   VEX_LEN_0F2A_P_1,
   1752   VEX_LEN_0F2A_P_3,
   1753   VEX_LEN_0F2C_P_1,
   1754   VEX_LEN_0F2C_P_3,
   1755   VEX_LEN_0F2D_P_1,
   1756   VEX_LEN_0F2D_P_3,
   1757   VEX_LEN_0F2E_P_0,
   1758   VEX_LEN_0F2E_P_2,
   1759   VEX_LEN_0F2F_P_0,
   1760   VEX_LEN_0F2F_P_2,
   1761   VEX_LEN_0F41_P_0,
   1762   VEX_LEN_0F41_P_2,
   1763   VEX_LEN_0F42_P_0,
   1764   VEX_LEN_0F42_P_2,
   1765   VEX_LEN_0F44_P_0,
   1766   VEX_LEN_0F44_P_2,
   1767   VEX_LEN_0F45_P_0,
   1768   VEX_LEN_0F45_P_2,
   1769   VEX_LEN_0F46_P_0,
   1770   VEX_LEN_0F46_P_2,
   1771   VEX_LEN_0F47_P_0,
   1772   VEX_LEN_0F47_P_2,
   1773   VEX_LEN_0F4A_P_0,
   1774   VEX_LEN_0F4A_P_2,
   1775   VEX_LEN_0F4B_P_0,
   1776   VEX_LEN_0F4B_P_2,
   1777   VEX_LEN_0F51_P_1,
   1778   VEX_LEN_0F51_P_3,
   1779   VEX_LEN_0F52_P_1,
   1780   VEX_LEN_0F53_P_1,
   1781   VEX_LEN_0F58_P_1,
   1782   VEX_LEN_0F58_P_3,
   1783   VEX_LEN_0F59_P_1,
   1784   VEX_LEN_0F59_P_3,
   1785   VEX_LEN_0F5A_P_1,
   1786   VEX_LEN_0F5A_P_3,
   1787   VEX_LEN_0F5C_P_1,
   1788   VEX_LEN_0F5C_P_3,
   1789   VEX_LEN_0F5D_P_1,
   1790   VEX_LEN_0F5D_P_3,
   1791   VEX_LEN_0F5E_P_1,
   1792   VEX_LEN_0F5E_P_3,
   1793   VEX_LEN_0F5F_P_1,
   1794   VEX_LEN_0F5F_P_3,
   1795   VEX_LEN_0F6E_P_2,
   1796   VEX_LEN_0F7E_P_1,
   1797   VEX_LEN_0F7E_P_2,
   1798   VEX_LEN_0F90_P_0,
   1799   VEX_LEN_0F90_P_2,
   1800   VEX_LEN_0F91_P_0,
   1801   VEX_LEN_0F91_P_2,
   1802   VEX_LEN_0F92_P_0,
   1803   VEX_LEN_0F92_P_2,
   1804   VEX_LEN_0F92_P_3,
   1805   VEX_LEN_0F93_P_0,
   1806   VEX_LEN_0F93_P_2,
   1807   VEX_LEN_0F93_P_3,
   1808   VEX_LEN_0F98_P_0,
   1809   VEX_LEN_0F98_P_2,
   1810   VEX_LEN_0F99_P_0,
   1811   VEX_LEN_0F99_P_2,
   1812   VEX_LEN_0FAE_R_2_M_0,
   1813   VEX_LEN_0FAE_R_3_M_0,
   1814   VEX_LEN_0FC2_P_1,
   1815   VEX_LEN_0FC2_P_3,
   1816   VEX_LEN_0FC4_P_2,
   1817   VEX_LEN_0FC5_P_2,
   1818   VEX_LEN_0FD6_P_2,
   1819   VEX_LEN_0FF7_P_2,
   1820   VEX_LEN_0F3816_P_2,
   1821   VEX_LEN_0F3819_P_2,
   1822   VEX_LEN_0F381A_P_2_M_0,
   1823   VEX_LEN_0F3836_P_2,
   1824   VEX_LEN_0F3841_P_2,
   1825   VEX_LEN_0F385A_P_2_M_0,
   1826   VEX_LEN_0F38DB_P_2,
   1827   VEX_LEN_0F38DC_P_2,
   1828   VEX_LEN_0F38DD_P_2,
   1829   VEX_LEN_0F38DE_P_2,
   1830   VEX_LEN_0F38DF_P_2,
   1831   VEX_LEN_0F38F2_P_0,
   1832   VEX_LEN_0F38F3_R_1_P_0,
   1833   VEX_LEN_0F38F3_R_2_P_0,
   1834   VEX_LEN_0F38F3_R_3_P_0,
   1835   VEX_LEN_0F38F5_P_0,
   1836   VEX_LEN_0F38F5_P_1,
   1837   VEX_LEN_0F38F5_P_3,
   1838   VEX_LEN_0F38F6_P_3,
   1839   VEX_LEN_0F38F7_P_0,
   1840   VEX_LEN_0F38F7_P_1,
   1841   VEX_LEN_0F38F7_P_2,
   1842   VEX_LEN_0F38F7_P_3,
   1843   VEX_LEN_0F3A00_P_2,
   1844   VEX_LEN_0F3A01_P_2,
   1845   VEX_LEN_0F3A06_P_2,
   1846   VEX_LEN_0F3A0A_P_2,
   1847   VEX_LEN_0F3A0B_P_2,
   1848   VEX_LEN_0F3A14_P_2,
   1849   VEX_LEN_0F3A15_P_2,
   1850   VEX_LEN_0F3A16_P_2,
   1851   VEX_LEN_0F3A17_P_2,
   1852   VEX_LEN_0F3A18_P_2,
   1853   VEX_LEN_0F3A19_P_2,
   1854   VEX_LEN_0F3A20_P_2,
   1855   VEX_LEN_0F3A21_P_2,
   1856   VEX_LEN_0F3A22_P_2,
   1857   VEX_LEN_0F3A30_P_2,
   1858   VEX_LEN_0F3A31_P_2,
   1859   VEX_LEN_0F3A32_P_2,
   1860   VEX_LEN_0F3A33_P_2,
   1861   VEX_LEN_0F3A38_P_2,
   1862   VEX_LEN_0F3A39_P_2,
   1863   VEX_LEN_0F3A41_P_2,
   1864   VEX_LEN_0F3A44_P_2,
   1865   VEX_LEN_0F3A46_P_2,
   1866   VEX_LEN_0F3A60_P_2,
   1867   VEX_LEN_0F3A61_P_2,
   1868   VEX_LEN_0F3A62_P_2,
   1869   VEX_LEN_0F3A63_P_2,
   1870   VEX_LEN_0F3A6A_P_2,
   1871   VEX_LEN_0F3A6B_P_2,
   1872   VEX_LEN_0F3A6E_P_2,
   1873   VEX_LEN_0F3A6F_P_2,
   1874   VEX_LEN_0F3A7A_P_2,
   1875   VEX_LEN_0F3A7B_P_2,
   1876   VEX_LEN_0F3A7E_P_2,
   1877   VEX_LEN_0F3A7F_P_2,
   1878   VEX_LEN_0F3ADF_P_2,
   1879   VEX_LEN_0F3AF0_P_3,
   1880   VEX_LEN_0FXOP_08_CC,
   1881   VEX_LEN_0FXOP_08_CD,
   1882   VEX_LEN_0FXOP_08_CE,
   1883   VEX_LEN_0FXOP_08_CF,
   1884   VEX_LEN_0FXOP_08_EC,
   1885   VEX_LEN_0FXOP_08_ED,
   1886   VEX_LEN_0FXOP_08_EE,
   1887   VEX_LEN_0FXOP_08_EF,
   1888   VEX_LEN_0FXOP_09_80,
   1889   VEX_LEN_0FXOP_09_81
   1890 };
   1891 
   1892 enum
   1893 {
   1894   VEX_W_0F10_P_0 = 0,
   1895   VEX_W_0F10_P_1,
   1896   VEX_W_0F10_P_2,
   1897   VEX_W_0F10_P_3,
   1898   VEX_W_0F11_P_0,
   1899   VEX_W_0F11_P_1,
   1900   VEX_W_0F11_P_2,
   1901   VEX_W_0F11_P_3,
   1902   VEX_W_0F12_P_0_M_0,
   1903   VEX_W_0F12_P_0_M_1,
   1904   VEX_W_0F12_P_1,
   1905   VEX_W_0F12_P_2,
   1906   VEX_W_0F12_P_3,
   1907   VEX_W_0F13_M_0,
   1908   VEX_W_0F14,
   1909   VEX_W_0F15,
   1910   VEX_W_0F16_P_0_M_0,
   1911   VEX_W_0F16_P_0_M_1,
   1912   VEX_W_0F16_P_1,
   1913   VEX_W_0F16_P_2,
   1914   VEX_W_0F17_M_0,
   1915   VEX_W_0F28,
   1916   VEX_W_0F29,
   1917   VEX_W_0F2B_M_0,
   1918   VEX_W_0F2E_P_0,
   1919   VEX_W_0F2E_P_2,
   1920   VEX_W_0F2F_P_0,
   1921   VEX_W_0F2F_P_2,
   1922   VEX_W_0F41_P_0_LEN_1,
   1923   VEX_W_0F41_P_2_LEN_1,
   1924   VEX_W_0F42_P_0_LEN_1,
   1925   VEX_W_0F42_P_2_LEN_1,
   1926   VEX_W_0F44_P_0_LEN_0,
   1927   VEX_W_0F44_P_2_LEN_0,
   1928   VEX_W_0F45_P_0_LEN_1,
   1929   VEX_W_0F45_P_2_LEN_1,
   1930   VEX_W_0F46_P_0_LEN_1,
   1931   VEX_W_0F46_P_2_LEN_1,
   1932   VEX_W_0F47_P_0_LEN_1,
   1933   VEX_W_0F47_P_2_LEN_1,
   1934   VEX_W_0F4A_P_0_LEN_1,
   1935   VEX_W_0F4A_P_2_LEN_1,
   1936   VEX_W_0F4B_P_0_LEN_1,
   1937   VEX_W_0F4B_P_2_LEN_1,
   1938   VEX_W_0F50_M_0,
   1939   VEX_W_0F51_P_0,
   1940   VEX_W_0F51_P_1,
   1941   VEX_W_0F51_P_2,
   1942   VEX_W_0F51_P_3,
   1943   VEX_W_0F52_P_0,
   1944   VEX_W_0F52_P_1,
   1945   VEX_W_0F53_P_0,
   1946   VEX_W_0F53_P_1,
   1947   VEX_W_0F58_P_0,
   1948   VEX_W_0F58_P_1,
   1949   VEX_W_0F58_P_2,
   1950   VEX_W_0F58_P_3,
   1951   VEX_W_0F59_P_0,
   1952   VEX_W_0F59_P_1,
   1953   VEX_W_0F59_P_2,
   1954   VEX_W_0F59_P_3,
   1955   VEX_W_0F5A_P_0,
   1956   VEX_W_0F5A_P_1,
   1957   VEX_W_0F5A_P_3,
   1958   VEX_W_0F5B_P_0,
   1959   VEX_W_0F5B_P_1,
   1960   VEX_W_0F5B_P_2,
   1961   VEX_W_0F5C_P_0,
   1962   VEX_W_0F5C_P_1,
   1963   VEX_W_0F5C_P_2,
   1964   VEX_W_0F5C_P_3,
   1965   VEX_W_0F5D_P_0,
   1966   VEX_W_0F5D_P_1,
   1967   VEX_W_0F5D_P_2,
   1968   VEX_W_0F5D_P_3,
   1969   VEX_W_0F5E_P_0,
   1970   VEX_W_0F5E_P_1,
   1971   VEX_W_0F5E_P_2,
   1972   VEX_W_0F5E_P_3,
   1973   VEX_W_0F5F_P_0,
   1974   VEX_W_0F5F_P_1,
   1975   VEX_W_0F5F_P_2,
   1976   VEX_W_0F5F_P_3,
   1977   VEX_W_0F60_P_2,
   1978   VEX_W_0F61_P_2,
   1979   VEX_W_0F62_P_2,
   1980   VEX_W_0F63_P_2,
   1981   VEX_W_0F64_P_2,
   1982   VEX_W_0F65_P_2,
   1983   VEX_W_0F66_P_2,
   1984   VEX_W_0F67_P_2,
   1985   VEX_W_0F68_P_2,
   1986   VEX_W_0F69_P_2,
   1987   VEX_W_0F6A_P_2,
   1988   VEX_W_0F6B_P_2,
   1989   VEX_W_0F6C_P_2,
   1990   VEX_W_0F6D_P_2,
   1991   VEX_W_0F6F_P_1,
   1992   VEX_W_0F6F_P_2,
   1993   VEX_W_0F70_P_1,
   1994   VEX_W_0F70_P_2,
   1995   VEX_W_0F70_P_3,
   1996   VEX_W_0F71_R_2_P_2,
   1997   VEX_W_0F71_R_4_P_2,
   1998   VEX_W_0F71_R_6_P_2,
   1999   VEX_W_0F72_R_2_P_2,
   2000   VEX_W_0F72_R_4_P_2,
   2001   VEX_W_0F72_R_6_P_2,
   2002   VEX_W_0F73_R_2_P_2,
   2003   VEX_W_0F73_R_3_P_2,
   2004   VEX_W_0F73_R_6_P_2,
   2005   VEX_W_0F73_R_7_P_2,
   2006   VEX_W_0F74_P_2,
   2007   VEX_W_0F75_P_2,
   2008   VEX_W_0F76_P_2,
   2009   VEX_W_0F77_P_0,
   2010   VEX_W_0F7C_P_2,
   2011   VEX_W_0F7C_P_3,
   2012   VEX_W_0F7D_P_2,
   2013   VEX_W_0F7D_P_3,
   2014   VEX_W_0F7E_P_1,
   2015   VEX_W_0F7F_P_1,
   2016   VEX_W_0F7F_P_2,
   2017   VEX_W_0F90_P_0_LEN_0,
   2018   VEX_W_0F90_P_2_LEN_0,
   2019   VEX_W_0F91_P_0_LEN_0,
   2020   VEX_W_0F91_P_2_LEN_0,
   2021   VEX_W_0F92_P_0_LEN_0,
   2022   VEX_W_0F92_P_2_LEN_0,
   2023   VEX_W_0F92_P_3_LEN_0,
   2024   VEX_W_0F93_P_0_LEN_0,
   2025   VEX_W_0F93_P_2_LEN_0,
   2026   VEX_W_0F93_P_3_LEN_0,
   2027   VEX_W_0F98_P_0_LEN_0,
   2028   VEX_W_0F98_P_2_LEN_0,
   2029   VEX_W_0F99_P_0_LEN_0,
   2030   VEX_W_0F99_P_2_LEN_0,
   2031   VEX_W_0FAE_R_2_M_0,
   2032   VEX_W_0FAE_R_3_M_0,
   2033   VEX_W_0FC2_P_0,
   2034   VEX_W_0FC2_P_1,
   2035   VEX_W_0FC2_P_2,
   2036   VEX_W_0FC2_P_3,
   2037   VEX_W_0FC4_P_2,
   2038   VEX_W_0FC5_P_2,
   2039   VEX_W_0FD0_P_2,
   2040   VEX_W_0FD0_P_3,
   2041   VEX_W_0FD1_P_2,
   2042   VEX_W_0FD2_P_2,
   2043   VEX_W_0FD3_P_2,
   2044   VEX_W_0FD4_P_2,
   2045   VEX_W_0FD5_P_2,
   2046   VEX_W_0FD6_P_2,
   2047   VEX_W_0FD7_P_2_M_1,
   2048   VEX_W_0FD8_P_2,
   2049   VEX_W_0FD9_P_2,
   2050   VEX_W_0FDA_P_2,
   2051   VEX_W_0FDB_P_2,
   2052   VEX_W_0FDC_P_2,
   2053   VEX_W_0FDD_P_2,
   2054   VEX_W_0FDE_P_2,
   2055   VEX_W_0FDF_P_2,
   2056   VEX_W_0FE0_P_2,
   2057   VEX_W_0FE1_P_2,
   2058   VEX_W_0FE2_P_2,
   2059   VEX_W_0FE3_P_2,
   2060   VEX_W_0FE4_P_2,
   2061   VEX_W_0FE5_P_2,
   2062   VEX_W_0FE6_P_1,
   2063   VEX_W_0FE6_P_2,
   2064   VEX_W_0FE6_P_3,
   2065   VEX_W_0FE7_P_2_M_0,
   2066   VEX_W_0FE8_P_2,
   2067   VEX_W_0FE9_P_2,
   2068   VEX_W_0FEA_P_2,
   2069   VEX_W_0FEB_P_2,
   2070   VEX_W_0FEC_P_2,
   2071   VEX_W_0FED_P_2,
   2072   VEX_W_0FEE_P_2,
   2073   VEX_W_0FEF_P_2,
   2074   VEX_W_0FF0_P_3_M_0,
   2075   VEX_W_0FF1_P_2,
   2076   VEX_W_0FF2_P_2,
   2077   VEX_W_0FF3_P_2,
   2078   VEX_W_0FF4_P_2,
   2079   VEX_W_0FF5_P_2,
   2080   VEX_W_0FF6_P_2,
   2081   VEX_W_0FF7_P_2,
   2082   VEX_W_0FF8_P_2,
   2083   VEX_W_0FF9_P_2,
   2084   VEX_W_0FFA_P_2,
   2085   VEX_W_0FFB_P_2,
   2086   VEX_W_0FFC_P_2,
   2087   VEX_W_0FFD_P_2,
   2088   VEX_W_0FFE_P_2,
   2089   VEX_W_0F3800_P_2,
   2090   VEX_W_0F3801_P_2,
   2091   VEX_W_0F3802_P_2,
   2092   VEX_W_0F3803_P_2,
   2093   VEX_W_0F3804_P_2,
   2094   VEX_W_0F3805_P_2,
   2095   VEX_W_0F3806_P_2,
   2096   VEX_W_0F3807_P_2,
   2097   VEX_W_0F3808_P_2,
   2098   VEX_W_0F3809_P_2,
   2099   VEX_W_0F380A_P_2,
   2100   VEX_W_0F380B_P_2,
   2101   VEX_W_0F380C_P_2,
   2102   VEX_W_0F380D_P_2,
   2103   VEX_W_0F380E_P_2,
   2104   VEX_W_0F380F_P_2,
   2105   VEX_W_0F3816_P_2,
   2106   VEX_W_0F3817_P_2,
   2107   VEX_W_0F3818_P_2,
   2108   VEX_W_0F3819_P_2,
   2109   VEX_W_0F381A_P_2_M_0,
   2110   VEX_W_0F381C_P_2,
   2111   VEX_W_0F381D_P_2,
   2112   VEX_W_0F381E_P_2,
   2113   VEX_W_0F3820_P_2,
   2114   VEX_W_0F3821_P_2,
   2115   VEX_W_0F3822_P_2,
   2116   VEX_W_0F3823_P_2,
   2117   VEX_W_0F3824_P_2,
   2118   VEX_W_0F3825_P_2,
   2119   VEX_W_0F3828_P_2,
   2120   VEX_W_0F3829_P_2,
   2121   VEX_W_0F382A_P_2_M_0,
   2122   VEX_W_0F382B_P_2,
   2123   VEX_W_0F382C_P_2_M_0,
   2124   VEX_W_0F382D_P_2_M_0,
   2125   VEX_W_0F382E_P_2_M_0,
   2126   VEX_W_0F382F_P_2_M_0,
   2127   VEX_W_0F3830_P_2,
   2128   VEX_W_0F3831_P_2,
   2129   VEX_W_0F3832_P_2,
   2130   VEX_W_0F3833_P_2,
   2131   VEX_W_0F3834_P_2,
   2132   VEX_W_0F3835_P_2,
   2133   VEX_W_0F3836_P_2,
   2134   VEX_W_0F3837_P_2,
   2135   VEX_W_0F3838_P_2,
   2136   VEX_W_0F3839_P_2,
   2137   VEX_W_0F383A_P_2,
   2138   VEX_W_0F383B_P_2,
   2139   VEX_W_0F383C_P_2,
   2140   VEX_W_0F383D_P_2,
   2141   VEX_W_0F383E_P_2,
   2142   VEX_W_0F383F_P_2,
   2143   VEX_W_0F3840_P_2,
   2144   VEX_W_0F3841_P_2,
   2145   VEX_W_0F3846_P_2,
   2146   VEX_W_0F3858_P_2,
   2147   VEX_W_0F3859_P_2,
   2148   VEX_W_0F385A_P_2_M_0,
   2149   VEX_W_0F3878_P_2,
   2150   VEX_W_0F3879_P_2,
   2151   VEX_W_0F38DB_P_2,
   2152   VEX_W_0F38DC_P_2,
   2153   VEX_W_0F38DD_P_2,
   2154   VEX_W_0F38DE_P_2,
   2155   VEX_W_0F38DF_P_2,
   2156   VEX_W_0F3A00_P_2,
   2157   VEX_W_0F3A01_P_2,
   2158   VEX_W_0F3A02_P_2,
   2159   VEX_W_0F3A04_P_2,
   2160   VEX_W_0F3A05_P_2,
   2161   VEX_W_0F3A06_P_2,
   2162   VEX_W_0F3A08_P_2,
   2163   VEX_W_0F3A09_P_2,
   2164   VEX_W_0F3A0A_P_2,
   2165   VEX_W_0F3A0B_P_2,
   2166   VEX_W_0F3A0C_P_2,
   2167   VEX_W_0F3A0D_P_2,
   2168   VEX_W_0F3A0E_P_2,
   2169   VEX_W_0F3A0F_P_2,
   2170   VEX_W_0F3A14_P_2,
   2171   VEX_W_0F3A15_P_2,
   2172   VEX_W_0F3A18_P_2,
   2173   VEX_W_0F3A19_P_2,
   2174   VEX_W_0F3A20_P_2,
   2175   VEX_W_0F3A21_P_2,
   2176   VEX_W_0F3A30_P_2_LEN_0,
   2177   VEX_W_0F3A31_P_2_LEN_0,
   2178   VEX_W_0F3A32_P_2_LEN_0,
   2179   VEX_W_0F3A33_P_2_LEN_0,
   2180   VEX_W_0F3A38_P_2,
   2181   VEX_W_0F3A39_P_2,
   2182   VEX_W_0F3A40_P_2,
   2183   VEX_W_0F3A41_P_2,
   2184   VEX_W_0F3A42_P_2,
   2185   VEX_W_0F3A44_P_2,
   2186   VEX_W_0F3A46_P_2,
   2187   VEX_W_0F3A48_P_2,
   2188   VEX_W_0F3A49_P_2,
   2189   VEX_W_0F3A4A_P_2,
   2190   VEX_W_0F3A4B_P_2,
   2191   VEX_W_0F3A4C_P_2,
   2192   VEX_W_0F3A60_P_2,
   2193   VEX_W_0F3A61_P_2,
   2194   VEX_W_0F3A62_P_2,
   2195   VEX_W_0F3A63_P_2,
   2196   VEX_W_0F3ADF_P_2,
   2197 
   2198   EVEX_W_0F10_P_0,
   2199   EVEX_W_0F10_P_1_M_0,
   2200   EVEX_W_0F10_P_1_M_1,
   2201   EVEX_W_0F10_P_2,
   2202   EVEX_W_0F10_P_3_M_0,
   2203   EVEX_W_0F10_P_3_M_1,
   2204   EVEX_W_0F11_P_0,
   2205   EVEX_W_0F11_P_1_M_0,
   2206   EVEX_W_0F11_P_1_M_1,
   2207   EVEX_W_0F11_P_2,
   2208   EVEX_W_0F11_P_3_M_0,
   2209   EVEX_W_0F11_P_3_M_1,
   2210   EVEX_W_0F12_P_0_M_0,
   2211   EVEX_W_0F12_P_0_M_1,
   2212   EVEX_W_0F12_P_1,
   2213   EVEX_W_0F12_P_2,
   2214   EVEX_W_0F12_P_3,
   2215   EVEX_W_0F13_P_0,
   2216   EVEX_W_0F13_P_2,
   2217   EVEX_W_0F14_P_0,
   2218   EVEX_W_0F14_P_2,
   2219   EVEX_W_0F15_P_0,
   2220   EVEX_W_0F15_P_2,
   2221   EVEX_W_0F16_P_0_M_0,
   2222   EVEX_W_0F16_P_0_M_1,
   2223   EVEX_W_0F16_P_1,
   2224   EVEX_W_0F16_P_2,
   2225   EVEX_W_0F17_P_0,
   2226   EVEX_W_0F17_P_2,
   2227   EVEX_W_0F28_P_0,
   2228   EVEX_W_0F28_P_2,
   2229   EVEX_W_0F29_P_0,
   2230   EVEX_W_0F29_P_2,
   2231   EVEX_W_0F2A_P_1,
   2232   EVEX_W_0F2A_P_3,
   2233   EVEX_W_0F2B_P_0,
   2234   EVEX_W_0F2B_P_2,
   2235   EVEX_W_0F2E_P_0,
   2236   EVEX_W_0F2E_P_2,
   2237   EVEX_W_0F2F_P_0,
   2238   EVEX_W_0F2F_P_2,
   2239   EVEX_W_0F51_P_0,
   2240   EVEX_W_0F51_P_1,
   2241   EVEX_W_0F51_P_2,
   2242   EVEX_W_0F51_P_3,
   2243   EVEX_W_0F54_P_0,
   2244   EVEX_W_0F54_P_2,
   2245   EVEX_W_0F55_P_0,
   2246   EVEX_W_0F55_P_2,
   2247   EVEX_W_0F56_P_0,
   2248   EVEX_W_0F56_P_2,
   2249   EVEX_W_0F57_P_0,
   2250   EVEX_W_0F57_P_2,
   2251   EVEX_W_0F58_P_0,
   2252   EVEX_W_0F58_P_1,
   2253   EVEX_W_0F58_P_2,
   2254   EVEX_W_0F58_P_3,
   2255   EVEX_W_0F59_P_0,
   2256   EVEX_W_0F59_P_1,
   2257   EVEX_W_0F59_P_2,
   2258   EVEX_W_0F59_P_3,
   2259   EVEX_W_0F5A_P_0,
   2260   EVEX_W_0F5A_P_1,
   2261   EVEX_W_0F5A_P_2,
   2262   EVEX_W_0F5A_P_3,
   2263   EVEX_W_0F5B_P_0,
   2264   EVEX_W_0F5B_P_1,
   2265   EVEX_W_0F5B_P_2,
   2266   EVEX_W_0F5C_P_0,
   2267   EVEX_W_0F5C_P_1,
   2268   EVEX_W_0F5C_P_2,
   2269   EVEX_W_0F5C_P_3,
   2270   EVEX_W_0F5D_P_0,
   2271   EVEX_W_0F5D_P_1,
   2272   EVEX_W_0F5D_P_2,
   2273   EVEX_W_0F5D_P_3,
   2274   EVEX_W_0F5E_P_0,
   2275   EVEX_W_0F5E_P_1,
   2276   EVEX_W_0F5E_P_2,
   2277   EVEX_W_0F5E_P_3,
   2278   EVEX_W_0F5F_P_0,
   2279   EVEX_W_0F5F_P_1,
   2280   EVEX_W_0F5F_P_2,
   2281   EVEX_W_0F5F_P_3,
   2282   EVEX_W_0F62_P_2,
   2283   EVEX_W_0F66_P_2,
   2284   EVEX_W_0F6A_P_2,
   2285   EVEX_W_0F6B_P_2,
   2286   EVEX_W_0F6C_P_2,
   2287   EVEX_W_0F6D_P_2,
   2288   EVEX_W_0F6E_P_2,
   2289   EVEX_W_0F6F_P_1,
   2290   EVEX_W_0F6F_P_2,
   2291   EVEX_W_0F6F_P_3,
   2292   EVEX_W_0F70_P_2,
   2293   EVEX_W_0F72_R_2_P_2,
   2294   EVEX_W_0F72_R_6_P_2,
   2295   EVEX_W_0F73_R_2_P_2,
   2296   EVEX_W_0F73_R_6_P_2,
   2297   EVEX_W_0F76_P_2,
   2298   EVEX_W_0F78_P_0,
   2299   EVEX_W_0F78_P_2,
   2300   EVEX_W_0F79_P_0,
   2301   EVEX_W_0F79_P_2,
   2302   EVEX_W_0F7A_P_1,
   2303   EVEX_W_0F7A_P_2,
   2304   EVEX_W_0F7A_P_3,
   2305   EVEX_W_0F7B_P_1,
   2306   EVEX_W_0F7B_P_2,
   2307   EVEX_W_0F7B_P_3,
   2308   EVEX_W_0F7E_P_1,
   2309   EVEX_W_0F7E_P_2,
   2310   EVEX_W_0F7F_P_1,
   2311   EVEX_W_0F7F_P_2,
   2312   EVEX_W_0F7F_P_3,
   2313   EVEX_W_0FC2_P_0,
   2314   EVEX_W_0FC2_P_1,
   2315   EVEX_W_0FC2_P_2,
   2316   EVEX_W_0FC2_P_3,
   2317   EVEX_W_0FC6_P_0,
   2318   EVEX_W_0FC6_P_2,
   2319   EVEX_W_0FD2_P_2,
   2320   EVEX_W_0FD3_P_2,
   2321   EVEX_W_0FD4_P_2,
   2322   EVEX_W_0FD6_P_2,
   2323   EVEX_W_0FE6_P_1,
   2324   EVEX_W_0FE6_P_2,
   2325   EVEX_W_0FE6_P_3,
   2326   EVEX_W_0FE7_P_2,
   2327   EVEX_W_0FF2_P_2,
   2328   EVEX_W_0FF3_P_2,
   2329   EVEX_W_0FF4_P_2,
   2330   EVEX_W_0FFA_P_2,
   2331   EVEX_W_0FFB_P_2,
   2332   EVEX_W_0FFE_P_2,
   2333   EVEX_W_0F380C_P_2,
   2334   EVEX_W_0F380D_P_2,
   2335   EVEX_W_0F3810_P_1,
   2336   EVEX_W_0F3810_P_2,
   2337   EVEX_W_0F3811_P_1,
   2338   EVEX_W_0F3811_P_2,
   2339   EVEX_W_0F3812_P_1,
   2340   EVEX_W_0F3812_P_2,
   2341   EVEX_W_0F3813_P_1,
   2342   EVEX_W_0F3813_P_2,
   2343   EVEX_W_0F3814_P_1,
   2344   EVEX_W_0F3815_P_1,
   2345   EVEX_W_0F3818_P_2,
   2346   EVEX_W_0F3819_P_2,
   2347   EVEX_W_0F381A_P_2,
   2348   EVEX_W_0F381B_P_2,
   2349   EVEX_W_0F381E_P_2,
   2350   EVEX_W_0F381F_P_2,
   2351   EVEX_W_0F3820_P_1,
   2352   EVEX_W_0F3821_P_1,
   2353   EVEX_W_0F3822_P_1,
   2354   EVEX_W_0F3823_P_1,
   2355   EVEX_W_0F3824_P_1,
   2356   EVEX_W_0F3825_P_1,
   2357   EVEX_W_0F3825_P_2,
   2358   EVEX_W_0F3826_P_1,
   2359   EVEX_W_0F3826_P_2,
   2360   EVEX_W_0F3828_P_1,
   2361   EVEX_W_0F3828_P_2,
   2362   EVEX_W_0F3829_P_1,
   2363   EVEX_W_0F3829_P_2,
   2364   EVEX_W_0F382A_P_1,
   2365   EVEX_W_0F382A_P_2,
   2366   EVEX_W_0F382B_P_2,
   2367   EVEX_W_0F3830_P_1,
   2368   EVEX_W_0F3831_P_1,
   2369   EVEX_W_0F3832_P_1,
   2370   EVEX_W_0F3833_P_1,
   2371   EVEX_W_0F3834_P_1,
   2372   EVEX_W_0F3835_P_1,
   2373   EVEX_W_0F3835_P_2,
   2374   EVEX_W_0F3837_P_2,
   2375   EVEX_W_0F3838_P_1,
   2376   EVEX_W_0F3839_P_1,
   2377   EVEX_W_0F383A_P_1,
   2378   EVEX_W_0F3840_P_2,
   2379   EVEX_W_0F3858_P_2,
   2380   EVEX_W_0F3859_P_2,
   2381   EVEX_W_0F385A_P_2,
   2382   EVEX_W_0F385B_P_2,
   2383   EVEX_W_0F3866_P_2,
   2384   EVEX_W_0F3875_P_2,
   2385   EVEX_W_0F3878_P_2,
   2386   EVEX_W_0F3879_P_2,
   2387   EVEX_W_0F387A_P_2,
   2388   EVEX_W_0F387B_P_2,
   2389   EVEX_W_0F387D_P_2,
   2390   EVEX_W_0F3883_P_2,
   2391   EVEX_W_0F388D_P_2,
   2392   EVEX_W_0F3891_P_2,
   2393   EVEX_W_0F3893_P_2,
   2394   EVEX_W_0F38A1_P_2,
   2395   EVEX_W_0F38A3_P_2,
   2396   EVEX_W_0F38C7_R_1_P_2,
   2397   EVEX_W_0F38C7_R_2_P_2,
   2398   EVEX_W_0F38C7_R_5_P_2,
   2399   EVEX_W_0F38C7_R_6_P_2,
   2400 
   2401   EVEX_W_0F3A00_P_2,
   2402   EVEX_W_0F3A01_P_2,
   2403   EVEX_W_0F3A04_P_2,
   2404   EVEX_W_0F3A05_P_2,
   2405   EVEX_W_0F3A08_P_2,
   2406   EVEX_W_0F3A09_P_2,
   2407   EVEX_W_0F3A0A_P_2,
   2408   EVEX_W_0F3A0B_P_2,
   2409   EVEX_W_0F3A16_P_2,
   2410   EVEX_W_0F3A18_P_2,
   2411   EVEX_W_0F3A19_P_2,
   2412   EVEX_W_0F3A1A_P_2,
   2413   EVEX_W_0F3A1B_P_2,
   2414   EVEX_W_0F3A1D_P_2,
   2415   EVEX_W_0F3A21_P_2,
   2416   EVEX_W_0F3A22_P_2,
   2417   EVEX_W_0F3A23_P_2,
   2418   EVEX_W_0F3A38_P_2,
   2419   EVEX_W_0F3A39_P_2,
   2420   EVEX_W_0F3A3A_P_2,
   2421   EVEX_W_0F3A3B_P_2,
   2422   EVEX_W_0F3A3E_P_2,
   2423   EVEX_W_0F3A3F_P_2,
   2424   EVEX_W_0F3A42_P_2,
   2425   EVEX_W_0F3A43_P_2,
   2426   EVEX_W_0F3A50_P_2,
   2427   EVEX_W_0F3A51_P_2,
   2428   EVEX_W_0F3A56_P_2,
   2429   EVEX_W_0F3A57_P_2,
   2430   EVEX_W_0F3A66_P_2,
   2431   EVEX_W_0F3A67_P_2
   2432 };
   2433 
   2434 typedef void (*op_rtn) (int bytemode, int sizeflag);
   2435 
   2436 struct dis386 {
   2437   const char *name;
   2438   struct
   2439     {
   2440       op_rtn rtn;
   2441       int bytemode;
   2442     } op[MAX_OPERANDS];
   2443   unsigned int prefix_requirement;
   2444 };
   2445 
   2446 /* Upper case letters in the instruction names here are macros.
   2447    'A' => print 'b' if no register operands or suffix_always is true
   2448    'B' => print 'b' if suffix_always is true
   2449    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
   2450 	  size prefix
   2451    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
   2452 	  suffix_always is true
   2453    'E' => print 'e' if 32-bit form of jcxz
   2454    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
   2455    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
   2456    'H' => print ",pt" or ",pn" branch hint
   2457    'I' => honor following macro letter even in Intel mode (implemented only
   2458 	  for some of the macro letters)
   2459    'J' => print 'l'
   2460    'K' => print 'd' or 'q' if rex prefix is present.
   2461    'L' => print 'l' if suffix_always is true
   2462    'M' => print 'r' if intel_mnemonic is false.
   2463    'N' => print 'n' if instruction has no wait "prefix"
   2464    'O' => print 'd' or 'o' (or 'q' in Intel mode)
   2465    'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
   2466 	  or suffix_always is true.  print 'q' if rex prefix is present.
   2467    'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
   2468 	  is true
   2469    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
   2470    'S' => print 'w', 'l' or 'q' if suffix_always is true
   2471    'T' => print 'q' in 64bit mode if instruction has no operand size
   2472 	  prefix and behave as 'P' otherwise
   2473    'U' => print 'q' in 64bit mode if instruction has no operand size
   2474 	  prefix and behave as 'Q' otherwise
   2475    'V' => print 'q' in 64bit mode if instruction has no operand size
   2476 	  prefix and behave as 'S' otherwise
   2477    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
   2478    'X' => print 's', 'd' depending on data16 prefix (for XMM)
   2479    'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
   2480 	  suffix_always is true.
   2481    'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
   2482    '!' => change condition from true to false or from false to true.
   2483    '%' => add 1 upper case letter to the macro.
   2484    '^' => print 'w' or 'l' depending on operand size prefix or
   2485 	  suffix_always is true (lcall/ljmp).
   2486    '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
   2487 	  on operand size prefix.
   2488    '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction
   2489 	  has no operand size prefix for AMD64 ISA, behave as 'P'
   2490 	  otherwise
   2491 
   2492    2 upper case letter macros:
   2493    "XY" => print 'x' or 'y' if suffix_always is true or no register
   2494 	   operands and no broadcast.
   2495    "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
   2496 	   register operands and no broadcast.
   2497    "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
   2498    "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
   2499 	   or suffix_always is true
   2500    "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
   2501    "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
   2502    "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
   2503    "LW" => print 'd', 'q' depending on the VEX.W bit
   2504    "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
   2505 	   an operand size prefix, or suffix_always is true.  print
   2506 	   'q' if rex prefix is present.
   2507 
   2508    Many of the above letters print nothing in Intel mode.  See "putop"
   2509    for the details.
   2510 
   2511    Braces '{' and '}', and vertical bars '|', indicate alternative
   2512    mnemonic strings for AT&T and Intel.  */
   2513 
   2514 static const struct dis386 dis386[] = {
   2515   /* 00 */
   2516   { "addB",		{ Ebh1, Gb }, 0 },
   2517   { "addS",		{ Evh1, Gv }, 0 },
   2518   { "addB",		{ Gb, EbS }, 0 },
   2519   { "addS",		{ Gv, EvS }, 0 },
   2520   { "addB",		{ AL, Ib }, 0 },
   2521   { "addS",		{ eAX, Iv }, 0 },
   2522   { X86_64_TABLE (X86_64_06) },
   2523   { X86_64_TABLE (X86_64_07) },
   2524   /* 08 */
   2525   { "orB",		{ Ebh1, Gb }, 0 },
   2526   { "orS",		{ Evh1, Gv }, 0 },
   2527   { "orB",		{ Gb, EbS }, 0 },
   2528   { "orS",		{ Gv, EvS }, 0 },
   2529   { "orB",		{ AL, Ib }, 0 },
   2530   { "orS",		{ eAX, Iv }, 0 },
   2531   { X86_64_TABLE (X86_64_0D) },
   2532   { Bad_Opcode },	/* 0x0f extended opcode escape */
   2533   /* 10 */
   2534   { "adcB",		{ Ebh1, Gb }, 0 },
   2535   { "adcS",		{ Evh1, Gv }, 0 },
   2536   { "adcB",		{ Gb, EbS }, 0 },
   2537   { "adcS",		{ Gv, EvS }, 0 },
   2538   { "adcB",		{ AL, Ib }, 0 },
   2539   { "adcS",		{ eAX, Iv }, 0 },
   2540   { X86_64_TABLE (X86_64_16) },
   2541   { X86_64_TABLE (X86_64_17) },
   2542   /* 18 */
   2543   { "sbbB",		{ Ebh1, Gb }, 0 },
   2544   { "sbbS",		{ Evh1, Gv }, 0 },
   2545   { "sbbB",		{ Gb, EbS }, 0 },
   2546   { "sbbS",		{ Gv, EvS }, 0 },
   2547   { "sbbB",		{ AL, Ib }, 0 },
   2548   { "sbbS",		{ eAX, Iv }, 0 },
   2549   { X86_64_TABLE (X86_64_1E) },
   2550   { X86_64_TABLE (X86_64_1F) },
   2551   /* 20 */
   2552   { "andB",		{ Ebh1, Gb }, 0 },
   2553   { "andS",		{ Evh1, Gv }, 0 },
   2554   { "andB",		{ Gb, EbS }, 0 },
   2555   { "andS",		{ Gv, EvS }, 0 },
   2556   { "andB",		{ AL, Ib }, 0 },
   2557   { "andS",		{ eAX, Iv }, 0 },
   2558   { Bad_Opcode },	/* SEG ES prefix */
   2559   { X86_64_TABLE (X86_64_27) },
   2560   /* 28 */
   2561   { "subB",		{ Ebh1, Gb }, 0 },
   2562   { "subS",		{ Evh1, Gv }, 0 },
   2563   { "subB",		{ Gb, EbS }, 0 },
   2564   { "subS",		{ Gv, EvS }, 0 },
   2565   { "subB",		{ AL, Ib }, 0 },
   2566   { "subS",		{ eAX, Iv }, 0 },
   2567   { Bad_Opcode },	/* SEG CS prefix */
   2568   { X86_64_TABLE (X86_64_2F) },
   2569   /* 30 */
   2570   { "xorB",		{ Ebh1, Gb }, 0 },
   2571   { "xorS",		{ Evh1, Gv }, 0 },
   2572   { "xorB",		{ Gb, EbS }, 0 },
   2573   { "xorS",		{ Gv, EvS }, 0 },
   2574   { "xorB",		{ AL, Ib }, 0 },
   2575   { "xorS",		{ eAX, Iv }, 0 },
   2576   { Bad_Opcode },	/* SEG SS prefix */
   2577   { X86_64_TABLE (X86_64_37) },
   2578   /* 38 */
   2579   { "cmpB",		{ Eb, Gb }, 0 },
   2580   { "cmpS",		{ Ev, Gv }, 0 },
   2581   { "cmpB",		{ Gb, EbS }, 0 },
   2582   { "cmpS",		{ Gv, EvS }, 0 },
   2583   { "cmpB",		{ AL, Ib }, 0 },
   2584   { "cmpS",		{ eAX, Iv }, 0 },
   2585   { Bad_Opcode },	/* SEG DS prefix */
   2586   { X86_64_TABLE (X86_64_3F) },
   2587   /* 40 */
   2588   { "inc{S|}",		{ RMeAX }, 0 },
   2589   { "inc{S|}",		{ RMeCX }, 0 },
   2590   { "inc{S|}",		{ RMeDX }, 0 },
   2591   { "inc{S|}",		{ RMeBX }, 0 },
   2592   { "inc{S|}",		{ RMeSP }, 0 },
   2593   { "inc{S|}",		{ RMeBP }, 0 },
   2594   { "inc{S|}",		{ RMeSI }, 0 },
   2595   { "inc{S|}",		{ RMeDI }, 0 },
   2596   /* 48 */
   2597   { "dec{S|}",		{ RMeAX }, 0 },
   2598   { "dec{S|}",		{ RMeCX }, 0 },
   2599   { "dec{S|}",		{ RMeDX }, 0 },
   2600   { "dec{S|}",		{ RMeBX }, 0 },
   2601   { "dec{S|}",		{ RMeSP }, 0 },
   2602   { "dec{S|}",		{ RMeBP }, 0 },
   2603   { "dec{S|}",		{ RMeSI }, 0 },
   2604   { "dec{S|}",		{ RMeDI }, 0 },
   2605   /* 50 */
   2606   { "pushV",		{ RMrAX }, 0 },
   2607   { "pushV",		{ RMrCX }, 0 },
   2608   { "pushV",		{ RMrDX }, 0 },
   2609   { "pushV",		{ RMrBX }, 0 },
   2610   { "pushV",		{ RMrSP }, 0 },
   2611   { "pushV",		{ RMrBP }, 0 },
   2612   { "pushV",		{ RMrSI }, 0 },
   2613   { "pushV",		{ RMrDI }, 0 },
   2614   /* 58 */
   2615   { "popV",		{ RMrAX }, 0 },
   2616   { "popV",		{ RMrCX }, 0 },
   2617   { "popV",		{ RMrDX }, 0 },
   2618   { "popV",		{ RMrBX }, 0 },
   2619   { "popV",		{ RMrSP }, 0 },
   2620   { "popV",		{ RMrBP }, 0 },
   2621   { "popV",		{ RMrSI }, 0 },
   2622   { "popV",		{ RMrDI }, 0 },
   2623   /* 60 */
   2624   { X86_64_TABLE (X86_64_60) },
   2625   { X86_64_TABLE (X86_64_61) },
   2626   { X86_64_TABLE (X86_64_62) },
   2627   { X86_64_TABLE (X86_64_63) },
   2628   { Bad_Opcode },	/* seg fs */
   2629   { Bad_Opcode },	/* seg gs */
   2630   { Bad_Opcode },	/* op size prefix */
   2631   { Bad_Opcode },	/* adr size prefix */
   2632   /* 68 */
   2633   { "pushT",		{ sIv }, 0 },
   2634   { "imulS",		{ Gv, Ev, Iv }, 0 },
   2635   { "pushT",		{ sIbT }, 0 },
   2636   { "imulS",		{ Gv, Ev, sIb }, 0 },
   2637   { "ins{b|}",		{ Ybr, indirDX }, 0 },
   2638   { X86_64_TABLE (X86_64_6D) },
   2639   { "outs{b|}",		{ indirDXr, Xb }, 0 },
   2640   { X86_64_TABLE (X86_64_6F) },
   2641   /* 70 */
   2642   { "joH",		{ Jb, BND, cond_jump_flag }, 0 },
   2643   { "jnoH",		{ Jb, BND, cond_jump_flag }, 0 },
   2644   { "jbH",		{ Jb, BND, cond_jump_flag }, 0 },
   2645   { "jaeH",		{ Jb, BND, cond_jump_flag }, 0 },
   2646   { "jeH",		{ Jb, BND, cond_jump_flag }, 0 },
   2647   { "jneH",		{ Jb, BND, cond_jump_flag }, 0 },
   2648   { "jbeH",		{ Jb, BND, cond_jump_flag }, 0 },
   2649   { "jaH",		{ Jb, BND, cond_jump_flag }, 0 },
   2650   /* 78 */
   2651   { "jsH",		{ Jb, BND, cond_jump_flag }, 0 },
   2652   { "jnsH",		{ Jb, BND, cond_jump_flag }, 0 },
   2653   { "jpH",		{ Jb, BND, cond_jump_flag }, 0 },
   2654   { "jnpH",		{ Jb, BND, cond_jump_flag }, 0 },
   2655   { "jlH",		{ Jb, BND, cond_jump_flag }, 0 },
   2656   { "jgeH",		{ Jb, BND, cond_jump_flag }, 0 },
   2657   { "jleH",		{ Jb, BND, cond_jump_flag }, 0 },
   2658   { "jgH",		{ Jb, BND, cond_jump_flag }, 0 },
   2659   /* 80 */
   2660   { REG_TABLE (REG_80) },
   2661   { REG_TABLE (REG_81) },
   2662   { Bad_Opcode },
   2663   { REG_TABLE (REG_82) },
   2664   { "testB",		{ Eb, Gb }, 0 },
   2665   { "testS",		{ Ev, Gv }, 0 },
   2666   { "xchgB",		{ Ebh2, Gb }, 0 },
   2667   { "xchgS",		{ Evh2, Gv }, 0 },
   2668   /* 88 */
   2669   { "movB",		{ Ebh3, Gb }, 0 },
   2670   { "movS",		{ Evh3, Gv }, 0 },
   2671   { "movB",		{ Gb, EbS }, 0 },
   2672   { "movS",		{ Gv, EvS }, 0 },
   2673   { "movD",		{ Sv, Sw }, 0 },
   2674   { MOD_TABLE (MOD_8D) },
   2675   { "movD",		{ Sw, Sv }, 0 },
   2676   { REG_TABLE (REG_8F) },
   2677   /* 90 */
   2678   { PREFIX_TABLE (PREFIX_90) },
   2679   { "xchgS",		{ RMeCX, eAX }, 0 },
   2680   { "xchgS",		{ RMeDX, eAX }, 0 },
   2681   { "xchgS",		{ RMeBX, eAX }, 0 },
   2682   { "xchgS",		{ RMeSP, eAX }, 0 },
   2683   { "xchgS",		{ RMeBP, eAX }, 0 },
   2684   { "xchgS",		{ RMeSI, eAX }, 0 },
   2685   { "xchgS",		{ RMeDI, eAX }, 0 },
   2686   /* 98 */
   2687   { "cW{t|}R",		{ XX }, 0 },
   2688   { "cR{t|}O",		{ XX }, 0 },
   2689   { X86_64_TABLE (X86_64_9A) },
   2690   { Bad_Opcode },	/* fwait */
   2691   { "pushfT",		{ XX }, 0 },
   2692   { "popfT",		{ XX }, 0 },
   2693   { "sahf",		{ XX }, 0 },
   2694   { "lahf",		{ XX }, 0 },
   2695   /* a0 */
   2696   { "mov%LB",		{ AL, Ob }, 0 },
   2697   { "mov%LS",		{ eAX, Ov }, 0 },
   2698   { "mov%LB",		{ Ob, AL }, 0 },
   2699   { "mov%LS",		{ Ov, eAX }, 0 },
   2700   { "movs{b|}",		{ Ybr, Xb }, 0 },
   2701   { "movs{R|}",		{ Yvr, Xv }, 0 },
   2702   { "cmps{b|}",		{ Xb, Yb }, 0 },
   2703   { "cmps{R|}",		{ Xv, Yv }, 0 },
   2704   /* a8 */
   2705   { "testB",		{ AL, Ib }, 0 },
   2706   { "testS",		{ eAX, Iv }, 0 },
   2707   { "stosB",		{ Ybr, AL }, 0 },
   2708   { "stosS",		{ Yvr, eAX }, 0 },
   2709   { "lodsB",		{ ALr, Xb }, 0 },
   2710   { "lodsS",		{ eAXr, Xv }, 0 },
   2711   { "scasB",		{ AL, Yb }, 0 },
   2712   { "scasS",		{ eAX, Yv }, 0 },
   2713   /* b0 */
   2714   { "movB",		{ RMAL, Ib }, 0 },
   2715   { "movB",		{ RMCL, Ib }, 0 },
   2716   { "movB",		{ RMDL, Ib }, 0 },
   2717   { "movB",		{ RMBL, Ib }, 0 },
   2718   { "movB",		{ RMAH, Ib }, 0 },
   2719   { "movB",		{ RMCH, Ib }, 0 },
   2720   { "movB",		{ RMDH, Ib }, 0 },
   2721   { "movB",		{ RMBH, Ib }, 0 },
   2722   /* b8 */
   2723   { "mov%LV",		{ RMeAX, Iv64 }, 0 },
   2724   { "mov%LV",		{ RMeCX, Iv64 }, 0 },
   2725   { "mov%LV",		{ RMeDX, Iv64 }, 0 },
   2726   { "mov%LV",		{ RMeBX, Iv64 }, 0 },
   2727   { "mov%LV",		{ RMeSP, Iv64 }, 0 },
   2728   { "mov%LV",		{ RMeBP, Iv64 }, 0 },
   2729   { "mov%LV",		{ RMeSI, Iv64 }, 0 },
   2730   { "mov%LV",		{ RMeDI, Iv64 }, 0 },
   2731   /* c0 */
   2732   { REG_TABLE (REG_C0) },
   2733   { REG_TABLE (REG_C1) },
   2734   { "retT",		{ Iw, BND }, 0 },
   2735   { "retT",		{ BND }, 0 },
   2736   { X86_64_TABLE (X86_64_C4) },
   2737   { X86_64_TABLE (X86_64_C5) },
   2738   { REG_TABLE (REG_C6) },
   2739   { REG_TABLE (REG_C7) },
   2740   /* c8 */
   2741   { "enterT",		{ Iw, Ib }, 0 },
   2742   { "leaveT",		{ XX }, 0 },
   2743   { "Jret{|f}P",	{ Iw }, 0 },
   2744   { "Jret{|f}P",	{ XX }, 0 },
   2745   { "int3",		{ XX }, 0 },
   2746   { "int",		{ Ib }, 0 },
   2747   { X86_64_TABLE (X86_64_CE) },
   2748   { "iret%LP",		{ XX }, 0 },
   2749   /* d0 */
   2750   { REG_TABLE (REG_D0) },
   2751   { REG_TABLE (REG_D1) },
   2752   { REG_TABLE (REG_D2) },
   2753   { REG_TABLE (REG_D3) },
   2754   { X86_64_TABLE (X86_64_D4) },
   2755   { X86_64_TABLE (X86_64_D5) },
   2756   { Bad_Opcode },
   2757   { "xlat",		{ DSBX }, 0 },
   2758   /* d8 */
   2759   { FLOAT },
   2760   { FLOAT },
   2761   { FLOAT },
   2762   { FLOAT },
   2763   { FLOAT },
   2764   { FLOAT },
   2765   { FLOAT },
   2766   { FLOAT },
   2767   /* e0 */
   2768   { "loopneFH",		{ Jb, XX, loop_jcxz_flag }, 0 },
   2769   { "loopeFH",		{ Jb, XX, loop_jcxz_flag }, 0 },
   2770   { "loopFH",		{ Jb, XX, loop_jcxz_flag }, 0 },
   2771   { "jEcxzH",		{ Jb, XX, loop_jcxz_flag }, 0 },
   2772   { "inB",		{ AL, Ib }, 0 },
   2773   { "inG",		{ zAX, Ib }, 0 },
   2774   { "outB",		{ Ib, AL }, 0 },
   2775   { "outG",		{ Ib, zAX }, 0 },
   2776   /* e8 */
   2777   { X86_64_TABLE (X86_64_E8) },
   2778   { X86_64_TABLE (X86_64_E9) },
   2779   { X86_64_TABLE (X86_64_EA) },
   2780   { "jmp",		{ Jb, BND }, 0 },
   2781   { "inB",		{ AL, indirDX }, 0 },
   2782   { "inG",		{ zAX, indirDX }, 0 },
   2783   { "outB",		{ indirDX, AL }, 0 },
   2784   { "outG",		{ indirDX, zAX }, 0 },
   2785   /* f0 */
   2786   { Bad_Opcode },	/* lock prefix */
   2787   { "icebp",		{ XX }, 0 },
   2788   { Bad_Opcode },	/* repne */
   2789   { Bad_Opcode },	/* repz */
   2790   { "hlt",		{ XX }, 0 },
   2791   { "cmc",		{ XX }, 0 },
   2792   { REG_TABLE (REG_F6) },
   2793   { REG_TABLE (REG_F7) },
   2794   /* f8 */
   2795   { "clc",		{ XX }, 0 },
   2796   { "stc",		{ XX }, 0 },
   2797   { "cli",		{ XX }, 0 },
   2798   { "sti",		{ XX }, 0 },
   2799   { "cld",		{ XX }, 0 },
   2800   { "std",		{ XX }, 0 },
   2801   { REG_TABLE (REG_FE) },
   2802   { REG_TABLE (REG_FF) },
   2803 };
   2804 
   2805 static const struct dis386 dis386_twobyte[] = {
   2806   /* 00 */
   2807   { REG_TABLE (REG_0F00 ) },
   2808   { REG_TABLE (REG_0F01 ) },
   2809   { "larS",		{ Gv, Ew }, 0 },
   2810   { "lslS",		{ Gv, Ew }, 0 },
   2811   { Bad_Opcode },
   2812   { "syscall",		{ XX }, 0 },
   2813   { "clts",		{ XX }, 0 },
   2814   { "sysret%LP",		{ XX }, 0 },
   2815   /* 08 */
   2816   { "invd",		{ XX }, 0 },
   2817   { "wbinvd",		{ XX }, 0 },
   2818   { Bad_Opcode },
   2819   { "ud2",		{ XX }, 0 },
   2820   { Bad_Opcode },
   2821   { REG_TABLE (REG_0F0D) },
   2822   { "femms",		{ XX }, 0 },
   2823   { "",			{ MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix.  */
   2824   /* 10 */
   2825   { PREFIX_TABLE (PREFIX_0F10) },
   2826   { PREFIX_TABLE (PREFIX_0F11) },
   2827   { PREFIX_TABLE (PREFIX_0F12) },
   2828   { MOD_TABLE (MOD_0F13) },
   2829   { "unpcklpX",		{ XM, EXx }, PREFIX_OPCODE },
   2830   { "unpckhpX",		{ XM, EXx }, PREFIX_OPCODE },
   2831   { PREFIX_TABLE (PREFIX_0F16) },
   2832   { MOD_TABLE (MOD_0F17) },
   2833   /* 18 */
   2834   { REG_TABLE (REG_0F18) },
   2835   { "nopQ",		{ Ev }, 0 },
   2836   { PREFIX_TABLE (PREFIX_0F1A) },
   2837   { PREFIX_TABLE (PREFIX_0F1B) },
   2838   { "nopQ",		{ Ev }, 0 },
   2839   { "nopQ",		{ Ev }, 0 },
   2840   { "nopQ",		{ Ev }, 0 },
   2841   { "nopQ",		{ Ev }, 0 },
   2842   /* 20 */
   2843   { "movZ",		{ Rm, Cm }, 0 },
   2844   { "movZ",		{ Rm, Dm }, 0 },
   2845   { "movZ",		{ Cm, Rm }, 0 },
   2846   { "movZ",		{ Dm, Rm }, 0 },
   2847   { MOD_TABLE (MOD_0F24) },
   2848   { Bad_Opcode },
   2849   { MOD_TABLE (MOD_0F26) },
   2850   { Bad_Opcode },
   2851   /* 28 */
   2852   { "movapX",		{ XM, EXx }, PREFIX_OPCODE },
   2853   { "movapX",		{ EXxS, XM }, PREFIX_OPCODE },
   2854   { PREFIX_TABLE (PREFIX_0F2A) },
   2855   { PREFIX_TABLE (PREFIX_0F2B) },
   2856   { PREFIX_TABLE (PREFIX_0F2C) },
   2857   { PREFIX_TABLE (PREFIX_0F2D) },
   2858   { PREFIX_TABLE (PREFIX_0F2E) },
   2859   { PREFIX_TABLE (PREFIX_0F2F) },
   2860   /* 30 */
   2861   { "wrmsr",		{ XX }, 0 },
   2862   { "rdtsc",		{ XX }, 0 },
   2863   { "rdmsr",		{ XX }, 0 },
   2864   { "rdpmc",		{ XX }, 0 },
   2865   { "sysenter",		{ XX }, 0 },
   2866   { "sysexit",		{ XX }, 0 },
   2867   { Bad_Opcode },
   2868   { "getsec",		{ XX }, 0 },
   2869   /* 38 */
   2870   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) },
   2871   { Bad_Opcode },
   2872   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) },
   2873   { Bad_Opcode },
   2874   { Bad_Opcode },
   2875   { Bad_Opcode },
   2876   { Bad_Opcode },
   2877   { Bad_Opcode },
   2878   /* 40 */
   2879   { "cmovoS",		{ Gv, Ev }, 0 },
   2880   { "cmovnoS",		{ Gv, Ev }, 0 },
   2881   { "cmovbS",		{ Gv, Ev }, 0 },
   2882   { "cmovaeS",		{ Gv, Ev }, 0 },
   2883   { "cmoveS",		{ Gv, Ev }, 0 },
   2884   { "cmovneS",		{ Gv, Ev }, 0 },
   2885   { "cmovbeS",		{ Gv, Ev }, 0 },
   2886   { "cmovaS",		{ Gv, Ev }, 0 },
   2887   /* 48 */
   2888   { "cmovsS",		{ Gv, Ev }, 0 },
   2889   { "cmovnsS",		{ Gv, Ev }, 0 },
   2890   { "cmovpS",		{ Gv, Ev }, 0 },
   2891   { "cmovnpS",		{ Gv, Ev }, 0 },
   2892   { "cmovlS",		{ Gv, Ev }, 0 },
   2893   { "cmovgeS",		{ Gv, Ev }, 0 },
   2894   { "cmovleS",		{ Gv, Ev }, 0 },
   2895   { "cmovgS",		{ Gv, Ev }, 0 },
   2896   /* 50 */
   2897   { MOD_TABLE (MOD_0F51) },
   2898   { PREFIX_TABLE (PREFIX_0F51) },
   2899   { PREFIX_TABLE (PREFIX_0F52) },
   2900   { PREFIX_TABLE (PREFIX_0F53) },
   2901   { "andpX",		{ XM, EXx }, PREFIX_OPCODE },
   2902   { "andnpX",		{ XM, EXx }, PREFIX_OPCODE },
   2903   { "orpX",		{ XM, EXx }, PREFIX_OPCODE },
   2904   { "xorpX",		{ XM, EXx }, PREFIX_OPCODE },
   2905   /* 58 */
   2906   { PREFIX_TABLE (PREFIX_0F58) },
   2907   { PREFIX_TABLE (PREFIX_0F59) },
   2908   { PREFIX_TABLE (PREFIX_0F5A) },
   2909   { PREFIX_TABLE (PREFIX_0F5B) },
   2910   { PREFIX_TABLE (PREFIX_0F5C) },
   2911   { PREFIX_TABLE (PREFIX_0F5D) },
   2912   { PREFIX_TABLE (PREFIX_0F5E) },
   2913   { PREFIX_TABLE (PREFIX_0F5F) },
   2914   /* 60 */
   2915   { PREFIX_TABLE (PREFIX_0F60) },
   2916   { PREFIX_TABLE (PREFIX_0F61) },
   2917   { PREFIX_TABLE (PREFIX_0F62) },
   2918   { "packsswb",		{ MX, EM }, PREFIX_OPCODE },
   2919   { "pcmpgtb",		{ MX, EM }, PREFIX_OPCODE },
   2920   { "pcmpgtw",		{ MX, EM }, PREFIX_OPCODE },
   2921   { "pcmpgtd",		{ MX, EM }, PREFIX_OPCODE },
   2922   { "packuswb",		{ MX, EM }, PREFIX_OPCODE },
   2923   /* 68 */
   2924   { "punpckhbw",	{ MX, EM }, PREFIX_OPCODE },
   2925   { "punpckhwd",	{ MX, EM }, PREFIX_OPCODE },
   2926   { "punpckhdq",	{ MX, EM }, PREFIX_OPCODE },
   2927   { "packssdw",		{ MX, EM }, PREFIX_OPCODE },
   2928   { PREFIX_TABLE (PREFIX_0F6C) },
   2929   { PREFIX_TABLE (PREFIX_0F6D) },
   2930   { "movK",		{ MX, Edq }, PREFIX_OPCODE },
   2931   { PREFIX_TABLE (PREFIX_0F6F) },
   2932   /* 70 */
   2933   { PREFIX_TABLE (PREFIX_0F70) },
   2934   { REG_TABLE (REG_0F71) },
   2935   { REG_TABLE (REG_0F72) },
   2936   { REG_TABLE (REG_0F73) },
   2937   { "pcmpeqb",		{ MX, EM }, PREFIX_OPCODE },
   2938   { "pcmpeqw",		{ MX, EM }, PREFIX_OPCODE },
   2939   { "pcmpeqd",		{ MX, EM }, PREFIX_OPCODE },
   2940   { "emms",		{ XX }, PREFIX_OPCODE },
   2941   /* 78 */
   2942   { PREFIX_TABLE (PREFIX_0F78) },
   2943   { PREFIX_TABLE (PREFIX_0F79) },
   2944   { THREE_BYTE_TABLE (THREE_BYTE_0F7A) },
   2945   { Bad_Opcode },
   2946   { PREFIX_TABLE (PREFIX_0F7C) },
   2947   { PREFIX_TABLE (PREFIX_0F7D) },
   2948   { PREFIX_TABLE (PREFIX_0F7E) },
   2949   { PREFIX_TABLE (PREFIX_0F7F) },
   2950   /* 80 */
   2951   { "joH",		{ Jv, BND, cond_jump_flag }, 0 },
   2952   { "jnoH",		{ Jv, BND, cond_jump_flag }, 0 },
   2953   { "jbH",		{ Jv, BND, cond_jump_flag }, 0 },
   2954   { "jaeH",		{ Jv, BND, cond_jump_flag }, 0 },
   2955   { "jeH",		{ Jv, BND, cond_jump_flag }, 0 },
   2956   { "jneH",		{ Jv, BND, cond_jump_flag }, 0 },
   2957   { "jbeH",		{ Jv, BND, cond_jump_flag }, 0 },
   2958   { "jaH",		{ Jv, BND, cond_jump_flag }, 0 },
   2959   /* 88 */
   2960   { "jsH",		{ Jv, BND, cond_jump_flag }, 0 },
   2961   { "jnsH",		{ Jv, BND, cond_jump_flag }, 0 },
   2962   { "jpH",		{ Jv, BND, cond_jump_flag }, 0 },
   2963   { "jnpH",		{ Jv, BND, cond_jump_flag }, 0 },
   2964   { "jlH",		{ Jv, BND, cond_jump_flag }, 0 },
   2965   { "jgeH",		{ Jv, BND, cond_jump_flag }, 0 },
   2966   { "jleH",		{ Jv, BND, cond_jump_flag }, 0 },
   2967   { "jgH",		{ Jv, BND, cond_jump_flag }, 0 },
   2968   /* 90 */
   2969   { "seto",		{ Eb }, 0 },
   2970   { "setno",		{ Eb }, 0 },
   2971   { "setb",		{ Eb }, 0 },
   2972   { "setae",		{ Eb }, 0 },
   2973   { "sete",		{ Eb }, 0 },
   2974   { "setne",		{ Eb }, 0 },
   2975   { "setbe",		{ Eb }, 0 },
   2976   { "seta",		{ Eb }, 0 },
   2977   /* 98 */
   2978   { "sets",		{ Eb }, 0 },
   2979   { "setns",		{ Eb }, 0 },
   2980   { "setp",		{ Eb }, 0 },
   2981   { "setnp",		{ Eb }, 0 },
   2982   { "setl",		{ Eb }, 0 },
   2983   { "setge",		{ Eb }, 0 },
   2984   { "setle",		{ Eb }, 0 },
   2985   { "setg",		{ Eb }, 0 },
   2986   /* a0 */
   2987   { "pushT",		{ fs }, 0 },
   2988   { "popT",		{ fs }, 0 },
   2989   { "cpuid",		{ XX }, 0 },
   2990   { "btS",		{ Ev, Gv }, 0 },
   2991   { "shldS",		{ Ev, Gv, Ib }, 0 },
   2992   { "shldS",		{ Ev, Gv, CL }, 0 },
   2993   { REG_TABLE (REG_0FA6) },
   2994   { REG_TABLE (REG_0FA7) },
   2995   /* a8 */
   2996   { "pushT",		{ gs }, 0 },
   2997   { "popT",		{ gs }, 0 },
   2998   { "rsm",		{ XX }, 0 },
   2999   { "btsS",		{ Evh1, Gv }, 0 },
   3000   { "shrdS",		{ Ev, Gv, Ib }, 0 },
   3001   { "shrdS",		{ Ev, Gv, CL }, 0 },
   3002   { REG_TABLE (REG_0FAE) },
   3003   { "imulS",		{ Gv, Ev }, 0 },
   3004   /* b0 */
   3005   { "cmpxchgB",		{ Ebh1, Gb }, 0 },
   3006   { "cmpxchgS",		{ Evh1, Gv }, 0 },
   3007   { MOD_TABLE (MOD_0FB2) },
   3008   { "btrS",		{ Evh1, Gv }, 0 },
   3009   { MOD_TABLE (MOD_0FB4) },
   3010   { MOD_TABLE (MOD_0FB5) },
   3011   { "movz{bR|x}",	{ Gv, Eb }, 0 },
   3012   { "movz{wR|x}",	{ Gv, Ew }, 0 }, /* yes, there really is movzww ! */
   3013   /* b8 */
   3014   { PREFIX_TABLE (PREFIX_0FB8) },
   3015   { "ud1",		{ XX }, 0 },
   3016   { REG_TABLE (REG_0FBA) },
   3017   { "btcS",		{ Evh1, Gv }, 0 },
   3018   { PREFIX_TABLE (PREFIX_0FBC) },
   3019   { PREFIX_TABLE (PREFIX_0FBD) },
   3020   { "movs{bR|x}",	{ Gv, Eb }, 0 },
   3021   { "movs{wR|x}",	{ Gv, Ew }, 0 }, /* yes, there really is movsww ! */
   3022   /* c0 */
   3023   { "xaddB",		{ Ebh1, Gb }, 0 },
   3024   { "xaddS",		{ Evh1, Gv }, 0 },
   3025   { PREFIX_TABLE (PREFIX_0FC2) },
   3026   { MOD_TABLE (MOD_0FC3) },
   3027   { "pinsrw",		{ MX, Edqw, Ib }, PREFIX_OPCODE },
   3028   { "pextrw",		{ Gdq, MS, Ib }, PREFIX_OPCODE },
   3029   { "shufpX",		{ XM, EXx, Ib }, PREFIX_OPCODE },
   3030   { REG_TABLE (REG_0FC7) },
   3031   /* c8 */
   3032   { "bswap",		{ RMeAX }, 0 },
   3033   { "bswap",		{ RMeCX }, 0 },
   3034   { "bswap",		{ RMeDX }, 0 },
   3035   { "bswap",		{ RMeBX }, 0 },
   3036   { "bswap",		{ RMeSP }, 0 },
   3037   { "bswap",		{ RMeBP }, 0 },
   3038   { "bswap",		{ RMeSI }, 0 },
   3039   { "bswap",		{ RMeDI }, 0 },
   3040   /* d0 */
   3041   { PREFIX_TABLE (PREFIX_0FD0) },
   3042   { "psrlw",		{ MX, EM }, PREFIX_OPCODE },
   3043   { "psrld",		{ MX, EM }, PREFIX_OPCODE },
   3044   { "psrlq",		{ MX, EM }, PREFIX_OPCODE },
   3045   { "paddq",		{ MX, EM }, PREFIX_OPCODE },
   3046   { "pmullw",		{ MX, EM }, PREFIX_OPCODE },
   3047   { PREFIX_TABLE (PREFIX_0FD6) },
   3048   { MOD_TABLE (MOD_0FD7) },
   3049   /* d8 */
   3050   { "psubusb",		{ MX, EM }, PREFIX_OPCODE },
   3051   { "psubusw",		{ MX, EM }, PREFIX_OPCODE },
   3052   { "pminub",		{ MX, EM }, PREFIX_OPCODE },
   3053   { "pand",		{ MX, EM }, PREFIX_OPCODE },
   3054   { "paddusb",		{ MX, EM }, PREFIX_OPCODE },
   3055   { "paddusw",		{ MX, EM }, PREFIX_OPCODE },
   3056   { "pmaxub",		{ MX, EM }, PREFIX_OPCODE },
   3057   { "pandn",		{ MX, EM }, PREFIX_OPCODE },
   3058   /* e0 */
   3059   { "pavgb",		{ MX, EM }, PREFIX_OPCODE },
   3060   { "psraw",		{ MX, EM }, PREFIX_OPCODE },
   3061   { "psrad",		{ MX, EM }, PREFIX_OPCODE },
   3062   { "pavgw",		{ MX, EM }, PREFIX_OPCODE },
   3063   { "pmulhuw",		{ MX, EM }, PREFIX_OPCODE },
   3064   { "pmulhw",		{ MX, EM }, PREFIX_OPCODE },
   3065   { PREFIX_TABLE (PREFIX_0FE6) },
   3066   { PREFIX_TABLE (PREFIX_0FE7) },
   3067   /* e8 */
   3068   { "psubsb",		{ MX, EM }, PREFIX_OPCODE },
   3069   { "psubsw",		{ MX, EM }, PREFIX_OPCODE },
   3070   { "pminsw",		{ MX, EM }, PREFIX_OPCODE },
   3071   { "por",		{ MX, EM }, PREFIX_OPCODE },
   3072   { "paddsb",		{ MX, EM }, PREFIX_OPCODE },
   3073   { "paddsw",		{ MX, EM }, PREFIX_OPCODE },
   3074   { "pmaxsw",		{ MX, EM }, PREFIX_OPCODE },
   3075   { "pxor",		{ MX, EM }, PREFIX_OPCODE },
   3076   /* f0 */
   3077   { PREFIX_TABLE (PREFIX_0FF0) },
   3078   { "psllw",		{ MX, EM }, PREFIX_OPCODE },
   3079   { "pslld",		{ MX, EM }, PREFIX_OPCODE },
   3080   { "psllq",		{ MX, EM }, PREFIX_OPCODE },
   3081   { "pmuludq",		{ MX, EM }, PREFIX_OPCODE },
   3082   { "pmaddwd",		{ MX, EM }, PREFIX_OPCODE },
   3083   { "psadbw",		{ MX, EM }, PREFIX_OPCODE },
   3084   { PREFIX_TABLE (PREFIX_0FF7) },
   3085   /* f8 */
   3086   { "psubb",		{ MX, EM }, PREFIX_OPCODE },
   3087   { "psubw",		{ MX, EM }, PREFIX_OPCODE },
   3088   { "psubd",		{ MX, EM }, PREFIX_OPCODE },
   3089   { "psubq",		{ MX, EM }, PREFIX_OPCODE },
   3090   { "paddb",		{ MX, EM }, PREFIX_OPCODE },
   3091   { "paddw",		{ MX, EM }, PREFIX_OPCODE },
   3092   { "paddd",		{ MX, EM }, PREFIX_OPCODE },
   3093   { Bad_Opcode },
   3094 };
   3095 
   3096 static const unsigned char onebyte_has_modrm[256] = {
   3097   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
   3098   /*       -------------------------------        */
   3099   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
   3100   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
   3101   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
   3102   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
   3103   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
   3104   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
   3105   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
   3106   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
   3107   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
   3108   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
   3109   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
   3110   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
   3111   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
   3112   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
   3113   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
   3114   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
   3115   /*       -------------------------------        */
   3116   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
   3117 };
   3118 
   3119 static const unsigned char twobyte_has_modrm[256] = {
   3120   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
   3121   /*       -------------------------------        */
   3122   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
   3123   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
   3124   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
   3125   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
   3126   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
   3127   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
   3128   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
   3129   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
   3130   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
   3131   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
   3132   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
   3133   /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
   3134   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
   3135   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
   3136   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
   3137   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0  /* ff */
   3138   /*       -------------------------------        */
   3139   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
   3140 };
   3141 
   3142 static char obuf[100];
   3143 static char *obufp;
   3144 static char *mnemonicendp;
   3145 static char scratchbuf[100];
   3146 static unsigned char *start_codep;
   3147 static unsigned char *insn_codep;
   3148 static unsigned char *codep;
   3149 static unsigned char *end_codep;
   3150 static int last_lock_prefix;
   3151 static int last_repz_prefix;
   3152 static int last_repnz_prefix;
   3153 static int last_data_prefix;
   3154 static int last_addr_prefix;
   3155 static int last_rex_prefix;
   3156 static int last_seg_prefix;
   3157 static int fwait_prefix;
   3158 /* The active segment register prefix.  */
   3159 static int active_seg_prefix;
   3160 #define MAX_CODE_LENGTH 15
   3161 /* We can up to 14 prefixes since the maximum instruction length is
   3162    15bytes.  */
   3163 static int all_prefixes[MAX_CODE_LENGTH - 1];
   3164 static disassemble_info *the_info;
   3165 static struct
   3166   {
   3167     int mod;
   3168     int reg;
   3169     int rm;
   3170   }
   3171 modrm;
   3172 static unsigned char need_modrm;
   3173 static struct
   3174   {
   3175     int scale;
   3176     int index;
   3177     int base;
   3178   }
   3179 sib;
   3180 static struct
   3181   {
   3182     int register_specifier;
   3183     int length;
   3184     int prefix;
   3185     int w;
   3186     int evex;
   3187     int r;
   3188     int v;
   3189     int mask_register_specifier;
   3190     int zeroing;
   3191     int ll;
   3192     int b;
   3193   }
   3194 vex;
   3195 static unsigned char need_vex;
   3196 static unsigned char need_vex_reg;
   3197 static unsigned char vex_w_done;
   3198 
   3199 struct op
   3200   {
   3201     const char *name;
   3202     unsigned int len;
   3203   };
   3204 
   3205 /* If we are accessing mod/rm/reg without need_modrm set, then the
   3206    values are stale.  Hitting this abort likely indicates that you
   3207    need to update onebyte_has_modrm or twobyte_has_modrm.  */
   3208 #define MODRM_CHECK  if (!need_modrm) abort ()
   3209 
   3210 static const char **names64;
   3211 static const char **names32;
   3212 static const char **names16;
   3213 static const char **names8;
   3214 static const char **names8rex;
   3215 static const char **names_seg;
   3216 static const char *index64;
   3217 static const char *index32;
   3218 static const char **index16;
   3219 static const char **names_bnd;
   3220 
   3221 static const char *intel_names64[] = {
   3222   "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
   3223   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
   3224 };
   3225 static const char *intel_names32[] = {
   3226   "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
   3227   "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
   3228 };
   3229 static const char *intel_names16[] = {
   3230   "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
   3231   "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
   3232 };
   3233 static const char *intel_names8[] = {
   3234   "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
   3235 };
   3236 static const char *intel_names8rex[] = {
   3237   "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
   3238   "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
   3239 };
   3240 static const char *intel_names_seg[] = {
   3241   "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
   3242 };
   3243 static const char *intel_index64 = "riz";
   3244 static const char *intel_index32 = "eiz";
   3245 static const char *intel_index16[] = {
   3246   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
   3247 };
   3248 
   3249 static const char *att_names64[] = {
   3250   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
   3251   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
   3252 };
   3253 static const char *att_names32[] = {
   3254   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
   3255   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
   3256 };
   3257 static const char *att_names16[] = {
   3258   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
   3259   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
   3260 };
   3261 static const char *att_names8[] = {
   3262   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
   3263 };
   3264 static const char *att_names8rex[] = {
   3265   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
   3266   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
   3267 };
   3268 static const char *att_names_seg[] = {
   3269   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
   3270 };
   3271 static const char *att_index64 = "%riz";
   3272 static const char *att_index32 = "%eiz";
   3273 static const char *att_index16[] = {
   3274   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
   3275 };
   3276 
   3277 static const char **names_mm;
   3278 static const char *intel_names_mm[] = {
   3279   "mm0", "mm1", "mm2", "mm3",
   3280   "mm4", "mm5", "mm6", "mm7"
   3281 };
   3282 static const char *att_names_mm[] = {
   3283   "%mm0", "%mm1", "%mm2", "%mm3",
   3284   "%mm4", "%mm5", "%mm6", "%mm7"
   3285 };
   3286 
   3287 static const char *intel_names_bnd[] = {
   3288   "bnd0", "bnd1", "bnd2", "bnd3"
   3289 };
   3290 
   3291 static const char *att_names_bnd[] = {
   3292   "%bnd0", "%bnd1", "%bnd2", "%bnd3"
   3293 };
   3294 
   3295 static const char **names_xmm;
   3296 static const char *intel_names_xmm[] = {
   3297   "xmm0", "xmm1", "xmm2", "xmm3",
   3298   "xmm4", "xmm5", "xmm6", "xmm7",
   3299   "xmm8", "xmm9", "xmm10", "xmm11",
   3300   "xmm12", "xmm13", "xmm14", "xmm15",
   3301   "xmm16", "xmm17", "xmm18", "xmm19",
   3302   "xmm20", "xmm21", "xmm22", "xmm23",
   3303   "xmm24", "xmm25", "xmm26", "xmm27",
   3304   "xmm28", "xmm29", "xmm30", "xmm31"
   3305 };
   3306 static const char *att_names_xmm[] = {
   3307   "%xmm0", "%xmm1", "%xmm2", "%xmm3",
   3308   "%xmm4", "%xmm5", "%xmm6", "%xmm7",
   3309   "%xmm8", "%xmm9", "%xmm10", "%xmm11",
   3310   "%xmm12", "%xmm13", "%xmm14", "%xmm15",
   3311   "%xmm16", "%xmm17", "%xmm18", "%xmm19",
   3312   "%xmm20", "%xmm21", "%xmm22", "%xmm23",
   3313   "%xmm24", "%xmm25", "%xmm26", "%xmm27",
   3314   "%xmm28", "%xmm29", "%xmm30", "%xmm31"
   3315 };
   3316 
   3317 static const char **names_ymm;
   3318 static const char *intel_names_ymm[] = {
   3319   "ymm0", "ymm1", "ymm2", "ymm3",
   3320   "ymm4", "ymm5", "ymm6", "ymm7",
   3321   "ymm8", "ymm9", "ymm10", "ymm11",
   3322   "ymm12", "ymm13", "ymm14", "ymm15",
   3323   "ymm16", "ymm17", "ymm18", "ymm19",
   3324   "ymm20", "ymm21", "ymm22", "ymm23",
   3325   "ymm24", "ymm25", "ymm26", "ymm27",
   3326   "ymm28", "ymm29", "ymm30", "ymm31"
   3327 };
   3328 static const char *att_names_ymm[] = {
   3329   "%ymm0", "%ymm1", "%ymm2", "%ymm3",
   3330   "%ymm4", "%ymm5", "%ymm6", "%ymm7",
   3331   "%ymm8", "%ymm9", "%ymm10", "%ymm11",
   3332   "%ymm12", "%ymm13", "%ymm14", "%ymm15",
   3333   "%ymm16", "%ymm17", "%ymm18", "%ymm19",
   3334   "%ymm20", "%ymm21", "%ymm22", "%ymm23",
   3335   "%ymm24", "%ymm25", "%ymm26", "%ymm27",
   3336   "%ymm28", "%ymm29", "%ymm30", "%ymm31"
   3337 };
   3338 
   3339 static const char **names_zmm;
   3340 static const char *intel_names_zmm[] = {
   3341   "zmm0", "zmm1", "zmm2", "zmm3",
   3342   "zmm4", "zmm5", "zmm6", "zmm7",
   3343   "zmm8", "zmm9", "zmm10", "zmm11",
   3344   "zmm12", "zmm13", "zmm14", "zmm15",
   3345   "zmm16", "zmm17", "zmm18", "zmm19",
   3346   "zmm20", "zmm21", "zmm22", "zmm23",
   3347   "zmm24", "zmm25", "zmm26", "zmm27",
   3348   "zmm28", "zmm29", "zmm30", "zmm31"
   3349 };
   3350 static const char *att_names_zmm[] = {
   3351   "%zmm0", "%zmm1", "%zmm2", "%zmm3",
   3352   "%zmm4", "%zmm5", "%zmm6", "%zmm7",
   3353   "%zmm8", "%zmm9", "%zmm10", "%zmm11",
   3354   "%zmm12", "%zmm13", "%zmm14", "%zmm15",
   3355   "%zmm16", "%zmm17", "%zmm18", "%zmm19",
   3356   "%zmm20", "%zmm21", "%zmm22", "%zmm23",
   3357   "%zmm24", "%zmm25", "%zmm26", "%zmm27",
   3358   "%zmm28", "%zmm29", "%zmm30", "%zmm31"
   3359 };
   3360 
   3361 static const char **names_mask;
   3362 static const char *intel_names_mask[] = {
   3363   "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
   3364 };
   3365 static const char *att_names_mask[] = {
   3366   "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
   3367 };
   3368 
   3369 static const char *names_rounding[] =
   3370 {
   3371   "{rn-sae}",
   3372   "{rd-sae}",
   3373   "{ru-sae}",
   3374   "{rz-sae}"
   3375 };
   3376 
   3377 static const struct dis386 reg_table[][8] = {
   3378   /* REG_80 */
   3379   {
   3380     { "addA",	{ Ebh1, Ib }, 0 },
   3381     { "orA",	{ Ebh1, Ib }, 0 },
   3382     { "adcA",	{ Ebh1, Ib }, 0 },
   3383     { "sbbA",	{ Ebh1, Ib }, 0 },
   3384     { "andA",	{ Ebh1, Ib }, 0 },
   3385     { "subA",	{ Ebh1, Ib }, 0 },
   3386     { "xorA",	{ Ebh1, Ib }, 0 },
   3387     { "cmpA",	{ Eb, Ib }, 0 },
   3388   },
   3389   /* REG_81 */
   3390   {
   3391     { "addQ",	{ Evh1, Iv }, 0 },
   3392     { "orQ",	{ Evh1, Iv }, 0 },
   3393     { "adcQ",	{ Evh1, Iv }, 0 },
   3394     { "sbbQ",	{ Evh1, Iv }, 0 },
   3395     { "andQ",	{ Evh1, Iv }, 0 },
   3396     { "subQ",	{ Evh1, Iv }, 0 },
   3397     { "xorQ",	{ Evh1, Iv }, 0 },
   3398     { "cmpQ",	{ Ev, Iv }, 0 },
   3399   },
   3400   /* REG_82 */
   3401   {
   3402     { "addQ",	{ Evh1, sIb }, 0 },
   3403     { "orQ",	{ Evh1, sIb }, 0 },
   3404     { "adcQ",	{ Evh1, sIb }, 0 },
   3405     { "sbbQ",	{ Evh1, sIb }, 0 },
   3406     { "andQ",	{ Evh1, sIb }, 0 },
   3407     { "subQ",	{ Evh1, sIb }, 0 },
   3408     { "xorQ",	{ Evh1, sIb }, 0 },
   3409     { "cmpQ",	{ Ev, sIb }, 0 },
   3410   },
   3411   /* REG_8F */
   3412   {
   3413     { "popU",	{ stackEv }, 0 },
   3414     { XOP_8F_TABLE (XOP_09) },
   3415     { Bad_Opcode },
   3416     { Bad_Opcode },
   3417     { Bad_Opcode },
   3418     { XOP_8F_TABLE (XOP_09) },
   3419   },
   3420   /* REG_C0 */
   3421   {
   3422     { "rolA",	{ Eb, Ib }, 0 },
   3423     { "rorA",	{ Eb, Ib }, 0 },
   3424     { "rclA",	{ Eb, Ib }, 0 },
   3425     { "rcrA",	{ Eb, Ib }, 0 },
   3426     { "shlA",	{ Eb, Ib }, 0 },
   3427     { "shrA",	{ Eb, Ib }, 0 },
   3428     { Bad_Opcode },
   3429     { "sarA",	{ Eb, Ib }, 0 },
   3430   },
   3431   /* REG_C1 */
   3432   {
   3433     { "rolQ",	{ Ev, Ib }, 0 },
   3434     { "rorQ",	{ Ev, Ib }, 0 },
   3435     { "rclQ",	{ Ev, Ib }, 0 },
   3436     { "rcrQ",	{ Ev, Ib }, 0 },
   3437     { "shlQ",	{ Ev, Ib }, 0 },
   3438     { "shrQ",	{ Ev, Ib }, 0 },
   3439     { Bad_Opcode },
   3440     { "sarQ",	{ Ev, Ib }, 0 },
   3441   },
   3442   /* REG_C6 */
   3443   {
   3444     { "movA",	{ Ebh3, Ib }, 0 },
   3445     { Bad_Opcode },
   3446     { Bad_Opcode },
   3447     { Bad_Opcode },
   3448     { Bad_Opcode },
   3449     { Bad_Opcode },
   3450     { Bad_Opcode },
   3451     { MOD_TABLE (MOD_C6_REG_7) },
   3452   },
   3453   /* REG_C7 */
   3454   {
   3455     { "movQ",	{ Evh3, Iv }, 0 },
   3456     { Bad_Opcode },
   3457     { Bad_Opcode },
   3458     { Bad_Opcode },
   3459     { Bad_Opcode },
   3460     { Bad_Opcode },
   3461     { Bad_Opcode },
   3462     { MOD_TABLE (MOD_C7_REG_7) },
   3463   },
   3464   /* REG_D0 */
   3465   {
   3466     { "rolA",	{ Eb, I1 }, 0 },
   3467     { "rorA",	{ Eb, I1 }, 0 },
   3468     { "rclA",	{ Eb, I1 }, 0 },
   3469     { "rcrA",	{ Eb, I1 }, 0 },
   3470     { "shlA",	{ Eb, I1 }, 0 },
   3471     { "shrA",	{ Eb, I1 }, 0 },
   3472     { Bad_Opcode },
   3473     { "sarA",	{ Eb, I1 }, 0 },
   3474   },
   3475   /* REG_D1 */
   3476   {
   3477     { "rolQ",	{ Ev, I1 }, 0 },
   3478     { "rorQ",	{ Ev, I1 }, 0 },
   3479     { "rclQ",	{ Ev, I1 }, 0 },
   3480     { "rcrQ",	{ Ev, I1 }, 0 },
   3481     { "shlQ",	{ Ev, I1 }, 0 },
   3482     { "shrQ",	{ Ev, I1 }, 0 },
   3483     { Bad_Opcode },
   3484     { "sarQ",	{ Ev, I1 }, 0 },
   3485   },
   3486   /* REG_D2 */
   3487   {
   3488     { "rolA",	{ Eb, CL }, 0 },
   3489     { "rorA",	{ Eb, CL }, 0 },
   3490     { "rclA",	{ Eb, CL }, 0 },
   3491     { "rcrA",	{ Eb, CL }, 0 },
   3492     { "shlA",	{ Eb, CL }, 0 },
   3493     { "shrA",	{ Eb, CL }, 0 },
   3494     { Bad_Opcode },
   3495     { "sarA",	{ Eb, CL }, 0 },
   3496   },
   3497   /* REG_D3 */
   3498   {
   3499     { "rolQ",	{ Ev, CL }, 0 },
   3500     { "rorQ",	{ Ev, CL }, 0 },
   3501     { "rclQ",	{ Ev, CL }, 0 },
   3502     { "rcrQ",	{ Ev, CL }, 0 },
   3503     { "shlQ",	{ Ev, CL }, 0 },
   3504     { "shrQ",	{ Ev, CL }, 0 },
   3505     { Bad_Opcode },
   3506     { "sarQ",	{ Ev, CL }, 0 },
   3507   },
   3508   /* REG_F6 */
   3509   {
   3510     { "testA",	{ Eb, Ib }, 0 },
   3511     { Bad_Opcode },
   3512     { "notA",	{ Ebh1 }, 0 },
   3513     { "negA",	{ Ebh1 }, 0 },
   3514     { "mulA",	{ Eb }, 0 },	/* Don't print the implicit %al register,  */
   3515     { "imulA",	{ Eb }, 0 },	/* to distinguish these opcodes from other */
   3516     { "divA",	{ Eb }, 0 },	/* mul/imul opcodes.  Do the same for div  */
   3517     { "idivA",	{ Eb }, 0 },	/* and idiv for consistency.		   */
   3518   },
   3519   /* REG_F7 */
   3520   {
   3521     { "testQ",	{ Ev, Iv }, 0 },
   3522     { Bad_Opcode },
   3523     { "notQ",	{ Evh1 }, 0 },
   3524     { "negQ",	{ Evh1 }, 0 },
   3525     { "mulQ",	{ Ev }, 0 },	/* Don't print the implicit register.  */
   3526     { "imulQ",	{ Ev }, 0 },
   3527     { "divQ",	{ Ev }, 0 },
   3528     { "idivQ",	{ Ev }, 0 },
   3529   },
   3530   /* REG_FE */
   3531   {
   3532     { "incA",	{ Ebh1 }, 0 },
   3533     { "decA",	{ Ebh1 }, 0 },
   3534   },
   3535   /* REG_FF */
   3536   {
   3537     { "incQ",	{ Evh1 }, 0 },
   3538     { "decQ",	{ Evh1 }, 0 },
   3539     { "call{&|}", { indirEv, BND }, 0 },
   3540     { MOD_TABLE (MOD_FF_REG_3) },
   3541     { "jmp{&|}", { indirEv, BND }, 0 },
   3542     { MOD_TABLE (MOD_FF_REG_5) },
   3543     { "pushU",	{ stackEv }, 0 },
   3544     { Bad_Opcode },
   3545   },
   3546   /* REG_0F00 */
   3547   {
   3548     { "sldtD",	{ Sv }, 0 },
   3549     { "strD",	{ Sv }, 0 },
   3550     { "lldt",	{ Ew }, 0 },
   3551     { "ltr",	{ Ew }, 0 },
   3552     { "verr",	{ Ew }, 0 },
   3553     { "verw",	{ Ew }, 0 },
   3554     { Bad_Opcode },
   3555     { Bad_Opcode },
   3556   },
   3557   /* REG_0F01 */
   3558   {
   3559     { MOD_TABLE (MOD_0F01_REG_0) },
   3560     { MOD_TABLE (MOD_0F01_REG_1) },
   3561     { MOD_TABLE (MOD_0F01_REG_2) },
   3562     { MOD_TABLE (MOD_0F01_REG_3) },
   3563     { "smswD",	{ Sv }, 0 },
   3564     { MOD_TABLE (MOD_0F01_REG_5) },
   3565     { "lmsw",	{ Ew }, 0 },
   3566     { MOD_TABLE (MOD_0F01_REG_7) },
   3567   },
   3568   /* REG_0F0D */
   3569   {
   3570     { "prefetch",	{ Mb }, 0 },
   3571     { "prefetchw",	{ Mb }, 0 },
   3572     { "prefetchwt1",	{ Mb }, 0 },
   3573     { "prefetch",	{ Mb }, 0 },
   3574     { "prefetch",	{ Mb }, 0 },
   3575     { "prefetch",	{ Mb }, 0 },
   3576     { "prefetch",	{ Mb }, 0 },
   3577     { "prefetch",	{ Mb }, 0 },
   3578   },
   3579   /* REG_0F18 */
   3580   {
   3581     { MOD_TABLE (MOD_0F18_REG_0) },
   3582     { MOD_TABLE (MOD_0F18_REG_1) },
   3583     { MOD_TABLE (MOD_0F18_REG_2) },
   3584     { MOD_TABLE (MOD_0F18_REG_3) },
   3585     { MOD_TABLE (MOD_0F18_REG_4) },
   3586     { MOD_TABLE (MOD_0F18_REG_5) },
   3587     { MOD_TABLE (MOD_0F18_REG_6) },
   3588     { MOD_TABLE (MOD_0F18_REG_7) },
   3589   },
   3590   /* REG_0F71 */
   3591   {
   3592     { Bad_Opcode },
   3593     { Bad_Opcode },
   3594     { MOD_TABLE (MOD_0F71_REG_2) },
   3595     { Bad_Opcode },
   3596     { MOD_TABLE (MOD_0F71_REG_4) },
   3597     { Bad_Opcode },
   3598     { MOD_TABLE (MOD_0F71_REG_6) },
   3599   },
   3600   /* REG_0F72 */
   3601   {
   3602     { Bad_Opcode },
   3603     { Bad_Opcode },
   3604     { MOD_TABLE (MOD_0F72_REG_2) },
   3605     { Bad_Opcode },
   3606     { MOD_TABLE (MOD_0F72_REG_4) },
   3607     { Bad_Opcode },
   3608     { MOD_TABLE (MOD_0F72_REG_6) },
   3609   },
   3610   /* REG_0F73 */
   3611   {
   3612     { Bad_Opcode },
   3613     { Bad_Opcode },
   3614     { MOD_TABLE (MOD_0F73_REG_2) },
   3615     { MOD_TABLE (MOD_0F73_REG_3) },
   3616     { Bad_Opcode },
   3617     { Bad_Opcode },
   3618     { MOD_TABLE (MOD_0F73_REG_6) },
   3619     { MOD_TABLE (MOD_0F73_REG_7) },
   3620   },
   3621   /* REG_0FA6 */
   3622   {
   3623     { "montmul",	{ { OP_0f07, 0 } }, 0 },
   3624     { "xsha1",		{ { OP_0f07, 0 } }, 0 },
   3625     { "xsha256",	{ { OP_0f07, 0 } }, 0 },
   3626   },
   3627   /* REG_0FA7 */
   3628   {
   3629     { "xstore-rng",	{ { OP_0f07, 0 } }, 0 },
   3630     { "xcrypt-ecb",	{ { OP_0f07, 0 } }, 0 },
   3631     { "xcrypt-cbc",	{ { OP_0f07, 0 } }, 0 },
   3632     { "xcrypt-ctr",	{ { OP_0f07, 0 } }, 0 },
   3633     { "xcrypt-cfb",	{ { OP_0f07, 0 } }, 0 },
   3634     { "xcrypt-ofb",	{ { OP_0f07, 0 } }, 0 },
   3635   },
   3636   /* REG_0FAE */
   3637   {
   3638     { MOD_TABLE (MOD_0FAE_REG_0) },
   3639     { MOD_TABLE (MOD_0FAE_REG_1) },
   3640     { MOD_TABLE (MOD_0FAE_REG_2) },
   3641     { MOD_TABLE (MOD_0FAE_REG_3) },
   3642     { MOD_TABLE (MOD_0FAE_REG_4) },
   3643     { MOD_TABLE (MOD_0FAE_REG_5) },
   3644     { MOD_TABLE (MOD_0FAE_REG_6) },
   3645     { MOD_TABLE (MOD_0FAE_REG_7) },
   3646   },
   3647   /* REG_0FBA */
   3648   {
   3649     { Bad_Opcode },
   3650     { Bad_Opcode },
   3651     { Bad_Opcode },
   3652     { Bad_Opcode },
   3653     { "btQ",	{ Ev, Ib }, 0 },
   3654     { "btsQ",	{ Evh1, Ib }, 0 },
   3655     { "btrQ",	{ Evh1, Ib }, 0 },
   3656     { "btcQ",	{ Evh1, Ib }, 0 },
   3657   },
   3658   /* REG_0FC7 */
   3659   {
   3660     { Bad_Opcode },
   3661     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 },
   3662     { Bad_Opcode },
   3663     { MOD_TABLE (MOD_0FC7_REG_3) },
   3664     { MOD_TABLE (MOD_0FC7_REG_4) },
   3665     { MOD_TABLE (MOD_0FC7_REG_5) },
   3666     { MOD_TABLE (MOD_0FC7_REG_6) },
   3667     { MOD_TABLE (MOD_0FC7_REG_7) },
   3668   },
   3669   /* REG_VEX_0F71 */
   3670   {
   3671     { Bad_Opcode },
   3672     { Bad_Opcode },
   3673     { MOD_TABLE (MOD_VEX_0F71_REG_2) },
   3674     { Bad_Opcode },
   3675     { MOD_TABLE (MOD_VEX_0F71_REG_4) },
   3676     { Bad_Opcode },
   3677     { MOD_TABLE (MOD_VEX_0F71_REG_6) },
   3678   },
   3679   /* REG_VEX_0F72 */
   3680   {
   3681     { Bad_Opcode },
   3682     { Bad_Opcode },
   3683     { MOD_TABLE (MOD_VEX_0F72_REG_2) },
   3684     { Bad_Opcode },
   3685     { MOD_TABLE (MOD_VEX_0F72_REG_4) },
   3686     { Bad_Opcode },
   3687     { MOD_TABLE (MOD_VEX_0F72_REG_6) },
   3688   },
   3689   /* REG_VEX_0F73 */
   3690   {
   3691     { Bad_Opcode },
   3692     { Bad_Opcode },
   3693     { MOD_TABLE (MOD_VEX_0F73_REG_2) },
   3694     { MOD_TABLE (MOD_VEX_0F73_REG_3) },
   3695     { Bad_Opcode },
   3696     { Bad_Opcode },
   3697     { MOD_TABLE (MOD_VEX_0F73_REG_6) },
   3698     { MOD_TABLE (MOD_VEX_0F73_REG_7) },
   3699   },
   3700   /* REG_VEX_0FAE */
   3701   {
   3702     { Bad_Opcode },
   3703     { Bad_Opcode },
   3704     { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
   3705     { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
   3706   },
   3707   /* REG_VEX_0F38F3 */
   3708   {
   3709     { Bad_Opcode },
   3710     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) },
   3711     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) },
   3712     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) },
   3713   },
   3714   /* REG_XOP_LWPCB */
   3715   {
   3716     { "llwpcb", { { OP_LWPCB_E, 0 } }, 0 },
   3717     { "slwpcb",	{ { OP_LWPCB_E, 0 } }, 0 },
   3718   },
   3719   /* REG_XOP_LWP */
   3720   {
   3721     { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq }, 0 },
   3722     { "lwpval",	{ { OP_LWP_E, 0 }, Ed, Iq }, 0 },
   3723   },
   3724   /* REG_XOP_TBM_01 */
   3725   {
   3726     { Bad_Opcode },
   3727     { "blcfill",	{ { OP_LWP_E, 0 }, Ev }, 0 },
   3728     { "blsfill",	{ { OP_LWP_E, 0 }, Ev }, 0 },
   3729     { "blcs",	{ { OP_LWP_E, 0 }, Ev }, 0 },
   3730     { "tzmsk",	{ { OP_LWP_E, 0 }, Ev }, 0 },
   3731     { "blcic",	{ { OP_LWP_E, 0 }, Ev }, 0 },
   3732     { "blsic",	{ { OP_LWP_E, 0 }, Ev }, 0 },
   3733     { "t1mskc",	{ { OP_LWP_E, 0 }, Ev }, 0 },
   3734   },
   3735   /* REG_XOP_TBM_02 */
   3736   {
   3737     { Bad_Opcode },
   3738     { "blcmsk",	{ { OP_LWP_E, 0 }, Ev }, 0 },
   3739     { Bad_Opcode },
   3740     { Bad_Opcode },
   3741     { Bad_Opcode },
   3742     { Bad_Opcode },
   3743     { "blci",	{ { OP_LWP_E, 0 }, Ev }, 0 },
   3744   },
   3745 #define NEED_REG_TABLE
   3746 #include "i386-dis-evex.h"
   3747 #undef NEED_REG_TABLE
   3748 };
   3749 
   3750 static const struct dis386 prefix_table[][4] = {
   3751   /* PREFIX_90 */
   3752   {
   3753     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
   3754     { "pause", { XX }, 0 },
   3755     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
   3756     { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
   3757   },
   3758 
   3759   /* PREFIX_0F10 */
   3760   {
   3761     { "movups",	{ XM, EXx }, PREFIX_OPCODE },
   3762     { "movss",	{ XM, EXd }, PREFIX_OPCODE },
   3763     { "movupd",	{ XM, EXx }, PREFIX_OPCODE },
   3764     { "movsd",	{ XM, EXq }, PREFIX_OPCODE },
   3765   },
   3766 
   3767   /* PREFIX_0F11 */
   3768   {
   3769     { "movups",	{ EXxS, XM }, PREFIX_OPCODE },
   3770     { "movss",	{ EXdS, XM }, PREFIX_OPCODE },
   3771     { "movupd",	{ EXxS, XM }, PREFIX_OPCODE },
   3772     { "movsd",	{ EXqS, XM }, PREFIX_OPCODE },
   3773   },
   3774 
   3775   /* PREFIX_0F12 */
   3776   {
   3777     { MOD_TABLE (MOD_0F12_PREFIX_0) },
   3778     { "movsldup", { XM, EXx }, PREFIX_OPCODE },
   3779     { "movlpd",	{ XM, EXq }, PREFIX_OPCODE },
   3780     { "movddup", { XM, EXq }, PREFIX_OPCODE },
   3781   },
   3782 
   3783   /* PREFIX_0F16 */
   3784   {
   3785     { MOD_TABLE (MOD_0F16_PREFIX_0) },
   3786     { "movshdup", { XM, EXx }, PREFIX_OPCODE },
   3787     { "movhpd",	{ XM, EXq }, PREFIX_OPCODE },
   3788   },
   3789 
   3790   /* PREFIX_0F1A */
   3791   {
   3792     { MOD_TABLE (MOD_0F1A_PREFIX_0) },
   3793     { "bndcl",  { Gbnd, Ev_bnd }, 0 },
   3794     { "bndmov", { Gbnd, Ebnd }, 0 },
   3795     { "bndcu",  { Gbnd, Ev_bnd }, 0 },
   3796   },
   3797 
   3798   /* PREFIX_0F1B */
   3799   {
   3800     { MOD_TABLE (MOD_0F1B_PREFIX_0) },
   3801     { MOD_TABLE (MOD_0F1B_PREFIX_1) },
   3802     { "bndmov", { Ebnd, Gbnd }, 0 },
   3803     { "bndcn",  { Gbnd, Ev_bnd }, 0 },
   3804   },
   3805 
   3806   /* PREFIX_0F2A */
   3807   {
   3808     { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
   3809     { "cvtsi2ss%LQ", { XM, Ev }, PREFIX_OPCODE },
   3810     { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
   3811     { "cvtsi2sd%LQ", { XM, Ev }, 0 },
   3812   },
   3813 
   3814   /* PREFIX_0F2B */
   3815   {
   3816     { MOD_TABLE (MOD_0F2B_PREFIX_0) },
   3817     { MOD_TABLE (MOD_0F2B_PREFIX_1) },
   3818     { MOD_TABLE (MOD_0F2B_PREFIX_2) },
   3819     { MOD_TABLE (MOD_0F2B_PREFIX_3) },
   3820   },
   3821 
   3822   /* PREFIX_0F2C */
   3823   {
   3824     { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
   3825     { "cvttss2siY", { Gv, EXd }, PREFIX_OPCODE },
   3826     { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
   3827     { "cvttsd2siY", { Gv, EXq }, PREFIX_OPCODE },
   3828   },
   3829 
   3830   /* PREFIX_0F2D */
   3831   {
   3832     { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
   3833     { "cvtss2siY", { Gv, EXd }, PREFIX_OPCODE },
   3834     { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
   3835     { "cvtsd2siY", { Gv, EXq }, PREFIX_OPCODE },
   3836   },
   3837 
   3838   /* PREFIX_0F2E */
   3839   {
   3840     { "ucomiss",{ XM, EXd }, 0 },
   3841     { Bad_Opcode },
   3842     { "ucomisd",{ XM, EXq }, 0 },
   3843   },
   3844 
   3845   /* PREFIX_0F2F */
   3846   {
   3847     { "comiss",	{ XM, EXd }, 0 },
   3848     { Bad_Opcode },
   3849     { "comisd",	{ XM, EXq }, 0 },
   3850   },
   3851 
   3852   /* PREFIX_0F51 */
   3853   {
   3854     { "sqrtps", { XM, EXx }, PREFIX_OPCODE },
   3855     { "sqrtss", { XM, EXd }, PREFIX_OPCODE },
   3856     { "sqrtpd", { XM, EXx }, PREFIX_OPCODE },
   3857     { "sqrtsd",	{ XM, EXq }, PREFIX_OPCODE },
   3858   },
   3859 
   3860   /* PREFIX_0F52 */
   3861   {
   3862     { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE },
   3863     { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE },
   3864   },
   3865 
   3866   /* PREFIX_0F53 */
   3867   {
   3868     { "rcpps",	{ XM, EXx }, PREFIX_OPCODE },
   3869     { "rcpss",	{ XM, EXd }, PREFIX_OPCODE },
   3870   },
   3871 
   3872   /* PREFIX_0F58 */
   3873   {
   3874     { "addps", { XM, EXx }, PREFIX_OPCODE },
   3875     { "addss", { XM, EXd }, PREFIX_OPCODE },
   3876     { "addpd", { XM, EXx }, PREFIX_OPCODE },
   3877     { "addsd", { XM, EXq }, PREFIX_OPCODE },
   3878   },
   3879 
   3880   /* PREFIX_0F59 */
   3881   {
   3882     { "mulps",	{ XM, EXx }, PREFIX_OPCODE },
   3883     { "mulss",	{ XM, EXd }, PREFIX_OPCODE },
   3884     { "mulpd",	{ XM, EXx }, PREFIX_OPCODE },
   3885     { "mulsd",	{ XM, EXq }, PREFIX_OPCODE },
   3886   },
   3887 
   3888   /* PREFIX_0F5A */
   3889   {
   3890     { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE },
   3891     { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE },
   3892     { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE },
   3893     { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE },
   3894   },
   3895 
   3896   /* PREFIX_0F5B */
   3897   {
   3898     { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE },
   3899     { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE },
   3900     { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE },
   3901   },
   3902 
   3903   /* PREFIX_0F5C */
   3904   {
   3905     { "subps",	{ XM, EXx }, PREFIX_OPCODE },
   3906     { "subss",	{ XM, EXd }, PREFIX_OPCODE },
   3907     { "subpd",	{ XM, EXx }, PREFIX_OPCODE },
   3908     { "subsd",	{ XM, EXq }, PREFIX_OPCODE },
   3909   },
   3910 
   3911   /* PREFIX_0F5D */
   3912   {
   3913     { "minps",	{ XM, EXx }, PREFIX_OPCODE },
   3914     { "minss",	{ XM, EXd }, PREFIX_OPCODE },
   3915     { "minpd",	{ XM, EXx }, PREFIX_OPCODE },
   3916     { "minsd",	{ XM, EXq }, PREFIX_OPCODE },
   3917   },
   3918 
   3919   /* PREFIX_0F5E */
   3920   {
   3921     { "divps",	{ XM, EXx }, PREFIX_OPCODE },
   3922     { "divss",	{ XM, EXd }, PREFIX_OPCODE },
   3923     { "divpd",	{ XM, EXx }, PREFIX_OPCODE },
   3924     { "divsd",	{ XM, EXq }, PREFIX_OPCODE },
   3925   },
   3926 
   3927   /* PREFIX_0F5F */
   3928   {
   3929     { "maxps",	{ XM, EXx }, PREFIX_OPCODE },
   3930     { "maxss",	{ XM, EXd }, PREFIX_OPCODE },
   3931     { "maxpd",	{ XM, EXx }, PREFIX_OPCODE },
   3932     { "maxsd",	{ XM, EXq }, PREFIX_OPCODE },
   3933   },
   3934 
   3935   /* PREFIX_0F60 */
   3936   {
   3937     { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE },
   3938     { Bad_Opcode },
   3939     { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE },
   3940   },
   3941 
   3942   /* PREFIX_0F61 */
   3943   {
   3944     { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE },
   3945     { Bad_Opcode },
   3946     { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE },
   3947   },
   3948 
   3949   /* PREFIX_0F62 */
   3950   {
   3951     { "punpckldq",{ MX, EMd }, PREFIX_OPCODE },
   3952     { Bad_Opcode },
   3953     { "punpckldq",{ MX, EMx }, PREFIX_OPCODE },
   3954   },
   3955 
   3956   /* PREFIX_0F6C */
   3957   {
   3958     { Bad_Opcode },
   3959     { Bad_Opcode },
   3960     { "punpcklqdq", { XM, EXx }, PREFIX_OPCODE },
   3961   },
   3962 
   3963   /* PREFIX_0F6D */
   3964   {
   3965     { Bad_Opcode },
   3966     { Bad_Opcode },
   3967     { "punpckhqdq", { XM, EXx }, PREFIX_OPCODE },
   3968   },
   3969 
   3970   /* PREFIX_0F6F */
   3971   {
   3972     { "movq",	{ MX, EM }, PREFIX_OPCODE },
   3973     { "movdqu",	{ XM, EXx }, PREFIX_OPCODE },
   3974     { "movdqa",	{ XM, EXx }, PREFIX_OPCODE },
   3975   },
   3976 
   3977   /* PREFIX_0F70 */
   3978   {
   3979     { "pshufw",	{ MX, EM, Ib }, PREFIX_OPCODE },
   3980     { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE },
   3981     { "pshufd",	{ XM, EXx, Ib }, PREFIX_OPCODE },
   3982     { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE },
   3983   },
   3984 
   3985   /* PREFIX_0F73_REG_3 */
   3986   {
   3987     { Bad_Opcode },
   3988     { Bad_Opcode },
   3989     { "psrldq",	{ XS, Ib }, 0 },
   3990   },
   3991 
   3992   /* PREFIX_0F73_REG_7 */
   3993   {
   3994     { Bad_Opcode },
   3995     { Bad_Opcode },
   3996     { "pslldq",	{ XS, Ib }, 0 },
   3997   },
   3998 
   3999   /* PREFIX_0F78 */
   4000   {
   4001     {"vmread",	{ Em, Gm }, 0 },
   4002     { Bad_Opcode },
   4003     {"extrq",	{ XS, Ib, Ib }, 0 },
   4004     {"insertq",	{ XM, XS, Ib, Ib }, 0 },
   4005   },
   4006 
   4007   /* PREFIX_0F79 */
   4008   {
   4009     {"vmwrite",	{ Gm, Em }, 0 },
   4010     { Bad_Opcode },
   4011     {"extrq",	{ XM, XS }, 0 },
   4012     {"insertq",	{ XM, XS }, 0 },
   4013   },
   4014 
   4015   /* PREFIX_0F7C */
   4016   {
   4017     { Bad_Opcode },
   4018     { Bad_Opcode },
   4019     { "haddpd",	{ XM, EXx }, PREFIX_OPCODE },
   4020     { "haddps",	{ XM, EXx }, PREFIX_OPCODE },
   4021   },
   4022 
   4023   /* PREFIX_0F7D */
   4024   {
   4025     { Bad_Opcode },
   4026     { Bad_Opcode },
   4027     { "hsubpd",	{ XM, EXx }, PREFIX_OPCODE },
   4028     { "hsubps",	{ XM, EXx }, PREFIX_OPCODE },
   4029   },
   4030 
   4031   /* PREFIX_0F7E */
   4032   {
   4033     { "movK",	{ Edq, MX }, PREFIX_OPCODE },
   4034     { "movq",	{ XM, EXq }, PREFIX_OPCODE },
   4035     { "movK",	{ Edq, XM }, PREFIX_OPCODE },
   4036   },
   4037 
   4038   /* PREFIX_0F7F */
   4039   {
   4040     { "movq",	{ EMS, MX }, PREFIX_OPCODE },
   4041     { "movdqu",	{ EXxS, XM }, PREFIX_OPCODE },
   4042     { "movdqa",	{ EXxS, XM }, PREFIX_OPCODE },
   4043   },
   4044 
   4045   /* PREFIX_0FAE_REG_0 */
   4046   {
   4047     { Bad_Opcode },
   4048     { "rdfsbase", { Ev }, 0 },
   4049   },
   4050 
   4051   /* PREFIX_0FAE_REG_1 */
   4052   {
   4053     { Bad_Opcode },
   4054     { "rdgsbase", { Ev }, 0 },
   4055   },
   4056 
   4057   /* PREFIX_0FAE_REG_2 */
   4058   {
   4059     { Bad_Opcode },
   4060     { "wrfsbase", { Ev }, 0 },
   4061   },
   4062 
   4063   /* PREFIX_0FAE_REG_3 */
   4064   {
   4065     { Bad_Opcode },
   4066     { "wrgsbase", { Ev }, 0 },
   4067   },
   4068 
   4069   /* PREFIX_0FAE_REG_6 */
   4070   {
   4071     { "xsaveopt",      { FXSAVE }, 0 },
   4072     { Bad_Opcode },
   4073     { "clwb",	{ Mb }, 0 },
   4074   },
   4075 
   4076   /* PREFIX_0FAE_REG_7 */
   4077   {
   4078     { "clflush",	{ Mb }, 0 },
   4079     { Bad_Opcode },
   4080     { "clflushopt",	{ Mb }, 0 },
   4081   },
   4082 
   4083   /* PREFIX_RM_0_0FAE_REG_7 */
   4084   {
   4085     { "sfence",		{ Skip_MODRM }, 0 },
   4086     { Bad_Opcode },
   4087     { "pcommit",		{ Skip_MODRM }, 0 },
   4088   },
   4089 
   4090   /* PREFIX_0FB8 */
   4091   {
   4092     { Bad_Opcode },
   4093     { "popcntS", { Gv, Ev }, 0 },
   4094   },
   4095 
   4096   /* PREFIX_0FBC */
   4097   {
   4098     { "bsfS",	{ Gv, Ev }, 0 },
   4099     { "tzcntS",	{ Gv, Ev }, 0 },
   4100     { "bsfS",	{ Gv, Ev }, 0 },
   4101   },
   4102 
   4103   /* PREFIX_0FBD */
   4104   {
   4105     { "bsrS",	{ Gv, Ev }, 0 },
   4106     { "lzcntS",	{ Gv, Ev }, 0 },
   4107     { "bsrS",	{ Gv, Ev }, 0 },
   4108   },
   4109 
   4110   /* PREFIX_0FC2 */
   4111   {
   4112     { "cmpps",	{ XM, EXx, CMP }, PREFIX_OPCODE },
   4113     { "cmpss",	{ XM, EXd, CMP }, PREFIX_OPCODE },
   4114     { "cmppd",	{ XM, EXx, CMP }, PREFIX_OPCODE },
   4115     { "cmpsd",	{ XM, EXq, CMP }, PREFIX_OPCODE },
   4116   },
   4117 
   4118   /* PREFIX_MOD_0_0FC3 */
   4119   {
   4120     { "movntiS", { Ev, Gv }, PREFIX_OPCODE },
   4121   },
   4122 
   4123   /* PREFIX_MOD_0_0FC7_REG_6 */
   4124   {
   4125     { "vmptrld",{ Mq }, 0 },
   4126     { "vmxon",	{ Mq }, 0 },
   4127     { "vmclear",{ Mq }, 0 },
   4128   },
   4129 
   4130   /* PREFIX_MOD_3_0FC7_REG_6 */
   4131   {
   4132     { "rdrand",	{ Ev }, 0 },
   4133     { Bad_Opcode },
   4134     { "rdrand",	{ Ev }, 0 }
   4135   },
   4136 
   4137   /* PREFIX_MOD_3_0FC7_REG_7 */
   4138   {
   4139     { "rdseed",	{ Ev }, 0 },
   4140     { "rdpid",	{ Em }, 0 },
   4141     { "rdseed",	{ Ev }, 0 },
   4142   },
   4143 
   4144   /* PREFIX_0FD0 */
   4145   {
   4146     { Bad_Opcode },
   4147     { Bad_Opcode },
   4148     { "addsubpd", { XM, EXx }, 0 },
   4149     { "addsubps", { XM, EXx }, 0 },
   4150   },
   4151 
   4152   /* PREFIX_0FD6 */
   4153   {
   4154     { Bad_Opcode },
   4155     { "movq2dq",{ XM, MS }, 0 },
   4156     { "movq",	{ EXqS, XM }, 0 },
   4157     { "movdq2q",{ MX, XS }, 0 },
   4158   },
   4159 
   4160   /* PREFIX_0FE6 */
   4161   {
   4162     { Bad_Opcode },
   4163     { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE },
   4164     { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE },
   4165     { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE },
   4166   },
   4167 
   4168   /* PREFIX_0FE7 */
   4169   {
   4170     { "movntq",	{ Mq, MX }, PREFIX_OPCODE },
   4171     { Bad_Opcode },
   4172     { MOD_TABLE (MOD_0FE7_PREFIX_2) },
   4173   },
   4174 
   4175   /* PREFIX_0FF0 */
   4176   {
   4177     { Bad_Opcode },
   4178     { Bad_Opcode },
   4179     { Bad_Opcode },
   4180     { MOD_TABLE (MOD_0FF0_PREFIX_3) },
   4181   },
   4182 
   4183   /* PREFIX_0FF7 */
   4184   {
   4185     { "maskmovq", { MX, MS }, PREFIX_OPCODE },
   4186     { Bad_Opcode },
   4187     { "maskmovdqu", { XM, XS }, PREFIX_OPCODE },
   4188   },
   4189 
   4190   /* PREFIX_0F3810 */
   4191   {
   4192     { Bad_Opcode },
   4193     { Bad_Opcode },
   4194     { "pblendvb", { XM, EXx, XMM0 }, PREFIX_OPCODE },
   4195   },
   4196 
   4197   /* PREFIX_0F3814 */
   4198   {
   4199     { Bad_Opcode },
   4200     { Bad_Opcode },
   4201     { "blendvps", { XM, EXx, XMM0 }, PREFIX_OPCODE },
   4202   },
   4203 
   4204   /* PREFIX_0F3815 */
   4205   {
   4206     { Bad_Opcode },
   4207     { Bad_Opcode },
   4208     { "blendvpd", { XM, EXx, XMM0 }, PREFIX_OPCODE },
   4209   },
   4210 
   4211   /* PREFIX_0F3817 */
   4212   {
   4213     { Bad_Opcode },
   4214     { Bad_Opcode },
   4215     { "ptest",  { XM, EXx }, PREFIX_OPCODE },
   4216   },
   4217 
   4218   /* PREFIX_0F3820 */
   4219   {
   4220     { Bad_Opcode },
   4221     { Bad_Opcode },
   4222     { "pmovsxbw", { XM, EXq }, PREFIX_OPCODE },
   4223   },
   4224 
   4225   /* PREFIX_0F3821 */
   4226   {
   4227     { Bad_Opcode },
   4228     { Bad_Opcode },
   4229     { "pmovsxbd", { XM, EXd }, PREFIX_OPCODE },
   4230   },
   4231 
   4232   /* PREFIX_0F3822 */
   4233   {
   4234     { Bad_Opcode },
   4235     { Bad_Opcode },
   4236     { "pmovsxbq", { XM, EXw }, PREFIX_OPCODE },
   4237   },
   4238 
   4239   /* PREFIX_0F3823 */
   4240   {
   4241     { Bad_Opcode },
   4242     { Bad_Opcode },
   4243     { "pmovsxwd", { XM, EXq }, PREFIX_OPCODE },
   4244   },
   4245 
   4246   /* PREFIX_0F3824 */
   4247   {
   4248     { Bad_Opcode },
   4249     { Bad_Opcode },
   4250     { "pmovsxwq", { XM, EXd }, PREFIX_OPCODE },
   4251   },
   4252 
   4253   /* PREFIX_0F3825 */
   4254   {
   4255     { Bad_Opcode },
   4256     { Bad_Opcode },
   4257     { "pmovsxdq", { XM, EXq }, PREFIX_OPCODE },
   4258   },
   4259 
   4260   /* PREFIX_0F3828 */
   4261   {
   4262     { Bad_Opcode },
   4263     { Bad_Opcode },
   4264     { "pmuldq", { XM, EXx }, PREFIX_OPCODE },
   4265   },
   4266 
   4267   /* PREFIX_0F3829 */
   4268   {
   4269     { Bad_Opcode },
   4270     { Bad_Opcode },
   4271     { "pcmpeqq", { XM, EXx }, PREFIX_OPCODE },
   4272   },
   4273 
   4274   /* PREFIX_0F382A */
   4275   {
   4276     { Bad_Opcode },
   4277     { Bad_Opcode },
   4278     { MOD_TABLE (MOD_0F382A_PREFIX_2) },
   4279   },
   4280 
   4281   /* PREFIX_0F382B */
   4282   {
   4283     { Bad_Opcode },
   4284     { Bad_Opcode },
   4285     { "packusdw", { XM, EXx }, PREFIX_OPCODE },
   4286   },
   4287 
   4288   /* PREFIX_0F3830 */
   4289   {
   4290     { Bad_Opcode },
   4291     { Bad_Opcode },
   4292     { "pmovzxbw", { XM, EXq }, PREFIX_OPCODE },
   4293   },
   4294 
   4295   /* PREFIX_0F3831 */
   4296   {
   4297     { Bad_Opcode },
   4298     { Bad_Opcode },
   4299     { "pmovzxbd", { XM, EXd }, PREFIX_OPCODE },
   4300   },
   4301 
   4302   /* PREFIX_0F3832 */
   4303   {
   4304     { Bad_Opcode },
   4305     { Bad_Opcode },
   4306     { "pmovzxbq", { XM, EXw }, PREFIX_OPCODE },
   4307   },
   4308 
   4309   /* PREFIX_0F3833 */
   4310   {
   4311     { Bad_Opcode },
   4312     { Bad_Opcode },
   4313     { "pmovzxwd", { XM, EXq }, PREFIX_OPCODE },
   4314   },
   4315 
   4316   /* PREFIX_0F3834 */
   4317   {
   4318     { Bad_Opcode },
   4319     { Bad_Opcode },
   4320     { "pmovzxwq", { XM, EXd }, PREFIX_OPCODE },
   4321   },
   4322 
   4323   /* PREFIX_0F3835 */
   4324   {
   4325     { Bad_Opcode },
   4326     { Bad_Opcode },
   4327     { "pmovzxdq", { XM, EXq }, PREFIX_OPCODE },
   4328   },
   4329 
   4330   /* PREFIX_0F3837 */
   4331   {
   4332     { Bad_Opcode },
   4333     { Bad_Opcode },
   4334     { "pcmpgtq", { XM, EXx }, PREFIX_OPCODE },
   4335   },
   4336 
   4337   /* PREFIX_0F3838 */
   4338   {
   4339     { Bad_Opcode },
   4340     { Bad_Opcode },
   4341     { "pminsb",	{ XM, EXx }, PREFIX_OPCODE },
   4342   },
   4343 
   4344   /* PREFIX_0F3839 */
   4345   {
   4346     { Bad_Opcode },
   4347     { Bad_Opcode },
   4348     { "pminsd",	{ XM, EXx }, PREFIX_OPCODE },
   4349   },
   4350 
   4351   /* PREFIX_0F383A */
   4352   {
   4353     { Bad_Opcode },
   4354     { Bad_Opcode },
   4355     { "pminuw",	{ XM, EXx }, PREFIX_OPCODE },
   4356   },
   4357 
   4358   /* PREFIX_0F383B */
   4359   {
   4360     { Bad_Opcode },
   4361     { Bad_Opcode },
   4362     { "pminud",	{ XM, EXx }, PREFIX_OPCODE },
   4363   },
   4364 
   4365   /* PREFIX_0F383C */
   4366   {
   4367     { Bad_Opcode },
   4368     { Bad_Opcode },
   4369     { "pmaxsb",	{ XM, EXx }, PREFIX_OPCODE },
   4370   },
   4371 
   4372   /* PREFIX_0F383D */
   4373   {
   4374     { Bad_Opcode },
   4375     { Bad_Opcode },
   4376     { "pmaxsd",	{ XM, EXx }, PREFIX_OPCODE },
   4377   },
   4378 
   4379   /* PREFIX_0F383E */
   4380   {
   4381     { Bad_Opcode },
   4382     { Bad_Opcode },
   4383     { "pmaxuw", { XM, EXx }, PREFIX_OPCODE },
   4384   },
   4385 
   4386   /* PREFIX_0F383F */
   4387   {
   4388     { Bad_Opcode },
   4389     { Bad_Opcode },
   4390     { "pmaxud", { XM, EXx }, PREFIX_OPCODE },
   4391   },
   4392 
   4393   /* PREFIX_0F3840 */
   4394   {
   4395     { Bad_Opcode },
   4396     { Bad_Opcode },
   4397     { "pmulld", { XM, EXx }, PREFIX_OPCODE },
   4398   },
   4399 
   4400   /* PREFIX_0F3841 */
   4401   {
   4402     { Bad_Opcode },
   4403     { Bad_Opcode },
   4404     { "phminposuw", { XM, EXx }, PREFIX_OPCODE },
   4405   },
   4406 
   4407   /* PREFIX_0F3880 */
   4408   {
   4409     { Bad_Opcode },
   4410     { Bad_Opcode },
   4411     { "invept",	{ Gm, Mo }, PREFIX_OPCODE },
   4412   },
   4413 
   4414   /* PREFIX_0F3881 */
   4415   {
   4416     { Bad_Opcode },
   4417     { Bad_Opcode },
   4418     { "invvpid", { Gm, Mo }, PREFIX_OPCODE },
   4419   },
   4420 
   4421   /* PREFIX_0F3882 */
   4422   {
   4423     { Bad_Opcode },
   4424     { Bad_Opcode },
   4425     { "invpcid", { Gm, M }, PREFIX_OPCODE },
   4426   },
   4427 
   4428   /* PREFIX_0F38C8 */
   4429   {
   4430     { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE },
   4431   },
   4432 
   4433   /* PREFIX_0F38C9 */
   4434   {
   4435     { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE },
   4436   },
   4437 
   4438   /* PREFIX_0F38CA */
   4439   {
   4440     { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE },
   4441   },
   4442 
   4443   /* PREFIX_0F38CB */
   4444   {
   4445     { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE },
   4446   },
   4447 
   4448   /* PREFIX_0F38CC */
   4449   {
   4450     { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE },
   4451   },
   4452 
   4453   /* PREFIX_0F38CD */
   4454   {
   4455     { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
   4456   },
   4457 
   4458   /* PREFIX_0F38DB */
   4459   {
   4460     { Bad_Opcode },
   4461     { Bad_Opcode },
   4462     { "aesimc", { XM, EXx }, PREFIX_OPCODE },
   4463   },
   4464 
   4465   /* PREFIX_0F38DC */
   4466   {
   4467     { Bad_Opcode },
   4468     { Bad_Opcode },
   4469     { "aesenc", { XM, EXx }, PREFIX_OPCODE },
   4470   },
   4471 
   4472   /* PREFIX_0F38DD */
   4473   {
   4474     { Bad_Opcode },
   4475     { Bad_Opcode },
   4476     { "aesenclast", { XM, EXx }, PREFIX_OPCODE },
   4477   },
   4478 
   4479   /* PREFIX_0F38DE */
   4480   {
   4481     { Bad_Opcode },
   4482     { Bad_Opcode },
   4483     { "aesdec", { XM, EXx }, PREFIX_OPCODE },
   4484   },
   4485 
   4486   /* PREFIX_0F38DF */
   4487   {
   4488     { Bad_Opcode },
   4489     { Bad_Opcode },
   4490     { "aesdeclast", { XM, EXx }, PREFIX_OPCODE },
   4491   },
   4492 
   4493   /* PREFIX_0F38F0 */
   4494   {
   4495     { "movbeS",	{ Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
   4496     { Bad_Opcode },
   4497     { "movbeS",	{ Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
   4498     { "crc32",	{ Gdq, { CRC32_Fixup, b_mode } }, PREFIX_OPCODE },
   4499   },
   4500 
   4501   /* PREFIX_0F38F1 */
   4502   {
   4503     { "movbeS",	{ { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
   4504     { Bad_Opcode },
   4505     { "movbeS",	{ { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
   4506     { "crc32",	{ Gdq, { CRC32_Fixup, v_mode } }, PREFIX_OPCODE },
   4507   },
   4508 
   4509   /* PREFIX_0F38F6 */
   4510   {
   4511     { Bad_Opcode },
   4512     { "adoxS",	{ Gdq, Edq}, PREFIX_OPCODE },
   4513     { "adcxS",	{ Gdq, Edq}, PREFIX_OPCODE },
   4514     { Bad_Opcode },
   4515   },
   4516 
   4517   /* PREFIX_0F3A08 */
   4518   {
   4519     { Bad_Opcode },
   4520     { Bad_Opcode },
   4521     { "roundps", { XM, EXx, Ib }, PREFIX_OPCODE },
   4522   },
   4523 
   4524   /* PREFIX_0F3A09 */
   4525   {
   4526     { Bad_Opcode },
   4527     { Bad_Opcode },
   4528     { "roundpd", { XM, EXx, Ib }, PREFIX_OPCODE },
   4529   },
   4530 
   4531   /* PREFIX_0F3A0A */
   4532   {
   4533     { Bad_Opcode },
   4534     { Bad_Opcode },
   4535     { "roundss", { XM, EXd, Ib }, PREFIX_OPCODE },
   4536   },
   4537 
   4538   /* PREFIX_0F3A0B */
   4539   {
   4540     { Bad_Opcode },
   4541     { Bad_Opcode },
   4542     { "roundsd", { XM, EXq, Ib }, PREFIX_OPCODE },
   4543   },
   4544 
   4545   /* PREFIX_0F3A0C */
   4546   {
   4547     { Bad_Opcode },
   4548     { Bad_Opcode },
   4549     { "blendps", { XM, EXx, Ib }, PREFIX_OPCODE },
   4550   },
   4551 
   4552   /* PREFIX_0F3A0D */
   4553   {
   4554     { Bad_Opcode },
   4555     { Bad_Opcode },
   4556     { "blendpd", { XM, EXx, Ib }, PREFIX_OPCODE },
   4557   },
   4558 
   4559   /* PREFIX_0F3A0E */
   4560   {
   4561     { Bad_Opcode },
   4562     { Bad_Opcode },
   4563     { "pblendw", { XM, EXx, Ib }, PREFIX_OPCODE },
   4564   },
   4565 
   4566   /* PREFIX_0F3A14 */
   4567   {
   4568     { Bad_Opcode },
   4569     { Bad_Opcode },
   4570     { "pextrb",	{ Edqb, XM, Ib }, PREFIX_OPCODE },
   4571   },
   4572 
   4573   /* PREFIX_0F3A15 */
   4574   {
   4575     { Bad_Opcode },
   4576     { Bad_Opcode },
   4577     { "pextrw",	{ Edqw, XM, Ib }, PREFIX_OPCODE },
   4578   },
   4579 
   4580   /* PREFIX_0F3A16 */
   4581   {
   4582     { Bad_Opcode },
   4583     { Bad_Opcode },
   4584     { "pextrK",	{ Edq, XM, Ib }, PREFIX_OPCODE },
   4585   },
   4586 
   4587   /* PREFIX_0F3A17 */
   4588   {
   4589     { Bad_Opcode },
   4590     { Bad_Opcode },
   4591     { "extractps", { Edqd, XM, Ib }, PREFIX_OPCODE },
   4592   },
   4593 
   4594   /* PREFIX_0F3A20 */
   4595   {
   4596     { Bad_Opcode },
   4597     { Bad_Opcode },
   4598     { "pinsrb",	{ XM, Edqb, Ib }, PREFIX_OPCODE },
   4599   },
   4600 
   4601   /* PREFIX_0F3A21 */
   4602   {
   4603     { Bad_Opcode },
   4604     { Bad_Opcode },
   4605     { "insertps", { XM, EXd, Ib }, PREFIX_OPCODE },
   4606   },
   4607 
   4608   /* PREFIX_0F3A22 */
   4609   {
   4610     { Bad_Opcode },
   4611     { Bad_Opcode },
   4612     { "pinsrK",	{ XM, Edq, Ib }, PREFIX_OPCODE },
   4613   },
   4614 
   4615   /* PREFIX_0F3A40 */
   4616   {
   4617     { Bad_Opcode },
   4618     { Bad_Opcode },
   4619     { "dpps",	{ XM, EXx, Ib }, PREFIX_OPCODE },
   4620   },
   4621 
   4622   /* PREFIX_0F3A41 */
   4623   {
   4624     { Bad_Opcode },
   4625     { Bad_Opcode },
   4626     { "dppd",	{ XM, EXx, Ib }, PREFIX_OPCODE },
   4627   },
   4628 
   4629   /* PREFIX_0F3A42 */
   4630   {
   4631     { Bad_Opcode },
   4632     { Bad_Opcode },
   4633     { "mpsadbw", { XM, EXx, Ib }, PREFIX_OPCODE },
   4634   },
   4635 
   4636   /* PREFIX_0F3A44 */
   4637   {
   4638     { Bad_Opcode },
   4639     { Bad_Opcode },
   4640     { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_OPCODE },
   4641   },
   4642 
   4643   /* PREFIX_0F3A60 */
   4644   {
   4645     { Bad_Opcode },
   4646     { Bad_Opcode },
   4647     { "pcmpestrm", { XM, EXx, Ib }, PREFIX_OPCODE },
   4648   },
   4649 
   4650   /* PREFIX_0F3A61 */
   4651   {
   4652     { Bad_Opcode },
   4653     { Bad_Opcode },
   4654     { "pcmpestri", { XM, EXx, Ib }, PREFIX_OPCODE },
   4655   },
   4656 
   4657   /* PREFIX_0F3A62 */
   4658   {
   4659     { Bad_Opcode },
   4660     { Bad_Opcode },
   4661     { "pcmpistrm", { XM, EXx, Ib }, PREFIX_OPCODE },
   4662   },
   4663 
   4664   /* PREFIX_0F3A63 */
   4665   {
   4666     { Bad_Opcode },
   4667     { Bad_Opcode },
   4668     { "pcmpistri", { XM, EXx, Ib }, PREFIX_OPCODE },
   4669   },
   4670 
   4671   /* PREFIX_0F3ACC */
   4672   {
   4673     { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
   4674   },
   4675 
   4676   /* PREFIX_0F3ADF */
   4677   {
   4678     { Bad_Opcode },
   4679     { Bad_Opcode },
   4680     { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_OPCODE },
   4681   },
   4682 
   4683   /* PREFIX_VEX_0F10 */
   4684   {
   4685     { VEX_W_TABLE (VEX_W_0F10_P_0) },
   4686     { VEX_LEN_TABLE (VEX_LEN_0F10_P_1) },
   4687     { VEX_W_TABLE (VEX_W_0F10_P_2) },
   4688     { VEX_LEN_TABLE (VEX_LEN_0F10_P_3) },
   4689   },
   4690 
   4691   /* PREFIX_VEX_0F11 */
   4692   {
   4693     { VEX_W_TABLE (VEX_W_0F11_P_0) },
   4694     { VEX_LEN_TABLE (VEX_LEN_0F11_P_1) },
   4695     { VEX_W_TABLE (VEX_W_0F11_P_2) },
   4696     { VEX_LEN_TABLE (VEX_LEN_0F11_P_3) },
   4697   },
   4698 
   4699   /* PREFIX_VEX_0F12 */
   4700   {
   4701     { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
   4702     { VEX_W_TABLE (VEX_W_0F12_P_1) },
   4703     { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) },
   4704     { VEX_W_TABLE (VEX_W_0F12_P_3) },
   4705   },
   4706 
   4707   /* PREFIX_VEX_0F16 */
   4708   {
   4709     { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
   4710     { VEX_W_TABLE (VEX_W_0F16_P_1) },
   4711     { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) },
   4712   },
   4713 
   4714   /* PREFIX_VEX_0F2A */
   4715   {
   4716     { Bad_Opcode },
   4717     { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1) },
   4718     { Bad_Opcode },
   4719     { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3) },
   4720   },
   4721 
   4722   /* PREFIX_VEX_0F2C */
   4723   {
   4724     { Bad_Opcode },
   4725     { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1) },
   4726     { Bad_Opcode },
   4727     { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3) },
   4728   },
   4729 
   4730   /* PREFIX_VEX_0F2D */
   4731   {
   4732     { Bad_Opcode },
   4733     { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1) },
   4734     { Bad_Opcode },
   4735     { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3) },
   4736   },
   4737 
   4738   /* PREFIX_VEX_0F2E */
   4739   {
   4740     { VEX_LEN_TABLE (VEX_LEN_0F2E_P_0) },
   4741     { Bad_Opcode },
   4742     { VEX_LEN_TABLE (VEX_LEN_0F2E_P_2) },
   4743   },
   4744 
   4745   /* PREFIX_VEX_0F2F */
   4746   {
   4747     { VEX_LEN_TABLE (VEX_LEN_0F2F_P_0) },
   4748     { Bad_Opcode },
   4749     { VEX_LEN_TABLE (VEX_LEN_0F2F_P_2) },
   4750   },
   4751 
   4752   /* PREFIX_VEX_0F41 */
   4753   {
   4754     { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) },
   4755     { Bad_Opcode },
   4756     { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) },
   4757   },
   4758 
   4759   /* PREFIX_VEX_0F42 */
   4760   {
   4761     { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) },
   4762     { Bad_Opcode },
   4763     { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) },
   4764   },
   4765 
   4766   /* PREFIX_VEX_0F44 */
   4767   {
   4768     { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) },
   4769     { Bad_Opcode },
   4770     { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) },
   4771   },
   4772 
   4773   /* PREFIX_VEX_0F45 */
   4774   {
   4775     { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) },
   4776     { Bad_Opcode },
   4777     { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) },
   4778   },
   4779 
   4780   /* PREFIX_VEX_0F46 */
   4781   {
   4782     { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) },
   4783     { Bad_Opcode },
   4784     { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) },
   4785   },
   4786 
   4787   /* PREFIX_VEX_0F47 */
   4788   {
   4789     { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) },
   4790     { Bad_Opcode },
   4791     { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) },
   4792   },
   4793 
   4794   /* PREFIX_VEX_0F4A */
   4795   {
   4796     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) },
   4797     { Bad_Opcode },
   4798     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) },
   4799   },
   4800 
   4801   /* PREFIX_VEX_0F4B */
   4802   {
   4803     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) },
   4804     { Bad_Opcode },
   4805     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) },
   4806   },
   4807 
   4808   /* PREFIX_VEX_0F51 */
   4809   {
   4810     { VEX_W_TABLE (VEX_W_0F51_P_0) },
   4811     { VEX_LEN_TABLE (VEX_LEN_0F51_P_1) },
   4812     { VEX_W_TABLE (VEX_W_0F51_P_2) },
   4813     { VEX_LEN_TABLE (VEX_LEN_0F51_P_3) },
   4814   },
   4815 
   4816   /* PREFIX_VEX_0F52 */
   4817   {
   4818     { VEX_W_TABLE (VEX_W_0F52_P_0) },
   4819     { VEX_LEN_TABLE (VEX_LEN_0F52_P_1) },
   4820   },
   4821 
   4822   /* PREFIX_VEX_0F53 */
   4823   {
   4824     { VEX_W_TABLE (VEX_W_0F53_P_0) },
   4825     { VEX_LEN_TABLE (VEX_LEN_0F53_P_1) },
   4826   },
   4827 
   4828   /* PREFIX_VEX_0F58 */
   4829   {
   4830     { VEX_W_TABLE (VEX_W_0F58_P_0) },
   4831     { VEX_LEN_TABLE (VEX_LEN_0F58_P_1) },
   4832     { VEX_W_TABLE (VEX_W_0F58_P_2) },
   4833     { VEX_LEN_TABLE (VEX_LEN_0F58_P_3) },
   4834   },
   4835 
   4836   /* PREFIX_VEX_0F59 */
   4837   {
   4838     { VEX_W_TABLE (VEX_W_0F59_P_0) },
   4839     { VEX_LEN_TABLE (VEX_LEN_0F59_P_1) },
   4840     { VEX_W_TABLE (VEX_W_0F59_P_2) },
   4841     { VEX_LEN_TABLE (VEX_LEN_0F59_P_3) },
   4842   },
   4843 
   4844   /* PREFIX_VEX_0F5A */
   4845   {
   4846     { VEX_W_TABLE (VEX_W_0F5A_P_0) },
   4847     { VEX_LEN_TABLE (VEX_LEN_0F5A_P_1) },
   4848     { "vcvtpd2ps%XY", { XMM, EXx }, 0 },
   4849     { VEX_LEN_TABLE (VEX_LEN_0F5A_P_3) },
   4850   },
   4851 
   4852   /* PREFIX_VEX_0F5B */
   4853   {
   4854     { VEX_W_TABLE (VEX_W_0F5B_P_0) },
   4855     { VEX_W_TABLE (VEX_W_0F5B_P_1) },
   4856     { VEX_W_TABLE (VEX_W_0F5B_P_2) },
   4857   },
   4858 
   4859   /* PREFIX_VEX_0F5C */
   4860   {
   4861     { VEX_W_TABLE (VEX_W_0F5C_P_0) },
   4862     { VEX_LEN_TABLE (VEX_LEN_0F5C_P_1) },
   4863     { VEX_W_TABLE (VEX_W_0F5C_P_2) },
   4864     { VEX_LEN_TABLE (VEX_LEN_0F5C_P_3) },
   4865   },
   4866 
   4867   /* PREFIX_VEX_0F5D */
   4868   {
   4869     { VEX_W_TABLE (VEX_W_0F5D_P_0) },
   4870     { VEX_LEN_TABLE (VEX_LEN_0F5D_P_1) },
   4871     { VEX_W_TABLE (VEX_W_0F5D_P_2) },
   4872     { VEX_LEN_TABLE (VEX_LEN_0F5D_P_3) },
   4873   },
   4874 
   4875   /* PREFIX_VEX_0F5E */
   4876   {
   4877     { VEX_W_TABLE (VEX_W_0F5E_P_0) },
   4878     { VEX_LEN_TABLE (VEX_LEN_0F5E_P_1) },
   4879     { VEX_W_TABLE (VEX_W_0F5E_P_2) },
   4880     { VEX_LEN_TABLE (VEX_LEN_0F5E_P_3) },
   4881   },
   4882 
   4883   /* PREFIX_VEX_0F5F */
   4884   {
   4885     { VEX_W_TABLE (VEX_W_0F5F_P_0) },
   4886     { VEX_LEN_TABLE (VEX_LEN_0F5F_P_1) },
   4887     { VEX_W_TABLE (VEX_W_0F5F_P_2) },
   4888     { VEX_LEN_TABLE (VEX_LEN_0F5F_P_3) },
   4889   },
   4890 
   4891   /* PREFIX_VEX_0F60 */
   4892   {
   4893     { Bad_Opcode },
   4894     { Bad_Opcode },
   4895     { VEX_W_TABLE (VEX_W_0F60_P_2) },
   4896   },
   4897 
   4898   /* PREFIX_VEX_0F61 */
   4899   {
   4900     { Bad_Opcode },
   4901     { Bad_Opcode },
   4902     { VEX_W_TABLE (VEX_W_0F61_P_2) },
   4903   },
   4904 
   4905   /* PREFIX_VEX_0F62 */
   4906   {
   4907     { Bad_Opcode },
   4908     { Bad_Opcode },
   4909     { VEX_W_TABLE (VEX_W_0F62_P_2) },
   4910   },
   4911 
   4912   /* PREFIX_VEX_0F63 */
   4913   {
   4914     { Bad_Opcode },
   4915     { Bad_Opcode },
   4916     { VEX_W_TABLE (VEX_W_0F63_P_2) },
   4917   },
   4918 
   4919   /* PREFIX_VEX_0F64 */
   4920   {
   4921     { Bad_Opcode },
   4922     { Bad_Opcode },
   4923     { VEX_W_TABLE (VEX_W_0F64_P_2) },
   4924   },
   4925 
   4926   /* PREFIX_VEX_0F65 */
   4927   {
   4928     { Bad_Opcode },
   4929     { Bad_Opcode },
   4930     { VEX_W_TABLE (VEX_W_0F65_P_2) },
   4931   },
   4932 
   4933   /* PREFIX_VEX_0F66 */
   4934   {
   4935     { Bad_Opcode },
   4936     { Bad_Opcode },
   4937     { VEX_W_TABLE (VEX_W_0F66_P_2) },
   4938   },
   4939 
   4940   /* PREFIX_VEX_0F67 */
   4941   {
   4942     { Bad_Opcode },
   4943     { Bad_Opcode },
   4944     { VEX_W_TABLE (VEX_W_0F67_P_2) },
   4945   },
   4946 
   4947   /* PREFIX_VEX_0F68 */
   4948   {
   4949     { Bad_Opcode },
   4950     { Bad_Opcode },
   4951     { VEX_W_TABLE (VEX_W_0F68_P_2) },
   4952   },
   4953 
   4954   /* PREFIX_VEX_0F69 */
   4955   {
   4956     { Bad_Opcode },
   4957     { Bad_Opcode },
   4958     { VEX_W_TABLE (VEX_W_0F69_P_2) },
   4959   },
   4960 
   4961   /* PREFIX_VEX_0F6A */
   4962   {
   4963     { Bad_Opcode },
   4964     { Bad_Opcode },
   4965     { VEX_W_TABLE (VEX_W_0F6A_P_2) },
   4966   },
   4967 
   4968   /* PREFIX_VEX_0F6B */
   4969   {
   4970     { Bad_Opcode },
   4971     { Bad_Opcode },
   4972     { VEX_W_TABLE (VEX_W_0F6B_P_2) },
   4973   },
   4974 
   4975   /* PREFIX_VEX_0F6C */
   4976   {
   4977     { Bad_Opcode },
   4978     { Bad_Opcode },
   4979     { VEX_W_TABLE (VEX_W_0F6C_P_2) },
   4980   },
   4981 
   4982   /* PREFIX_VEX_0F6D */
   4983   {
   4984     { Bad_Opcode },
   4985     { Bad_Opcode },
   4986     { VEX_W_TABLE (VEX_W_0F6D_P_2) },
   4987   },
   4988 
   4989   /* PREFIX_VEX_0F6E */
   4990   {
   4991     { Bad_Opcode },
   4992     { Bad_Opcode },
   4993     { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) },
   4994   },
   4995 
   4996   /* PREFIX_VEX_0F6F */
   4997   {
   4998     { Bad_Opcode },
   4999     { VEX_W_TABLE (VEX_W_0F6F_P_1) },
   5000     { VEX_W_TABLE (VEX_W_0F6F_P_2) },
   5001   },
   5002 
   5003   /* PREFIX_VEX_0F70 */
   5004   {
   5005     { Bad_Opcode },
   5006     { VEX_W_TABLE (VEX_W_0F70_P_1) },
   5007     { VEX_W_TABLE (VEX_W_0F70_P_2) },
   5008     { VEX_W_TABLE (VEX_W_0F70_P_3) },
   5009   },
   5010 
   5011   /* PREFIX_VEX_0F71_REG_2 */
   5012   {
   5013     { Bad_Opcode },
   5014     { Bad_Opcode },
   5015     { VEX_W_TABLE (VEX_W_0F71_R_2_P_2) },
   5016   },
   5017 
   5018   /* PREFIX_VEX_0F71_REG_4 */
   5019   {
   5020     { Bad_Opcode },
   5021     { Bad_Opcode },
   5022     { VEX_W_TABLE (VEX_W_0F71_R_4_P_2) },
   5023   },
   5024 
   5025   /* PREFIX_VEX_0F71_REG_6 */
   5026   {
   5027     { Bad_Opcode },
   5028     { Bad_Opcode },
   5029     { VEX_W_TABLE (VEX_W_0F71_R_6_P_2) },
   5030   },
   5031 
   5032   /* PREFIX_VEX_0F72_REG_2 */
   5033   {
   5034     { Bad_Opcode },
   5035     { Bad_Opcode },
   5036     { VEX_W_TABLE (VEX_W_0F72_R_2_P_2) },
   5037   },
   5038 
   5039   /* PREFIX_VEX_0F72_REG_4 */
   5040   {
   5041     { Bad_Opcode },
   5042     { Bad_Opcode },
   5043     { VEX_W_TABLE (VEX_W_0F72_R_4_P_2) },
   5044   },
   5045 
   5046   /* PREFIX_VEX_0F72_REG_6 */
   5047   {
   5048     { Bad_Opcode },
   5049     { Bad_Opcode },
   5050     { VEX_W_TABLE (VEX_W_0F72_R_6_P_2) },
   5051   },
   5052 
   5053   /* PREFIX_VEX_0F73_REG_2 */
   5054   {
   5055     { Bad_Opcode },
   5056     { Bad_Opcode },
   5057     { VEX_W_TABLE (VEX_W_0F73_R_2_P_2) },
   5058   },
   5059 
   5060   /* PREFIX_VEX_0F73_REG_3 */
   5061   {
   5062     { Bad_Opcode },
   5063     { Bad_Opcode },
   5064     { VEX_W_TABLE (VEX_W_0F73_R_3_P_2) },
   5065   },
   5066 
   5067   /* PREFIX_VEX_0F73_REG_6 */
   5068   {
   5069     { Bad_Opcode },
   5070     { Bad_Opcode },
   5071     { VEX_W_TABLE (VEX_W_0F73_R_6_P_2) },
   5072   },
   5073 
   5074   /* PREFIX_VEX_0F73_REG_7 */
   5075   {
   5076     { Bad_Opcode },
   5077     { Bad_Opcode },
   5078     { VEX_W_TABLE (VEX_W_0F73_R_7_P_2) },
   5079   },
   5080 
   5081   /* PREFIX_VEX_0F74 */
   5082   {
   5083     { Bad_Opcode },
   5084     { Bad_Opcode },
   5085     { VEX_W_TABLE (VEX_W_0F74_P_2) },
   5086   },
   5087 
   5088   /* PREFIX_VEX_0F75 */
   5089   {
   5090     { Bad_Opcode },
   5091     { Bad_Opcode },
   5092     { VEX_W_TABLE (VEX_W_0F75_P_2) },
   5093   },
   5094 
   5095   /* PREFIX_VEX_0F76 */
   5096   {
   5097     { Bad_Opcode },
   5098     { Bad_Opcode },
   5099     { VEX_W_TABLE (VEX_W_0F76_P_2) },
   5100   },
   5101 
   5102   /* PREFIX_VEX_0F77 */
   5103   {
   5104     { VEX_W_TABLE (VEX_W_0F77_P_0) },
   5105   },
   5106 
   5107   /* PREFIX_VEX_0F7C */
   5108   {
   5109     { Bad_Opcode },
   5110     { Bad_Opcode },
   5111     { VEX_W_TABLE (VEX_W_0F7C_P_2) },
   5112     { VEX_W_TABLE (VEX_W_0F7C_P_3) },
   5113   },
   5114 
   5115   /* PREFIX_VEX_0F7D */
   5116   {
   5117     { Bad_Opcode },
   5118     { Bad_Opcode },
   5119     { VEX_W_TABLE (VEX_W_0F7D_P_2) },
   5120     { VEX_W_TABLE (VEX_W_0F7D_P_3) },
   5121   },
   5122 
   5123   /* PREFIX_VEX_0F7E */
   5124   {
   5125     { Bad_Opcode },
   5126     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
   5127     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
   5128   },
   5129 
   5130   /* PREFIX_VEX_0F7F */
   5131   {
   5132     { Bad_Opcode },
   5133     { VEX_W_TABLE (VEX_W_0F7F_P_1) },
   5134     { VEX_W_TABLE (VEX_W_0F7F_P_2) },
   5135   },
   5136 
   5137   /* PREFIX_VEX_0F90 */
   5138   {
   5139     { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) },
   5140     { Bad_Opcode },
   5141     { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) },
   5142   },
   5143 
   5144   /* PREFIX_VEX_0F91 */
   5145   {
   5146     { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) },
   5147     { Bad_Opcode },
   5148     { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) },
   5149   },
   5150 
   5151   /* PREFIX_VEX_0F92 */
   5152   {
   5153     { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) },
   5154     { Bad_Opcode },
   5155     { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) },
   5156     { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) },
   5157   },
   5158 
   5159   /* PREFIX_VEX_0F93 */
   5160   {
   5161     { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) },
   5162     { Bad_Opcode },
   5163     { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) },
   5164     { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) },
   5165   },
   5166 
   5167   /* PREFIX_VEX_0F98 */
   5168   {
   5169     { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) },
   5170     { Bad_Opcode },
   5171     { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) },
   5172   },
   5173 
   5174   /* PREFIX_VEX_0F99 */
   5175   {
   5176     { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) },
   5177     { Bad_Opcode },
   5178     { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) },
   5179   },
   5180 
   5181   /* PREFIX_VEX_0FC2 */
   5182   {
   5183     { VEX_W_TABLE (VEX_W_0FC2_P_0) },
   5184     { VEX_LEN_TABLE (VEX_LEN_0FC2_P_1) },
   5185     { VEX_W_TABLE (VEX_W_0FC2_P_2) },
   5186     { VEX_LEN_TABLE (VEX_LEN_0FC2_P_3) },
   5187   },
   5188 
   5189   /* PREFIX_VEX_0FC4 */
   5190   {
   5191     { Bad_Opcode },
   5192     { Bad_Opcode },
   5193     { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) },
   5194   },
   5195 
   5196   /* PREFIX_VEX_0FC5 */
   5197   {
   5198     { Bad_Opcode },
   5199     { Bad_Opcode },
   5200     { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) },
   5201   },
   5202 
   5203   /* PREFIX_VEX_0FD0 */
   5204   {
   5205     { Bad_Opcode },
   5206     { Bad_Opcode },
   5207     { VEX_W_TABLE (VEX_W_0FD0_P_2) },
   5208     { VEX_W_TABLE (VEX_W_0FD0_P_3) },
   5209   },
   5210 
   5211   /* PREFIX_VEX_0FD1 */
   5212   {
   5213     { Bad_Opcode },
   5214     { Bad_Opcode },
   5215     { VEX_W_TABLE (VEX_W_0FD1_P_2) },
   5216   },
   5217 
   5218   /* PREFIX_VEX_0FD2 */
   5219   {
   5220     { Bad_Opcode },
   5221     { Bad_Opcode },
   5222     { VEX_W_TABLE (VEX_W_0FD2_P_2) },
   5223   },
   5224 
   5225   /* PREFIX_VEX_0FD3 */
   5226   {
   5227     { Bad_Opcode },
   5228     { Bad_Opcode },
   5229     { VEX_W_TABLE (VEX_W_0FD3_P_2) },
   5230   },
   5231 
   5232   /* PREFIX_VEX_0FD4 */
   5233   {
   5234     { Bad_Opcode },
   5235     { Bad_Opcode },
   5236     { VEX_W_TABLE (VEX_W_0FD4_P_2) },
   5237   },
   5238 
   5239   /* PREFIX_VEX_0FD5 */
   5240   {
   5241     { Bad_Opcode },
   5242     { Bad_Opcode },
   5243     { VEX_W_TABLE (VEX_W_0FD5_P_2) },
   5244   },
   5245 
   5246   /* PREFIX_VEX_0FD6 */
   5247   {
   5248     { Bad_Opcode },
   5249     { Bad_Opcode },
   5250     { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) },
   5251   },
   5252 
   5253   /* PREFIX_VEX_0FD7 */
   5254   {
   5255     { Bad_Opcode },
   5256     { Bad_Opcode },
   5257     { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) },
   5258   },
   5259 
   5260   /* PREFIX_VEX_0FD8 */
   5261   {
   5262     { Bad_Opcode },
   5263     { Bad_Opcode },
   5264     { VEX_W_TABLE (VEX_W_0FD8_P_2) },
   5265   },
   5266 
   5267   /* PREFIX_VEX_0FD9 */
   5268   {
   5269     { Bad_Opcode },
   5270     { Bad_Opcode },
   5271     { VEX_W_TABLE (VEX_W_0FD9_P_2) },
   5272   },
   5273 
   5274   /* PREFIX_VEX_0FDA */
   5275   {
   5276     { Bad_Opcode },
   5277     { Bad_Opcode },
   5278     { VEX_W_TABLE (VEX_W_0FDA_P_2) },
   5279   },
   5280 
   5281   /* PREFIX_VEX_0FDB */
   5282   {
   5283     { Bad_Opcode },
   5284     { Bad_Opcode },
   5285     { VEX_W_TABLE (VEX_W_0FDB_P_2) },
   5286   },
   5287 
   5288   /* PREFIX_VEX_0FDC */
   5289   {
   5290     { Bad_Opcode },
   5291     { Bad_Opcode },
   5292     { VEX_W_TABLE (VEX_W_0FDC_P_2) },
   5293   },
   5294 
   5295   /* PREFIX_VEX_0FDD */
   5296   {
   5297     { Bad_Opcode },
   5298     { Bad_Opcode },
   5299     { VEX_W_TABLE (VEX_W_0FDD_P_2) },
   5300   },
   5301 
   5302   /* PREFIX_VEX_0FDE */
   5303   {
   5304     { Bad_Opcode },
   5305     { Bad_Opcode },
   5306     { VEX_W_TABLE (VEX_W_0FDE_P_2) },
   5307   },
   5308 
   5309   /* PREFIX_VEX_0FDF */
   5310   {
   5311     { Bad_Opcode },
   5312     { Bad_Opcode },
   5313     { VEX_W_TABLE (VEX_W_0FDF_P_2) },
   5314   },
   5315 
   5316   /* PREFIX_VEX_0FE0 */
   5317   {
   5318     { Bad_Opcode },
   5319     { Bad_Opcode },
   5320     { VEX_W_TABLE (VEX_W_0FE0_P_2) },
   5321   },
   5322 
   5323   /* PREFIX_VEX_0FE1 */
   5324   {
   5325     { Bad_Opcode },
   5326     { Bad_Opcode },
   5327     { VEX_W_TABLE (VEX_W_0FE1_P_2) },
   5328   },
   5329 
   5330   /* PREFIX_VEX_0FE2 */
   5331   {
   5332     { Bad_Opcode },
   5333     { Bad_Opcode },
   5334     { VEX_W_TABLE (VEX_W_0FE2_P_2) },
   5335   },
   5336 
   5337   /* PREFIX_VEX_0FE3 */
   5338   {
   5339     { Bad_Opcode },
   5340     { Bad_Opcode },
   5341     { VEX_W_TABLE (VEX_W_0FE3_P_2) },
   5342   },
   5343 
   5344   /* PREFIX_VEX_0FE4 */
   5345   {
   5346     { Bad_Opcode },
   5347     { Bad_Opcode },
   5348     { VEX_W_TABLE (VEX_W_0FE4_P_2) },
   5349   },
   5350 
   5351   /* PREFIX_VEX_0FE5 */
   5352   {
   5353     { Bad_Opcode },
   5354     { Bad_Opcode },
   5355     { VEX_W_TABLE (VEX_W_0FE5_P_2) },
   5356   },
   5357 
   5358   /* PREFIX_VEX_0FE6 */
   5359   {
   5360     { Bad_Opcode },
   5361     { VEX_W_TABLE (VEX_W_0FE6_P_1) },
   5362     { VEX_W_TABLE (VEX_W_0FE6_P_2) },
   5363     { VEX_W_TABLE (VEX_W_0FE6_P_3) },
   5364   },
   5365 
   5366   /* PREFIX_VEX_0FE7 */
   5367   {
   5368     { Bad_Opcode },
   5369     { Bad_Opcode },
   5370     { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) },
   5371   },
   5372 
   5373   /* PREFIX_VEX_0FE8 */
   5374   {
   5375     { Bad_Opcode },
   5376     { Bad_Opcode },
   5377     { VEX_W_TABLE (VEX_W_0FE8_P_2) },
   5378   },
   5379 
   5380   /* PREFIX_VEX_0FE9 */
   5381   {
   5382     { Bad_Opcode },
   5383     { Bad_Opcode },
   5384     { VEX_W_TABLE (VEX_W_0FE9_P_2) },
   5385   },
   5386 
   5387   /* PREFIX_VEX_0FEA */
   5388   {
   5389     { Bad_Opcode },
   5390     { Bad_Opcode },
   5391     { VEX_W_TABLE (VEX_W_0FEA_P_2) },
   5392   },
   5393 
   5394   /* PREFIX_VEX_0FEB */
   5395   {
   5396     { Bad_Opcode },
   5397     { Bad_Opcode },
   5398     { VEX_W_TABLE (VEX_W_0FEB_P_2) },
   5399   },
   5400 
   5401   /* PREFIX_VEX_0FEC */
   5402   {
   5403     { Bad_Opcode },
   5404     { Bad_Opcode },
   5405     { VEX_W_TABLE (VEX_W_0FEC_P_2) },
   5406   },
   5407 
   5408   /* PREFIX_VEX_0FED */
   5409   {
   5410     { Bad_Opcode },
   5411     { Bad_Opcode },
   5412     { VEX_W_TABLE (VEX_W_0FED_P_2) },
   5413   },
   5414 
   5415   /* PREFIX_VEX_0FEE */
   5416   {
   5417     { Bad_Opcode },
   5418     { Bad_Opcode },
   5419     { VEX_W_TABLE (VEX_W_0FEE_P_2) },
   5420   },
   5421 
   5422   /* PREFIX_VEX_0FEF */
   5423   {
   5424     { Bad_Opcode },
   5425     { Bad_Opcode },
   5426     { VEX_W_TABLE (VEX_W_0FEF_P_2) },
   5427   },
   5428 
   5429   /* PREFIX_VEX_0FF0 */
   5430   {
   5431     { Bad_Opcode },
   5432     { Bad_Opcode },
   5433     { Bad_Opcode },
   5434     { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
   5435   },
   5436 
   5437   /* PREFIX_VEX_0FF1 */
   5438   {
   5439     { Bad_Opcode },
   5440     { Bad_Opcode },
   5441     { VEX_W_TABLE (VEX_W_0FF1_P_2) },
   5442   },
   5443 
   5444   /* PREFIX_VEX_0FF2 */
   5445   {
   5446     { Bad_Opcode },
   5447     { Bad_Opcode },
   5448     { VEX_W_TABLE (VEX_W_0FF2_P_2) },
   5449   },
   5450 
   5451   /* PREFIX_VEX_0FF3 */
   5452   {
   5453     { Bad_Opcode },
   5454     { Bad_Opcode },
   5455     { VEX_W_TABLE (VEX_W_0FF3_P_2) },
   5456   },
   5457 
   5458   /* PREFIX_VEX_0FF4 */
   5459   {
   5460     { Bad_Opcode },
   5461     { Bad_Opcode },
   5462     { VEX_W_TABLE (VEX_W_0FF4_P_2) },
   5463   },
   5464 
   5465   /* PREFIX_VEX_0FF5 */
   5466   {
   5467     { Bad_Opcode },
   5468     { Bad_Opcode },
   5469     { VEX_W_TABLE (VEX_W_0FF5_P_2) },
   5470   },
   5471 
   5472   /* PREFIX_VEX_0FF6 */
   5473   {
   5474     { Bad_Opcode },
   5475     { Bad_Opcode },
   5476     { VEX_W_TABLE (VEX_W_0FF6_P_2) },
   5477   },
   5478 
   5479   /* PREFIX_VEX_0FF7 */
   5480   {
   5481     { Bad_Opcode },
   5482     { Bad_Opcode },
   5483     { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) },
   5484   },
   5485 
   5486   /* PREFIX_VEX_0FF8 */
   5487   {
   5488     { Bad_Opcode },
   5489     { Bad_Opcode },
   5490     { VEX_W_TABLE (VEX_W_0FF8_P_2) },
   5491   },
   5492 
   5493   /* PREFIX_VEX_0FF9 */
   5494   {
   5495     { Bad_Opcode },
   5496     { Bad_Opcode },
   5497     { VEX_W_TABLE (VEX_W_0FF9_P_2) },
   5498   },
   5499 
   5500   /* PREFIX_VEX_0FFA */
   5501   {
   5502     { Bad_Opcode },
   5503     { Bad_Opcode },
   5504     { VEX_W_TABLE (VEX_W_0FFA_P_2) },
   5505   },
   5506 
   5507   /* PREFIX_VEX_0FFB */
   5508   {
   5509     { Bad_Opcode },
   5510     { Bad_Opcode },
   5511     { VEX_W_TABLE (VEX_W_0FFB_P_2) },
   5512   },
   5513 
   5514   /* PREFIX_VEX_0FFC */
   5515   {
   5516     { Bad_Opcode },
   5517     { Bad_Opcode },
   5518     { VEX_W_TABLE (VEX_W_0FFC_P_2) },
   5519   },
   5520 
   5521   /* PREFIX_VEX_0FFD */
   5522   {
   5523     { Bad_Opcode },
   5524     { Bad_Opcode },
   5525     { VEX_W_TABLE (VEX_W_0FFD_P_2) },
   5526   },
   5527 
   5528   /* PREFIX_VEX_0FFE */
   5529   {
   5530     { Bad_Opcode },
   5531     { Bad_Opcode },
   5532     { VEX_W_TABLE (VEX_W_0FFE_P_2) },
   5533   },
   5534 
   5535   /* PREFIX_VEX_0F3800 */
   5536   {
   5537     { Bad_Opcode },
   5538     { Bad_Opcode },
   5539     { VEX_W_TABLE (VEX_W_0F3800_P_2) },
   5540   },
   5541 
   5542   /* PREFIX_VEX_0F3801 */
   5543   {
   5544     { Bad_Opcode },
   5545     { Bad_Opcode },
   5546     { VEX_W_TABLE (VEX_W_0F3801_P_2) },
   5547   },
   5548 
   5549   /* PREFIX_VEX_0F3802 */
   5550   {
   5551     { Bad_Opcode },
   5552     { Bad_Opcode },
   5553     { VEX_W_TABLE (VEX_W_0F3802_P_2) },
   5554   },
   5555 
   5556   /* PREFIX_VEX_0F3803 */
   5557   {
   5558     { Bad_Opcode },
   5559     { Bad_Opcode },
   5560     { VEX_W_TABLE (VEX_W_0F3803_P_2) },
   5561   },
   5562 
   5563   /* PREFIX_VEX_0F3804 */
   5564   {
   5565     { Bad_Opcode },
   5566     { Bad_Opcode },
   5567     { VEX_W_TABLE (VEX_W_0F3804_P_2) },
   5568   },
   5569 
   5570   /* PREFIX_VEX_0F3805 */
   5571   {
   5572     { Bad_Opcode },
   5573     { Bad_Opcode },
   5574     { VEX_W_TABLE (VEX_W_0F3805_P_2) },
   5575   },
   5576 
   5577   /* PREFIX_VEX_0F3806 */
   5578   {
   5579     { Bad_Opcode },
   5580     { Bad_Opcode },
   5581     { VEX_W_TABLE (VEX_W_0F3806_P_2) },
   5582   },
   5583 
   5584   /* PREFIX_VEX_0F3807 */
   5585   {
   5586     { Bad_Opcode },
   5587     { Bad_Opcode },
   5588     { VEX_W_TABLE (VEX_W_0F3807_P_2) },
   5589   },
   5590 
   5591   /* PREFIX_VEX_0F3808 */
   5592   {
   5593     { Bad_Opcode },
   5594     { Bad_Opcode },
   5595     { VEX_W_TABLE (VEX_W_0F3808_P_2) },
   5596   },
   5597 
   5598   /* PREFIX_VEX_0F3809 */
   5599   {
   5600     { Bad_Opcode },
   5601     { Bad_Opcode },
   5602     { VEX_W_TABLE (VEX_W_0F3809_P_2) },
   5603   },
   5604 
   5605   /* PREFIX_VEX_0F380A */
   5606   {
   5607     { Bad_Opcode },
   5608     { Bad_Opcode },
   5609     { VEX_W_TABLE (VEX_W_0F380A_P_2) },
   5610   },
   5611 
   5612   /* PREFIX_VEX_0F380B */
   5613   {
   5614     { Bad_Opcode },
   5615     { Bad_Opcode },
   5616     { VEX_W_TABLE (VEX_W_0F380B_P_2) },
   5617   },
   5618 
   5619   /* PREFIX_VEX_0F380C */
   5620   {
   5621     { Bad_Opcode },
   5622     { Bad_Opcode },
   5623     { VEX_W_TABLE (VEX_W_0F380C_P_2) },
   5624   },
   5625 
   5626   /* PREFIX_VEX_0F380D */
   5627   {
   5628     { Bad_Opcode },
   5629     { Bad_Opcode },
   5630     { VEX_W_TABLE (VEX_W_0F380D_P_2) },
   5631   },
   5632 
   5633   /* PREFIX_VEX_0F380E */
   5634   {
   5635     { Bad_Opcode },
   5636     { Bad_Opcode },
   5637     { VEX_W_TABLE (VEX_W_0F380E_P_2) },
   5638   },
   5639 
   5640   /* PREFIX_VEX_0F380F */
   5641   {
   5642     { Bad_Opcode },
   5643     { Bad_Opcode },
   5644     { VEX_W_TABLE (VEX_W_0F380F_P_2) },
   5645   },
   5646 
   5647   /* PREFIX_VEX_0F3813 */
   5648   {
   5649     { Bad_Opcode },
   5650     { Bad_Opcode },
   5651     { "vcvtph2ps", { XM, EXxmmq }, 0 },
   5652   },
   5653 
   5654   /* PREFIX_VEX_0F3816 */
   5655   {
   5656     { Bad_Opcode },
   5657     { Bad_Opcode },
   5658     { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) },
   5659   },
   5660 
   5661   /* PREFIX_VEX_0F3817 */
   5662   {
   5663     { Bad_Opcode },
   5664     { Bad_Opcode },
   5665     { VEX_W_TABLE (VEX_W_0F3817_P_2) },
   5666   },
   5667 
   5668   /* PREFIX_VEX_0F3818 */
   5669   {
   5670     { Bad_Opcode },
   5671     { Bad_Opcode },
   5672     { VEX_W_TABLE (VEX_W_0F3818_P_2) },
   5673   },
   5674 
   5675   /* PREFIX_VEX_0F3819 */
   5676   {
   5677     { Bad_Opcode },
   5678     { Bad_Opcode },
   5679     { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) },
   5680   },
   5681 
   5682   /* PREFIX_VEX_0F381A */
   5683   {
   5684     { Bad_Opcode },
   5685     { Bad_Opcode },
   5686     { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) },
   5687   },
   5688 
   5689   /* PREFIX_VEX_0F381C */
   5690   {
   5691     { Bad_Opcode },
   5692     { Bad_Opcode },
   5693     { VEX_W_TABLE (VEX_W_0F381C_P_2) },
   5694   },
   5695 
   5696   /* PREFIX_VEX_0F381D */
   5697   {
   5698     { Bad_Opcode },
   5699     { Bad_Opcode },
   5700     { VEX_W_TABLE (VEX_W_0F381D_P_2) },
   5701   },
   5702 
   5703   /* PREFIX_VEX_0F381E */
   5704   {
   5705     { Bad_Opcode },
   5706     { Bad_Opcode },
   5707     { VEX_W_TABLE (VEX_W_0F381E_P_2) },
   5708   },
   5709 
   5710   /* PREFIX_VEX_0F3820 */
   5711   {
   5712     { Bad_Opcode },
   5713     { Bad_Opcode },
   5714     { VEX_W_TABLE (VEX_W_0F3820_P_2) },
   5715   },
   5716 
   5717   /* PREFIX_VEX_0F3821 */
   5718   {
   5719     { Bad_Opcode },
   5720     { Bad_Opcode },
   5721     { VEX_W_TABLE (VEX_W_0F3821_P_2) },
   5722   },
   5723 
   5724   /* PREFIX_VEX_0F3822 */
   5725   {
   5726     { Bad_Opcode },
   5727     { Bad_Opcode },
   5728     { VEX_W_TABLE (VEX_W_0F3822_P_2) },
   5729   },
   5730 
   5731   /* PREFIX_VEX_0F3823 */
   5732   {
   5733     { Bad_Opcode },
   5734     { Bad_Opcode },
   5735     { VEX_W_TABLE (VEX_W_0F3823_P_2) },
   5736   },
   5737 
   5738   /* PREFIX_VEX_0F3824 */
   5739   {
   5740     { Bad_Opcode },
   5741     { Bad_Opcode },
   5742     { VEX_W_TABLE (VEX_W_0F3824_P_2) },
   5743   },
   5744 
   5745   /* PREFIX_VEX_0F3825 */
   5746   {
   5747     { Bad_Opcode },
   5748     { Bad_Opcode },
   5749     { VEX_W_TABLE (VEX_W_0F3825_P_2) },
   5750   },
   5751 
   5752   /* PREFIX_VEX_0F3828 */
   5753   {
   5754     { Bad_Opcode },
   5755     { Bad_Opcode },
   5756     { VEX_W_TABLE (VEX_W_0F3828_P_2) },
   5757   },
   5758 
   5759   /* PREFIX_VEX_0F3829 */
   5760   {
   5761     { Bad_Opcode },
   5762     { Bad_Opcode },
   5763     { VEX_W_TABLE (VEX_W_0F3829_P_2) },
   5764   },
   5765 
   5766   /* PREFIX_VEX_0F382A */
   5767   {
   5768     { Bad_Opcode },
   5769     { Bad_Opcode },
   5770     { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) },
   5771   },
   5772 
   5773   /* PREFIX_VEX_0F382B */
   5774   {
   5775     { Bad_Opcode },
   5776     { Bad_Opcode },
   5777     { VEX_W_TABLE (VEX_W_0F382B_P_2) },
   5778   },
   5779 
   5780   /* PREFIX_VEX_0F382C */
   5781   {
   5782     { Bad_Opcode },
   5783     { Bad_Opcode },
   5784      { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) },
   5785   },
   5786 
   5787   /* PREFIX_VEX_0F382D */
   5788   {
   5789     { Bad_Opcode },
   5790     { Bad_Opcode },
   5791      { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) },
   5792   },
   5793 
   5794   /* PREFIX_VEX_0F382E */
   5795   {
   5796     { Bad_Opcode },
   5797     { Bad_Opcode },
   5798      { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) },
   5799   },
   5800 
   5801   /* PREFIX_VEX_0F382F */
   5802   {
   5803     { Bad_Opcode },
   5804     { Bad_Opcode },
   5805      { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) },
   5806   },
   5807 
   5808   /* PREFIX_VEX_0F3830 */
   5809   {
   5810     { Bad_Opcode },
   5811     { Bad_Opcode },
   5812     { VEX_W_TABLE (VEX_W_0F3830_P_2) },
   5813   },
   5814 
   5815   /* PREFIX_VEX_0F3831 */
   5816   {
   5817     { Bad_Opcode },
   5818     { Bad_Opcode },
   5819     { VEX_W_TABLE (VEX_W_0F3831_P_2) },
   5820   },
   5821 
   5822   /* PREFIX_VEX_0F3832 */
   5823   {
   5824     { Bad_Opcode },
   5825     { Bad_Opcode },
   5826     { VEX_W_TABLE (VEX_W_0F3832_P_2) },
   5827   },
   5828 
   5829   /* PREFIX_VEX_0F3833 */
   5830   {
   5831     { Bad_Opcode },
   5832     { Bad_Opcode },
   5833     { VEX_W_TABLE (VEX_W_0F3833_P_2) },
   5834   },
   5835 
   5836   /* PREFIX_VEX_0F3834 */
   5837   {
   5838     { Bad_Opcode },
   5839     { Bad_Opcode },
   5840     { VEX_W_TABLE (VEX_W_0F3834_P_2) },
   5841   },
   5842 
   5843   /* PREFIX_VEX_0F3835 */
   5844   {
   5845     { Bad_Opcode },
   5846     { Bad_Opcode },
   5847     { VEX_W_TABLE (VEX_W_0F3835_P_2) },
   5848   },
   5849 
   5850   /* PREFIX_VEX_0F3836 */
   5851   {
   5852     { Bad_Opcode },
   5853     { Bad_Opcode },
   5854     { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) },
   5855   },
   5856 
   5857   /* PREFIX_VEX_0F3837 */
   5858   {
   5859     { Bad_Opcode },
   5860     { Bad_Opcode },
   5861     { VEX_W_TABLE (VEX_W_0F3837_P_2) },
   5862   },
   5863 
   5864   /* PREFIX_VEX_0F3838 */
   5865   {
   5866     { Bad_Opcode },
   5867     { Bad_Opcode },
   5868     { VEX_W_TABLE (VEX_W_0F3838_P_2) },
   5869   },
   5870 
   5871   /* PREFIX_VEX_0F3839 */
   5872   {
   5873     { Bad_Opcode },
   5874     { Bad_Opcode },
   5875     { VEX_W_TABLE (VEX_W_0F3839_P_2) },
   5876   },
   5877 
   5878   /* PREFIX_VEX_0F383A */
   5879   {
   5880     { Bad_Opcode },
   5881     { Bad_Opcode },
   5882     { VEX_W_TABLE (VEX_W_0F383A_P_2) },
   5883   },
   5884 
   5885   /* PREFIX_VEX_0F383B */
   5886   {
   5887     { Bad_Opcode },
   5888     { Bad_Opcode },
   5889     { VEX_W_TABLE (VEX_W_0F383B_P_2) },
   5890   },
   5891 
   5892   /* PREFIX_VEX_0F383C */
   5893   {
   5894     { Bad_Opcode },
   5895     { Bad_Opcode },
   5896     { VEX_W_TABLE (VEX_W_0F383C_P_2) },
   5897   },
   5898 
   5899   /* PREFIX_VEX_0F383D */
   5900   {
   5901     { Bad_Opcode },
   5902     { Bad_Opcode },
   5903     { VEX_W_TABLE (VEX_W_0F383D_P_2) },
   5904   },
   5905 
   5906   /* PREFIX_VEX_0F383E */
   5907   {
   5908     { Bad_Opcode },
   5909     { Bad_Opcode },
   5910     { VEX_W_TABLE (VEX_W_0F383E_P_2) },
   5911   },
   5912 
   5913   /* PREFIX_VEX_0F383F */
   5914   {
   5915     { Bad_Opcode },
   5916     { Bad_Opcode },
   5917     { VEX_W_TABLE (VEX_W_0F383F_P_2) },
   5918   },
   5919 
   5920   /* PREFIX_VEX_0F3840 */
   5921   {
   5922     { Bad_Opcode },
   5923     { Bad_Opcode },
   5924     { VEX_W_TABLE (VEX_W_0F3840_P_2) },
   5925   },
   5926 
   5927   /* PREFIX_VEX_0F3841 */
   5928   {
   5929     { Bad_Opcode },
   5930     { Bad_Opcode },
   5931     { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) },
   5932   },
   5933 
   5934   /* PREFIX_VEX_0F3845 */
   5935   {
   5936     { Bad_Opcode },
   5937     { Bad_Opcode },
   5938     { "vpsrlv%LW", { XM, Vex, EXx }, 0 },
   5939   },
   5940 
   5941   /* PREFIX_VEX_0F3846 */
   5942   {
   5943     { Bad_Opcode },
   5944     { Bad_Opcode },
   5945     { VEX_W_TABLE (VEX_W_0F3846_P_2) },
   5946   },
   5947 
   5948   /* PREFIX_VEX_0F3847 */
   5949   {
   5950     { Bad_Opcode },
   5951     { Bad_Opcode },
   5952     { "vpsllv%LW", { XM, Vex, EXx }, 0 },
   5953   },
   5954 
   5955   /* PREFIX_VEX_0F3858 */
   5956   {
   5957     { Bad_Opcode },
   5958     { Bad_Opcode },
   5959     { VEX_W_TABLE (VEX_W_0F3858_P_2) },
   5960   },
   5961 
   5962   /* PREFIX_VEX_0F3859 */
   5963   {
   5964     { Bad_Opcode },
   5965     { Bad_Opcode },
   5966     { VEX_W_TABLE (VEX_W_0F3859_P_2) },
   5967   },
   5968 
   5969   /* PREFIX_VEX_0F385A */
   5970   {
   5971     { Bad_Opcode },
   5972     { Bad_Opcode },
   5973     { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) },
   5974   },
   5975 
   5976   /* PREFIX_VEX_0F3878 */
   5977   {
   5978     { Bad_Opcode },
   5979     { Bad_Opcode },
   5980     { VEX_W_TABLE (VEX_W_0F3878_P_2) },
   5981   },
   5982 
   5983   /* PREFIX_VEX_0F3879 */
   5984   {
   5985     { Bad_Opcode },
   5986     { Bad_Opcode },
   5987     { VEX_W_TABLE (VEX_W_0F3879_P_2) },
   5988   },
   5989 
   5990   /* PREFIX_VEX_0F388C */
   5991   {
   5992     { Bad_Opcode },
   5993     { Bad_Opcode },
   5994     { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) },
   5995   },
   5996 
   5997   /* PREFIX_VEX_0F388E */
   5998   {
   5999     { Bad_Opcode },
   6000     { Bad_Opcode },
   6001     { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) },
   6002   },
   6003 
   6004   /* PREFIX_VEX_0F3890 */
   6005   {
   6006     { Bad_Opcode },
   6007     { Bad_Opcode },
   6008     { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex }, 0 },
   6009   },
   6010 
   6011   /* PREFIX_VEX_0F3891 */
   6012   {
   6013     { Bad_Opcode },
   6014     { Bad_Opcode },
   6015     { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
   6016   },
   6017 
   6018   /* PREFIX_VEX_0F3892 */
   6019   {
   6020     { Bad_Opcode },
   6021     { Bad_Opcode },
   6022     { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, 0 },
   6023   },
   6024 
   6025   /* PREFIX_VEX_0F3893 */
   6026   {
   6027     { Bad_Opcode },
   6028     { Bad_Opcode },
   6029     { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
   6030   },
   6031 
   6032   /* PREFIX_VEX_0F3896 */
   6033   {
   6034     { Bad_Opcode },
   6035     { Bad_Opcode },
   6036     { "vfmaddsub132p%XW", { XM, Vex, EXx }, 0 },
   6037   },
   6038 
   6039   /* PREFIX_VEX_0F3897 */
   6040   {
   6041     { Bad_Opcode },
   6042     { Bad_Opcode },
   6043     { "vfmsubadd132p%XW", { XM, Vex, EXx }, 0 },
   6044   },
   6045 
   6046   /* PREFIX_VEX_0F3898 */
   6047   {
   6048     { Bad_Opcode },
   6049     { Bad_Opcode },
   6050     { "vfmadd132p%XW", { XM, Vex, EXx }, 0 },
   6051   },
   6052 
   6053   /* PREFIX_VEX_0F3899 */
   6054   {
   6055     { Bad_Opcode },
   6056     { Bad_Opcode },
   6057     { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
   6058   },
   6059 
   6060   /* PREFIX_VEX_0F389A */
   6061   {
   6062     { Bad_Opcode },
   6063     { Bad_Opcode },
   6064     { "vfmsub132p%XW", { XM, Vex, EXx }, 0 },
   6065   },
   6066 
   6067   /* PREFIX_VEX_0F389B */
   6068   {
   6069     { Bad_Opcode },
   6070     { Bad_Opcode },
   6071     { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
   6072   },
   6073 
   6074   /* PREFIX_VEX_0F389C */
   6075   {
   6076     { Bad_Opcode },
   6077     { Bad_Opcode },
   6078     { "vfnmadd132p%XW", { XM, Vex, EXx }, 0 },
   6079   },
   6080 
   6081   /* PREFIX_VEX_0F389D */
   6082   {
   6083     { Bad_Opcode },
   6084     { Bad_Opcode },
   6085     { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
   6086   },
   6087 
   6088   /* PREFIX_VEX_0F389E */
   6089   {
   6090     { Bad_Opcode },
   6091     { Bad_Opcode },
   6092     { "vfnmsub132p%XW", { XM, Vex, EXx }, 0 },
   6093   },
   6094 
   6095   /* PREFIX_VEX_0F389F */
   6096   {
   6097     { Bad_Opcode },
   6098     { Bad_Opcode },
   6099     { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
   6100   },
   6101 
   6102   /* PREFIX_VEX_0F38A6 */
   6103   {
   6104     { Bad_Opcode },
   6105     { Bad_Opcode },
   6106     { "vfmaddsub213p%XW", { XM, Vex, EXx }, 0 },
   6107     { Bad_Opcode },
   6108   },
   6109 
   6110   /* PREFIX_VEX_0F38A7 */
   6111   {
   6112     { Bad_Opcode },
   6113     { Bad_Opcode },
   6114     { "vfmsubadd213p%XW", { XM, Vex, EXx }, 0 },
   6115   },
   6116 
   6117   /* PREFIX_VEX_0F38A8 */
   6118   {
   6119     { Bad_Opcode },
   6120     { Bad_Opcode },
   6121     { "vfmadd213p%XW", { XM, Vex, EXx }, 0 },
   6122   },
   6123 
   6124   /* PREFIX_VEX_0F38A9 */
   6125   {
   6126     { Bad_Opcode },
   6127     { Bad_Opcode },
   6128     { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
   6129   },
   6130 
   6131   /* PREFIX_VEX_0F38AA */
   6132   {
   6133     { Bad_Opcode },
   6134     { Bad_Opcode },
   6135     { "vfmsub213p%XW", { XM, Vex, EXx }, 0 },
   6136   },
   6137 
   6138   /* PREFIX_VEX_0F38AB */
   6139   {
   6140     { Bad_Opcode },
   6141     { Bad_Opcode },
   6142     { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
   6143   },
   6144 
   6145   /* PREFIX_VEX_0F38AC */
   6146   {
   6147     { Bad_Opcode },
   6148     { Bad_Opcode },
   6149     { "vfnmadd213p%XW", { XM, Vex, EXx }, 0 },
   6150   },
   6151 
   6152   /* PREFIX_VEX_0F38AD */
   6153   {
   6154     { Bad_Opcode },
   6155     { Bad_Opcode },
   6156     { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
   6157   },
   6158 
   6159   /* PREFIX_VEX_0F38AE */
   6160   {
   6161     { Bad_Opcode },
   6162     { Bad_Opcode },
   6163     { "vfnmsub213p%XW", { XM, Vex, EXx }, 0 },
   6164   },
   6165 
   6166   /* PREFIX_VEX_0F38AF */
   6167   {
   6168     { Bad_Opcode },
   6169     { Bad_Opcode },
   6170     { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
   6171   },
   6172 
   6173   /* PREFIX_VEX_0F38B6 */
   6174   {
   6175     { Bad_Opcode },
   6176     { Bad_Opcode },
   6177     { "vfmaddsub231p%XW", { XM, Vex, EXx }, 0 },
   6178   },
   6179 
   6180   /* PREFIX_VEX_0F38B7 */
   6181   {
   6182     { Bad_Opcode },
   6183     { Bad_Opcode },
   6184     { "vfmsubadd231p%XW", { XM, Vex, EXx }, 0 },
   6185   },
   6186 
   6187   /* PREFIX_VEX_0F38B8 */
   6188   {
   6189     { Bad_Opcode },
   6190     { Bad_Opcode },
   6191     { "vfmadd231p%XW", { XM, Vex, EXx }, 0 },
   6192   },
   6193 
   6194   /* PREFIX_VEX_0F38B9 */
   6195   {
   6196     { Bad_Opcode },
   6197     { Bad_Opcode },
   6198     { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
   6199   },
   6200 
   6201   /* PREFIX_VEX_0F38BA */
   6202   {
   6203     { Bad_Opcode },
   6204     { Bad_Opcode },
   6205     { "vfmsub231p%XW", { XM, Vex, EXx }, 0 },
   6206   },
   6207 
   6208   /* PREFIX_VEX_0F38BB */
   6209   {
   6210     { Bad_Opcode },
   6211     { Bad_Opcode },
   6212     { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
   6213   },
   6214 
   6215   /* PREFIX_VEX_0F38BC */
   6216   {
   6217     { Bad_Opcode },
   6218     { Bad_Opcode },
   6219     { "vfnmadd231p%XW", { XM, Vex, EXx }, 0 },
   6220   },
   6221 
   6222   /* PREFIX_VEX_0F38BD */
   6223   {
   6224     { Bad_Opcode },
   6225     { Bad_Opcode },
   6226     { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
   6227   },
   6228 
   6229   /* PREFIX_VEX_0F38BE */
   6230   {
   6231     { Bad_Opcode },
   6232     { Bad_Opcode },
   6233     { "vfnmsub231p%XW", { XM, Vex, EXx }, 0 },
   6234   },
   6235 
   6236   /* PREFIX_VEX_0F38BF */
   6237   {
   6238     { Bad_Opcode },
   6239     { Bad_Opcode },
   6240     { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
   6241   },
   6242 
   6243   /* PREFIX_VEX_0F38DB */
   6244   {
   6245     { Bad_Opcode },
   6246     { Bad_Opcode },
   6247     { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) },
   6248   },
   6249 
   6250   /* PREFIX_VEX_0F38DC */
   6251   {
   6252     { Bad_Opcode },
   6253     { Bad_Opcode },
   6254     { VEX_LEN_TABLE (VEX_LEN_0F38DC_P_2) },
   6255   },
   6256 
   6257   /* PREFIX_VEX_0F38DD */
   6258   {
   6259     { Bad_Opcode },
   6260     { Bad_Opcode },
   6261     { VEX_LEN_TABLE (VEX_LEN_0F38DD_P_2) },
   6262   },
   6263 
   6264   /* PREFIX_VEX_0F38DE */
   6265   {
   6266     { Bad_Opcode },
   6267     { Bad_Opcode },
   6268     { VEX_LEN_TABLE (VEX_LEN_0F38DE_P_2) },
   6269   },
   6270 
   6271   /* PREFIX_VEX_0F38DF */
   6272   {
   6273     { Bad_Opcode },
   6274     { Bad_Opcode },
   6275     { VEX_LEN_TABLE (VEX_LEN_0F38DF_P_2) },
   6276   },
   6277 
   6278   /* PREFIX_VEX_0F38F2 */
   6279   {
   6280     { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) },
   6281   },
   6282 
   6283   /* PREFIX_VEX_0F38F3_REG_1 */
   6284   {
   6285     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) },
   6286   },
   6287 
   6288   /* PREFIX_VEX_0F38F3_REG_2 */
   6289   {
   6290     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) },
   6291   },
   6292 
   6293   /* PREFIX_VEX_0F38F3_REG_3 */
   6294   {
   6295     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) },
   6296   },
   6297 
   6298   /* PREFIX_VEX_0F38F5 */
   6299   {
   6300     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
   6301     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
   6302     { Bad_Opcode },
   6303     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
   6304   },
   6305 
   6306   /* PREFIX_VEX_0F38F6 */
   6307   {
   6308     { Bad_Opcode },
   6309     { Bad_Opcode },
   6310     { Bad_Opcode },
   6311     { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
   6312   },
   6313 
   6314   /* PREFIX_VEX_0F38F7 */
   6315   {
   6316     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
   6317     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
   6318     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
   6319     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
   6320   },
   6321 
   6322   /* PREFIX_VEX_0F3A00 */
   6323   {
   6324     { Bad_Opcode },
   6325     { Bad_Opcode },
   6326     { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) },
   6327   },
   6328 
   6329   /* PREFIX_VEX_0F3A01 */
   6330   {
   6331     { Bad_Opcode },
   6332     { Bad_Opcode },
   6333     { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) },
   6334   },
   6335 
   6336   /* PREFIX_VEX_0F3A02 */
   6337   {
   6338     { Bad_Opcode },
   6339     { Bad_Opcode },
   6340     { VEX_W_TABLE (VEX_W_0F3A02_P_2) },
   6341   },
   6342 
   6343   /* PREFIX_VEX_0F3A04 */
   6344   {
   6345     { Bad_Opcode },
   6346     { Bad_Opcode },
   6347     { VEX_W_TABLE (VEX_W_0F3A04_P_2) },
   6348   },
   6349 
   6350   /* PREFIX_VEX_0F3A05 */
   6351   {
   6352     { Bad_Opcode },
   6353     { Bad_Opcode },
   6354     { VEX_W_TABLE (VEX_W_0F3A05_P_2) },
   6355   },
   6356 
   6357   /* PREFIX_VEX_0F3A06 */
   6358   {
   6359     { Bad_Opcode },
   6360     { Bad_Opcode },
   6361     { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) },
   6362   },
   6363 
   6364   /* PREFIX_VEX_0F3A08 */
   6365   {
   6366     { Bad_Opcode },
   6367     { Bad_Opcode },
   6368     { VEX_W_TABLE (VEX_W_0F3A08_P_2) },
   6369   },
   6370 
   6371   /* PREFIX_VEX_0F3A09 */
   6372   {
   6373     { Bad_Opcode },
   6374     { Bad_Opcode },
   6375     { VEX_W_TABLE (VEX_W_0F3A09_P_2) },
   6376   },
   6377 
   6378   /* PREFIX_VEX_0F3A0A */
   6379   {
   6380     { Bad_Opcode },
   6381     { Bad_Opcode },
   6382     { VEX_LEN_TABLE (VEX_LEN_0F3A0A_P_2) },
   6383   },
   6384 
   6385   /* PREFIX_VEX_0F3A0B */
   6386   {
   6387     { Bad_Opcode },
   6388     { Bad_Opcode },
   6389     { VEX_LEN_TABLE (VEX_LEN_0F3A0B_P_2) },
   6390   },
   6391 
   6392   /* PREFIX_VEX_0F3A0C */
   6393   {
   6394     { Bad_Opcode },
   6395     { Bad_Opcode },
   6396     { VEX_W_TABLE (VEX_W_0F3A0C_P_2) },
   6397   },
   6398 
   6399   /* PREFIX_VEX_0F3A0D */
   6400   {
   6401     { Bad_Opcode },
   6402     { Bad_Opcode },
   6403     { VEX_W_TABLE (VEX_W_0F3A0D_P_2) },
   6404   },
   6405 
   6406   /* PREFIX_VEX_0F3A0E */
   6407   {
   6408     { Bad_Opcode },
   6409     { Bad_Opcode },
   6410     { VEX_W_TABLE (VEX_W_0F3A0E_P_2) },
   6411   },
   6412 
   6413   /* PREFIX_VEX_0F3A0F */
   6414   {
   6415     { Bad_Opcode },
   6416     { Bad_Opcode },
   6417     { VEX_W_TABLE (VEX_W_0F3A0F_P_2) },
   6418   },
   6419 
   6420   /* PREFIX_VEX_0F3A14 */
   6421   {
   6422     { Bad_Opcode },
   6423     { Bad_Opcode },
   6424     { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) },
   6425   },
   6426 
   6427   /* PREFIX_VEX_0F3A15 */
   6428   {
   6429     { Bad_Opcode },
   6430     { Bad_Opcode },
   6431     { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) },
   6432   },
   6433 
   6434   /* PREFIX_VEX_0F3A16 */
   6435   {
   6436     { Bad_Opcode },
   6437     { Bad_Opcode },
   6438     { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) },
   6439   },
   6440 
   6441   /* PREFIX_VEX_0F3A17 */
   6442   {
   6443     { Bad_Opcode },
   6444     { Bad_Opcode },
   6445     { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) },
   6446   },
   6447 
   6448   /* PREFIX_VEX_0F3A18 */
   6449   {
   6450     { Bad_Opcode },
   6451     { Bad_Opcode },
   6452     { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) },
   6453   },
   6454 
   6455   /* PREFIX_VEX_0F3A19 */
   6456   {
   6457     { Bad_Opcode },
   6458     { Bad_Opcode },
   6459     { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) },
   6460   },
   6461 
   6462   /* PREFIX_VEX_0F3A1D */
   6463   {
   6464     { Bad_Opcode },
   6465     { Bad_Opcode },
   6466     { "vcvtps2ph", { EXxmmq, XM, Ib }, 0 },
   6467   },
   6468 
   6469   /* PREFIX_VEX_0F3A20 */
   6470   {
   6471     { Bad_Opcode },
   6472     { Bad_Opcode },
   6473     { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) },
   6474   },
   6475 
   6476   /* PREFIX_VEX_0F3A21 */
   6477   {
   6478     { Bad_Opcode },
   6479     { Bad_Opcode },
   6480     { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) },
   6481   },
   6482 
   6483   /* PREFIX_VEX_0F3A22 */
   6484   {
   6485     { Bad_Opcode },
   6486     { Bad_Opcode },
   6487     { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) },
   6488   },
   6489 
   6490   /* PREFIX_VEX_0F3A30 */
   6491   {
   6492     { Bad_Opcode },
   6493     { Bad_Opcode },
   6494     { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) },
   6495   },
   6496 
   6497   /* PREFIX_VEX_0F3A31 */
   6498   {
   6499     { Bad_Opcode },
   6500     { Bad_Opcode },
   6501     { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2) },
   6502   },
   6503 
   6504   /* PREFIX_VEX_0F3A32 */
   6505   {
   6506     { Bad_Opcode },
   6507     { Bad_Opcode },
   6508     { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) },
   6509   },
   6510 
   6511   /* PREFIX_VEX_0F3A33 */
   6512   {
   6513     { Bad_Opcode },
   6514     { Bad_Opcode },
   6515     { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2) },
   6516   },
   6517 
   6518   /* PREFIX_VEX_0F3A38 */
   6519   {
   6520     { Bad_Opcode },
   6521     { Bad_Opcode },
   6522     { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) },
   6523   },
   6524 
   6525   /* PREFIX_VEX_0F3A39 */
   6526   {
   6527     { Bad_Opcode },
   6528     { Bad_Opcode },
   6529     { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) },
   6530   },
   6531 
   6532   /* PREFIX_VEX_0F3A40 */
   6533   {
   6534     { Bad_Opcode },
   6535     { Bad_Opcode },
   6536     { VEX_W_TABLE (VEX_W_0F3A40_P_2) },
   6537   },
   6538 
   6539   /* PREFIX_VEX_0F3A41 */
   6540   {
   6541     { Bad_Opcode },
   6542     { Bad_Opcode },
   6543     { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) },
   6544   },
   6545 
   6546   /* PREFIX_VEX_0F3A42 */
   6547   {
   6548     { Bad_Opcode },
   6549     { Bad_Opcode },
   6550     { VEX_W_TABLE (VEX_W_0F3A42_P_2) },
   6551   },
   6552 
   6553   /* PREFIX_VEX_0F3A44 */
   6554   {
   6555     { Bad_Opcode },
   6556     { Bad_Opcode },
   6557     { VEX_LEN_TABLE (VEX_LEN_0F3A44_P_2) },
   6558   },
   6559 
   6560   /* PREFIX_VEX_0F3A46 */
   6561   {
   6562     { Bad_Opcode },
   6563     { Bad_Opcode },
   6564     { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) },
   6565   },
   6566 
   6567   /* PREFIX_VEX_0F3A48 */
   6568   {
   6569     { Bad_Opcode },
   6570     { Bad_Opcode },
   6571     { VEX_W_TABLE (VEX_W_0F3A48_P_2) },
   6572   },
   6573 
   6574   /* PREFIX_VEX_0F3A49 */
   6575   {
   6576     { Bad_Opcode },
   6577     { Bad_Opcode },
   6578     { VEX_W_TABLE (VEX_W_0F3A49_P_2) },
   6579   },
   6580 
   6581   /* PREFIX_VEX_0F3A4A */
   6582   {
   6583     { Bad_Opcode },
   6584     { Bad_Opcode },
   6585     { VEX_W_TABLE (VEX_W_0F3A4A_P_2) },
   6586   },
   6587 
   6588   /* PREFIX_VEX_0F3A4B */
   6589   {
   6590     { Bad_Opcode },
   6591     { Bad_Opcode },
   6592     { VEX_W_TABLE (VEX_W_0F3A4B_P_2) },
   6593   },
   6594 
   6595   /* PREFIX_VEX_0F3A4C */
   6596   {
   6597     { Bad_Opcode },
   6598     { Bad_Opcode },
   6599     { VEX_W_TABLE (VEX_W_0F3A4C_P_2) },
   6600   },
   6601 
   6602   /* PREFIX_VEX_0F3A5C */
   6603   {
   6604     { Bad_Opcode },
   6605     { Bad_Opcode },
   6606     { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
   6607   },
   6608 
   6609   /* PREFIX_VEX_0F3A5D */
   6610   {
   6611     { Bad_Opcode },
   6612     { Bad_Opcode },
   6613     { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
   6614   },
   6615 
   6616   /* PREFIX_VEX_0F3A5E */
   6617   {
   6618     { Bad_Opcode },
   6619     { Bad_Opcode },
   6620     { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
   6621   },
   6622 
   6623   /* PREFIX_VEX_0F3A5F */
   6624   {
   6625     { Bad_Opcode },
   6626     { Bad_Opcode },
   6627     { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
   6628   },
   6629 
   6630   /* PREFIX_VEX_0F3A60 */
   6631   {
   6632     { Bad_Opcode },
   6633     { Bad_Opcode },
   6634     { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) },
   6635     { Bad_Opcode },
   6636   },
   6637 
   6638   /* PREFIX_VEX_0F3A61 */
   6639   {
   6640     { Bad_Opcode },
   6641     { Bad_Opcode },
   6642     { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) },
   6643   },
   6644 
   6645   /* PREFIX_VEX_0F3A62 */
   6646   {
   6647     { Bad_Opcode },
   6648     { Bad_Opcode },
   6649     { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) },
   6650   },
   6651 
   6652   /* PREFIX_VEX_0F3A63 */
   6653   {
   6654     { Bad_Opcode },
   6655     { Bad_Opcode },
   6656     { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) },
   6657   },
   6658 
   6659   /* PREFIX_VEX_0F3A68 */
   6660   {
   6661     { Bad_Opcode },
   6662     { Bad_Opcode },
   6663     { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
   6664   },
   6665 
   6666   /* PREFIX_VEX_0F3A69 */
   6667   {
   6668     { Bad_Opcode },
   6669     { Bad_Opcode },
   6670     { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
   6671   },
   6672 
   6673   /* PREFIX_VEX_0F3A6A */
   6674   {
   6675     { Bad_Opcode },
   6676     { Bad_Opcode },
   6677     { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) },
   6678   },
   6679 
   6680   /* PREFIX_VEX_0F3A6B */
   6681   {
   6682     { Bad_Opcode },
   6683     { Bad_Opcode },
   6684     { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) },
   6685   },
   6686 
   6687   /* PREFIX_VEX_0F3A6C */
   6688   {
   6689     { Bad_Opcode },
   6690     { Bad_Opcode },
   6691     { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
   6692   },
   6693 
   6694   /* PREFIX_VEX_0F3A6D */
   6695   {
   6696     { Bad_Opcode },
   6697     { Bad_Opcode },
   6698     { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
   6699   },
   6700 
   6701   /* PREFIX_VEX_0F3A6E */
   6702   {
   6703     { Bad_Opcode },
   6704     { Bad_Opcode },
   6705     { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) },
   6706   },
   6707 
   6708   /* PREFIX_VEX_0F3A6F */
   6709   {
   6710     { Bad_Opcode },
   6711     { Bad_Opcode },
   6712     { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) },
   6713   },
   6714 
   6715   /* PREFIX_VEX_0F3A78 */
   6716   {
   6717     { Bad_Opcode },
   6718     { Bad_Opcode },
   6719     { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
   6720   },
   6721 
   6722   /* PREFIX_VEX_0F3A79 */
   6723   {
   6724     { Bad_Opcode },
   6725     { Bad_Opcode },
   6726     { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
   6727   },
   6728 
   6729   /* PREFIX_VEX_0F3A7A */
   6730   {
   6731     { Bad_Opcode },
   6732     { Bad_Opcode },
   6733     { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) },
   6734   },
   6735 
   6736   /* PREFIX_VEX_0F3A7B */
   6737   {
   6738     { Bad_Opcode },
   6739     { Bad_Opcode },
   6740     { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) },
   6741   },
   6742 
   6743   /* PREFIX_VEX_0F3A7C */
   6744   {
   6745     { Bad_Opcode },
   6746     { Bad_Opcode },
   6747     { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
   6748     { Bad_Opcode },
   6749   },
   6750 
   6751   /* PREFIX_VEX_0F3A7D */
   6752   {
   6753     { Bad_Opcode },
   6754     { Bad_Opcode },
   6755     { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
   6756   },
   6757 
   6758   /* PREFIX_VEX_0F3A7E */
   6759   {
   6760     { Bad_Opcode },
   6761     { Bad_Opcode },
   6762     { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) },
   6763   },
   6764 
   6765   /* PREFIX_VEX_0F3A7F */
   6766   {
   6767     { Bad_Opcode },
   6768     { Bad_Opcode },
   6769     { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) },
   6770   },
   6771 
   6772   /* PREFIX_VEX_0F3ADF */
   6773   {
   6774     { Bad_Opcode },
   6775     { Bad_Opcode },
   6776     { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
   6777   },
   6778 
   6779   /* PREFIX_VEX_0F3AF0 */
   6780   {
   6781     { Bad_Opcode },
   6782     { Bad_Opcode },
   6783     { Bad_Opcode },
   6784     { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
   6785   },
   6786 
   6787 #define NEED_PREFIX_TABLE
   6788 #include "i386-dis-evex.h"
   6789 #undef NEED_PREFIX_TABLE
   6790 };
   6791 
   6792 static const struct dis386 x86_64_table[][2] = {
   6793   /* X86_64_06 */
   6794   {
   6795     { "pushP", { es }, 0 },
   6796   },
   6797 
   6798   /* X86_64_07 */
   6799   {
   6800     { "popP", { es }, 0 },
   6801   },
   6802 
   6803   /* X86_64_0D */
   6804   {
   6805     { "pushP", { cs }, 0 },
   6806   },
   6807 
   6808   /* X86_64_16 */
   6809   {
   6810     { "pushP", { ss }, 0 },
   6811   },
   6812 
   6813   /* X86_64_17 */
   6814   {
   6815     { "popP", { ss }, 0 },
   6816   },
   6817 
   6818   /* X86_64_1E */
   6819   {
   6820     { "pushP", { ds }, 0 },
   6821   },
   6822 
   6823   /* X86_64_1F */
   6824   {
   6825     { "popP", { ds }, 0 },
   6826   },
   6827 
   6828   /* X86_64_27 */
   6829   {
   6830     { "daa", { XX }, 0 },
   6831   },
   6832 
   6833   /* X86_64_2F */
   6834   {
   6835     { "das", { XX }, 0 },
   6836   },
   6837 
   6838   /* X86_64_37 */
   6839   {
   6840     { "aaa", { XX }, 0 },
   6841   },
   6842 
   6843   /* X86_64_3F */
   6844   {
   6845     { "aas", { XX }, 0 },
   6846   },
   6847 
   6848   /* X86_64_60 */
   6849   {
   6850     { "pushaP", { XX }, 0 },
   6851   },
   6852 
   6853   /* X86_64_61 */
   6854   {
   6855     { "popaP", { XX }, 0 },
   6856   },
   6857 
   6858   /* X86_64_62 */
   6859   {
   6860     { MOD_TABLE (MOD_62_32BIT) },
   6861     { EVEX_TABLE (EVEX_0F) },
   6862   },
   6863 
   6864   /* X86_64_63 */
   6865   {
   6866     { "arpl", { Ew, Gw }, 0 },
   6867     { "movs{lq|xd}", { Gv, Ed }, 0 },
   6868   },
   6869 
   6870   /* X86_64_6D */
   6871   {
   6872     { "ins{R|}", { Yzr, indirDX }, 0 },
   6873     { "ins{G|}", { Yzr, indirDX }, 0 },
   6874   },
   6875 
   6876   /* X86_64_6F */
   6877   {
   6878     { "outs{R|}", { indirDXr, Xz }, 0 },
   6879     { "outs{G|}", { indirDXr, Xz }, 0 },
   6880   },
   6881 
   6882   /* X86_64_9A */
   6883   {
   6884     { "Jcall{T|}", { Ap }, 0 },
   6885   },
   6886 
   6887   /* X86_64_C4 */
   6888   {
   6889     { MOD_TABLE (MOD_C4_32BIT) },
   6890     { VEX_C4_TABLE (VEX_0F) },
   6891   },
   6892 
   6893   /* X86_64_C5 */
   6894   {
   6895     { MOD_TABLE (MOD_C5_32BIT) },
   6896     { VEX_C5_TABLE (VEX_0F) },
   6897   },
   6898 
   6899   /* X86_64_CE */
   6900   {
   6901     { "into", { XX }, 0 },
   6902   },
   6903 
   6904   /* X86_64_D4 */
   6905   {
   6906     { "aam", { Ib }, 0 },
   6907   },
   6908 
   6909   /* X86_64_D5 */
   6910   {
   6911     { "aad", { Ib }, 0 },
   6912   },
   6913 
   6914   /* X86_64_E8 */
   6915   {
   6916     { "callP",		{ Jv, BND }, 0 },
   6917     { "call@",		{ Jv, BND }, 0 }
   6918   },
   6919 
   6920   /* X86_64_E9 */
   6921   {
   6922     { "jmpP",		{ Jv, BND }, 0 },
   6923     { "jmp@",		{ Jv, BND }, 0 }
   6924   },
   6925 
   6926   /* X86_64_EA */
   6927   {
   6928     { "Jjmp{T|}", { Ap }, 0 },
   6929   },
   6930 
   6931   /* X86_64_0F01_REG_0 */
   6932   {
   6933     { "sgdt{Q|IQ}", { M }, 0 },
   6934     { "sgdt", { M }, 0 },
   6935   },
   6936 
   6937   /* X86_64_0F01_REG_1 */
   6938   {
   6939     { "sidt{Q|IQ}", { M }, 0 },
   6940     { "sidt", { M }, 0 },
   6941   },
   6942 
   6943   /* X86_64_0F01_REG_2 */
   6944   {
   6945     { "lgdt{Q|Q}", { M }, 0 },
   6946     { "lgdt", { M }, 0 },
   6947   },
   6948 
   6949   /* X86_64_0F01_REG_3 */
   6950   {
   6951     { "lidt{Q|Q}", { M }, 0 },
   6952     { "lidt", { M }, 0 },
   6953   },
   6954 };
   6955 
   6956 static const struct dis386 three_byte_table[][256] = {
   6957 
   6958   /* THREE_BYTE_0F38 */
   6959   {
   6960     /* 00 */
   6961     { "pshufb",		{ MX, EM }, PREFIX_OPCODE },
   6962     { "phaddw",		{ MX, EM }, PREFIX_OPCODE },
   6963     { "phaddd",		{ MX, EM }, PREFIX_OPCODE },
   6964     { "phaddsw",	{ MX, EM }, PREFIX_OPCODE },
   6965     { "pmaddubsw",	{ MX, EM }, PREFIX_OPCODE },
   6966     { "phsubw",		{ MX, EM }, PREFIX_OPCODE },
   6967     { "phsubd",		{ MX, EM }, PREFIX_OPCODE },
   6968     { "phsubsw",	{ MX, EM }, PREFIX_OPCODE },
   6969     /* 08 */
   6970     { "psignb",		{ MX, EM }, PREFIX_OPCODE },
   6971     { "psignw",		{ MX, EM }, PREFIX_OPCODE },
   6972     { "psignd",		{ MX, EM }, PREFIX_OPCODE },
   6973     { "pmulhrsw",	{ MX, EM }, PREFIX_OPCODE },
   6974     { Bad_Opcode },
   6975     { Bad_Opcode },
   6976     { Bad_Opcode },
   6977     { Bad_Opcode },
   6978     /* 10 */
   6979     { PREFIX_TABLE (PREFIX_0F3810) },
   6980     { Bad_Opcode },
   6981     { Bad_Opcode },
   6982     { Bad_Opcode },
   6983     { PREFIX_TABLE (PREFIX_0F3814) },
   6984     { PREFIX_TABLE (PREFIX_0F3815) },
   6985     { Bad_Opcode },
   6986     { PREFIX_TABLE (PREFIX_0F3817) },
   6987     /* 18 */
   6988     { Bad_Opcode },
   6989     { Bad_Opcode },
   6990     { Bad_Opcode },
   6991     { Bad_Opcode },
   6992     { "pabsb",		{ MX, EM }, PREFIX_OPCODE },
   6993     { "pabsw",		{ MX, EM }, PREFIX_OPCODE },
   6994     { "pabsd",		{ MX, EM }, PREFIX_OPCODE },
   6995     { Bad_Opcode },
   6996     /* 20 */
   6997     { PREFIX_TABLE (PREFIX_0F3820) },
   6998     { PREFIX_TABLE (PREFIX_0F3821) },
   6999     { PREFIX_TABLE (PREFIX_0F3822) },
   7000     { PREFIX_TABLE (PREFIX_0F3823) },
   7001     { PREFIX_TABLE (PREFIX_0F3824) },
   7002     { PREFIX_TABLE (PREFIX_0F3825) },
   7003     { Bad_Opcode },
   7004     { Bad_Opcode },
   7005     /* 28 */
   7006     { PREFIX_TABLE (PREFIX_0F3828) },
   7007     { PREFIX_TABLE (PREFIX_0F3829) },
   7008     { PREFIX_TABLE (PREFIX_0F382A) },
   7009     { PREFIX_TABLE (PREFIX_0F382B) },
   7010     { Bad_Opcode },
   7011     { Bad_Opcode },
   7012     { Bad_Opcode },
   7013     { Bad_Opcode },
   7014     /* 30 */
   7015     { PREFIX_TABLE (PREFIX_0F3830) },
   7016     { PREFIX_TABLE (PREFIX_0F3831) },
   7017     { PREFIX_TABLE (PREFIX_0F3832) },
   7018     { PREFIX_TABLE (PREFIX_0F3833) },
   7019     { PREFIX_TABLE (PREFIX_0F3834) },
   7020     { PREFIX_TABLE (PREFIX_0F3835) },
   7021     { Bad_Opcode },
   7022     { PREFIX_TABLE (PREFIX_0F3837) },
   7023     /* 38 */
   7024     { PREFIX_TABLE (PREFIX_0F3838) },
   7025     { PREFIX_TABLE (PREFIX_0F3839) },
   7026     { PREFIX_TABLE (PREFIX_0F383A) },
   7027     { PREFIX_TABLE (PREFIX_0F383B) },
   7028     { PREFIX_TABLE (PREFIX_0F383C) },
   7029     { PREFIX_TABLE (PREFIX_0F383D) },
   7030     { PREFIX_TABLE (PREFIX_0F383E) },
   7031     { PREFIX_TABLE (PREFIX_0F383F) },
   7032     /* 40 */
   7033     { PREFIX_TABLE (PREFIX_0F3840) },
   7034     { PREFIX_TABLE (PREFIX_0F3841) },
   7035     { Bad_Opcode },
   7036     { Bad_Opcode },
   7037     { Bad_Opcode },
   7038     { Bad_Opcode },
   7039     { Bad_Opcode },
   7040     { Bad_Opcode },
   7041     /* 48 */
   7042     { Bad_Opcode },
   7043     { Bad_Opcode },
   7044     { Bad_Opcode },
   7045     { Bad_Opcode },
   7046     { Bad_Opcode },
   7047     { Bad_Opcode },
   7048     { Bad_Opcode },
   7049     { Bad_Opcode },
   7050     /* 50 */
   7051     { Bad_Opcode },
   7052     { Bad_Opcode },
   7053     { Bad_Opcode },
   7054     { Bad_Opcode },
   7055     { Bad_Opcode },
   7056     { Bad_Opcode },
   7057     { Bad_Opcode },
   7058     { Bad_Opcode },
   7059     /* 58 */
   7060     { Bad_Opcode },
   7061     { Bad_Opcode },
   7062     { Bad_Opcode },
   7063     { Bad_Opcode },
   7064     { Bad_Opcode },
   7065     { Bad_Opcode },
   7066     { Bad_Opcode },
   7067     { Bad_Opcode },
   7068     /* 60 */
   7069     { Bad_Opcode },
   7070     { Bad_Opcode },
   7071     { Bad_Opcode },
   7072     { Bad_Opcode },
   7073     { Bad_Opcode },
   7074     { Bad_Opcode },
   7075     { Bad_Opcode },
   7076     { Bad_Opcode },
   7077     /* 68 */
   7078     { Bad_Opcode },
   7079     { Bad_Opcode },
   7080     { Bad_Opcode },
   7081     { Bad_Opcode },
   7082     { Bad_Opcode },
   7083     { Bad_Opcode },
   7084     { Bad_Opcode },
   7085     { Bad_Opcode },
   7086     /* 70 */
   7087     { Bad_Opcode },
   7088     { Bad_Opcode },
   7089     { Bad_Opcode },
   7090     { Bad_Opcode },
   7091     { Bad_Opcode },
   7092     { Bad_Opcode },
   7093     { Bad_Opcode },
   7094     { Bad_Opcode },
   7095     /* 78 */
   7096     { Bad_Opcode },
   7097     { Bad_Opcode },
   7098     { Bad_Opcode },
   7099     { Bad_Opcode },
   7100     { Bad_Opcode },
   7101     { Bad_Opcode },
   7102     { Bad_Opcode },
   7103     { Bad_Opcode },
   7104     /* 80 */
   7105     { PREFIX_TABLE (PREFIX_0F3880) },
   7106     { PREFIX_TABLE (PREFIX_0F3881) },
   7107     { PREFIX_TABLE (PREFIX_0F3882) },
   7108     { Bad_Opcode },
   7109     { Bad_Opcode },
   7110     { Bad_Opcode },
   7111     { Bad_Opcode },
   7112     { Bad_Opcode },
   7113     /* 88 */
   7114     { Bad_Opcode },
   7115     { Bad_Opcode },
   7116     { Bad_Opcode },
   7117     { Bad_Opcode },
   7118     { Bad_Opcode },
   7119     { Bad_Opcode },
   7120     { Bad_Opcode },
   7121     { Bad_Opcode },
   7122     /* 90 */
   7123     { Bad_Opcode },
   7124     { Bad_Opcode },
   7125     { Bad_Opcode },
   7126     { Bad_Opcode },
   7127     { Bad_Opcode },
   7128     { Bad_Opcode },
   7129     { Bad_Opcode },
   7130     { Bad_Opcode },
   7131     /* 98 */
   7132     { Bad_Opcode },
   7133     { Bad_Opcode },
   7134     { Bad_Opcode },
   7135     { Bad_Opcode },
   7136     { Bad_Opcode },
   7137     { Bad_Opcode },
   7138     { Bad_Opcode },
   7139     { Bad_Opcode },
   7140     /* a0 */
   7141     { Bad_Opcode },
   7142     { Bad_Opcode },
   7143     { Bad_Opcode },
   7144     { Bad_Opcode },
   7145     { Bad_Opcode },
   7146     { Bad_Opcode },
   7147     { Bad_Opcode },
   7148     { Bad_Opcode },
   7149     /* a8 */
   7150     { Bad_Opcode },
   7151     { Bad_Opcode },
   7152     { Bad_Opcode },
   7153     { Bad_Opcode },
   7154     { Bad_Opcode },
   7155     { Bad_Opcode },
   7156     { Bad_Opcode },
   7157     { Bad_Opcode },
   7158     /* b0 */
   7159     { Bad_Opcode },
   7160     { Bad_Opcode },
   7161     { Bad_Opcode },
   7162     { Bad_Opcode },
   7163     { Bad_Opcode },
   7164     { Bad_Opcode },
   7165     { Bad_Opcode },
   7166     { Bad_Opcode },
   7167     /* b8 */
   7168     { Bad_Opcode },
   7169     { Bad_Opcode },
   7170     { Bad_Opcode },
   7171     { Bad_Opcode },
   7172     { Bad_Opcode },
   7173     { Bad_Opcode },
   7174     { Bad_Opcode },
   7175     { Bad_Opcode },
   7176     /* c0 */
   7177     { Bad_Opcode },
   7178     { Bad_Opcode },
   7179     { Bad_Opcode },
   7180     { Bad_Opcode },
   7181     { Bad_Opcode },
   7182     { Bad_Opcode },
   7183     { Bad_Opcode },
   7184     { Bad_Opcode },
   7185     /* c8 */
   7186     { PREFIX_TABLE (PREFIX_0F38C8) },
   7187     { PREFIX_TABLE (PREFIX_0F38C9) },
   7188     { PREFIX_TABLE (PREFIX_0F38CA) },
   7189     { PREFIX_TABLE (PREFIX_0F38CB) },
   7190     { PREFIX_TABLE (PREFIX_0F38CC) },
   7191     { PREFIX_TABLE (PREFIX_0F38CD) },
   7192     { Bad_Opcode },
   7193     { Bad_Opcode },
   7194     /* d0 */
   7195     { Bad_Opcode },
   7196     { Bad_Opcode },
   7197     { Bad_Opcode },
   7198     { Bad_Opcode },
   7199     { Bad_Opcode },
   7200     { Bad_Opcode },
   7201     { Bad_Opcode },
   7202     { Bad_Opcode },
   7203     /* d8 */
   7204     { Bad_Opcode },
   7205     { Bad_Opcode },
   7206     { Bad_Opcode },
   7207     { PREFIX_TABLE (PREFIX_0F38DB) },
   7208     { PREFIX_TABLE (PREFIX_0F38DC) },
   7209     { PREFIX_TABLE (PREFIX_0F38DD) },
   7210     { PREFIX_TABLE (PREFIX_0F38DE) },
   7211     { PREFIX_TABLE (PREFIX_0F38DF) },
   7212     /* e0 */
   7213     { Bad_Opcode },
   7214     { Bad_Opcode },
   7215     { Bad_Opcode },
   7216     { Bad_Opcode },
   7217     { Bad_Opcode },
   7218     { Bad_Opcode },
   7219     { Bad_Opcode },
   7220     { Bad_Opcode },
   7221     /* e8 */
   7222     { Bad_Opcode },
   7223     { Bad_Opcode },
   7224     { Bad_Opcode },
   7225     { Bad_Opcode },
   7226     { Bad_Opcode },
   7227     { Bad_Opcode },
   7228     { Bad_Opcode },
   7229     { Bad_Opcode },
   7230     /* f0 */
   7231     { PREFIX_TABLE (PREFIX_0F38F0) },
   7232     { PREFIX_TABLE (PREFIX_0F38F1) },
   7233     { Bad_Opcode },
   7234     { Bad_Opcode },
   7235     { Bad_Opcode },
   7236     { Bad_Opcode },
   7237     { PREFIX_TABLE (PREFIX_0F38F6) },
   7238     { Bad_Opcode },
   7239     /* f8 */
   7240     { Bad_Opcode },
   7241     { Bad_Opcode },
   7242     { Bad_Opcode },
   7243     { Bad_Opcode },
   7244     { Bad_Opcode },
   7245     { Bad_Opcode },
   7246     { Bad_Opcode },
   7247     { Bad_Opcode },
   7248   },
   7249   /* THREE_BYTE_0F3A */
   7250   {
   7251     /* 00 */
   7252     { Bad_Opcode },
   7253     { Bad_Opcode },
   7254     { Bad_Opcode },
   7255     { Bad_Opcode },
   7256     { Bad_Opcode },
   7257     { Bad_Opcode },
   7258     { Bad_Opcode },
   7259     { Bad_Opcode },
   7260     /* 08 */
   7261     { PREFIX_TABLE (PREFIX_0F3A08) },
   7262     { PREFIX_TABLE (PREFIX_0F3A09) },
   7263     { PREFIX_TABLE (PREFIX_0F3A0A) },
   7264     { PREFIX_TABLE (PREFIX_0F3A0B) },
   7265     { PREFIX_TABLE (PREFIX_0F3A0C) },
   7266     { PREFIX_TABLE (PREFIX_0F3A0D) },
   7267     { PREFIX_TABLE (PREFIX_0F3A0E) },
   7268     { "palignr",	{ MX, EM, Ib }, PREFIX_OPCODE },
   7269     /* 10 */
   7270     { Bad_Opcode },
   7271     { Bad_Opcode },
   7272     { Bad_Opcode },
   7273     { Bad_Opcode },
   7274     { PREFIX_TABLE (PREFIX_0F3A14) },
   7275     { PREFIX_TABLE (PREFIX_0F3A15) },
   7276     { PREFIX_TABLE (PREFIX_0F3A16) },
   7277     { PREFIX_TABLE (PREFIX_0F3A17) },
   7278     /* 18 */
   7279     { Bad_Opcode },
   7280     { Bad_Opcode },
   7281     { Bad_Opcode },
   7282     { Bad_Opcode },
   7283     { Bad_Opcode },
   7284     { Bad_Opcode },
   7285     { Bad_Opcode },
   7286     { Bad_Opcode },
   7287     /* 20 */
   7288     { PREFIX_TABLE (PREFIX_0F3A20) },
   7289     { PREFIX_TABLE (PREFIX_0F3A21) },
   7290     { PREFIX_TABLE (PREFIX_0F3A22) },
   7291     { Bad_Opcode },
   7292     { Bad_Opcode },
   7293     { Bad_Opcode },
   7294     { Bad_Opcode },
   7295     { Bad_Opcode },
   7296     /* 28 */
   7297     { Bad_Opcode },
   7298     { Bad_Opcode },
   7299     { Bad_Opcode },
   7300     { Bad_Opcode },
   7301     { Bad_Opcode },
   7302     { Bad_Opcode },
   7303     { Bad_Opcode },
   7304     { Bad_Opcode },
   7305     /* 30 */
   7306     { Bad_Opcode },
   7307     { Bad_Opcode },
   7308     { Bad_Opcode },
   7309     { Bad_Opcode },
   7310     { Bad_Opcode },
   7311     { Bad_Opcode },
   7312     { Bad_Opcode },
   7313     { Bad_Opcode },
   7314     /* 38 */
   7315     { Bad_Opcode },
   7316     { Bad_Opcode },
   7317     { Bad_Opcode },
   7318     { Bad_Opcode },
   7319     { Bad_Opcode },
   7320     { Bad_Opcode },
   7321     { Bad_Opcode },
   7322     { Bad_Opcode },
   7323     /* 40 */
   7324     { PREFIX_TABLE (PREFIX_0F3A40) },
   7325     { PREFIX_TABLE (PREFIX_0F3A41) },
   7326     { PREFIX_TABLE (PREFIX_0F3A42) },
   7327     { Bad_Opcode },
   7328     { PREFIX_TABLE (PREFIX_0F3A44) },
   7329     { Bad_Opcode },
   7330     { Bad_Opcode },
   7331     { Bad_Opcode },
   7332     /* 48 */
   7333     { Bad_Opcode },
   7334     { Bad_Opcode },
   7335     { Bad_Opcode },
   7336     { Bad_Opcode },
   7337     { Bad_Opcode },
   7338     { Bad_Opcode },
   7339     { Bad_Opcode },
   7340     { Bad_Opcode },
   7341     /* 50 */
   7342     { Bad_Opcode },
   7343     { Bad_Opcode },
   7344     { Bad_Opcode },
   7345     { Bad_Opcode },
   7346     { Bad_Opcode },
   7347     { Bad_Opcode },
   7348     { Bad_Opcode },
   7349     { Bad_Opcode },
   7350     /* 58 */
   7351     { Bad_Opcode },
   7352     { Bad_Opcode },
   7353     { Bad_Opcode },
   7354     { Bad_Opcode },
   7355     { Bad_Opcode },
   7356     { Bad_Opcode },
   7357     { Bad_Opcode },
   7358     { Bad_Opcode },
   7359     /* 60 */
   7360     { PREFIX_TABLE (PREFIX_0F3A60) },
   7361     { PREFIX_TABLE (PREFIX_0F3A61) },
   7362     { PREFIX_TABLE (PREFIX_0F3A62) },
   7363     { PREFIX_TABLE (PREFIX_0F3A63) },
   7364     { Bad_Opcode },
   7365     { Bad_Opcode },
   7366     { Bad_Opcode },
   7367     { Bad_Opcode },
   7368     /* 68 */
   7369     { Bad_Opcode },
   7370     { Bad_Opcode },
   7371     { Bad_Opcode },
   7372     { Bad_Opcode },
   7373     { Bad_Opcode },
   7374     { Bad_Opcode },
   7375     { Bad_Opcode },
   7376     { Bad_Opcode },
   7377     /* 70 */
   7378     { Bad_Opcode },
   7379     { Bad_Opcode },
   7380     { Bad_Opcode },
   7381     { Bad_Opcode },
   7382     { Bad_Opcode },
   7383     { Bad_Opcode },
   7384     { Bad_Opcode },
   7385     { Bad_Opcode },
   7386     /* 78 */
   7387     { Bad_Opcode },
   7388     { Bad_Opcode },
   7389     { Bad_Opcode },
   7390     { Bad_Opcode },
   7391     { Bad_Opcode },
   7392     { Bad_Opcode },
   7393     { Bad_Opcode },
   7394     { Bad_Opcode },
   7395     /* 80 */
   7396     { Bad_Opcode },
   7397     { Bad_Opcode },
   7398     { Bad_Opcode },
   7399     { Bad_Opcode },
   7400     { Bad_Opcode },
   7401     { Bad_Opcode },
   7402     { Bad_Opcode },
   7403     { Bad_Opcode },
   7404     /* 88 */
   7405     { Bad_Opcode },
   7406     { Bad_Opcode },
   7407     { Bad_Opcode },
   7408     { Bad_Opcode },
   7409     { Bad_Opcode },
   7410     { Bad_Opcode },
   7411     { Bad_Opcode },
   7412     { Bad_Opcode },
   7413     /* 90 */
   7414     { Bad_Opcode },
   7415     { Bad_Opcode },
   7416     { Bad_Opcode },
   7417     { Bad_Opcode },
   7418     { Bad_Opcode },
   7419     { Bad_Opcode },
   7420     { Bad_Opcode },
   7421     { Bad_Opcode },
   7422     /* 98 */
   7423     { Bad_Opcode },
   7424     { Bad_Opcode },
   7425     { Bad_Opcode },
   7426     { Bad_Opcode },
   7427     { Bad_Opcode },
   7428     { Bad_Opcode },
   7429     { Bad_Opcode },
   7430     { Bad_Opcode },
   7431     /* a0 */
   7432     { Bad_Opcode },
   7433     { Bad_Opcode },
   7434     { Bad_Opcode },
   7435     { Bad_Opcode },
   7436     { Bad_Opcode },
   7437     { Bad_Opcode },
   7438     { Bad_Opcode },
   7439     { Bad_Opcode },
   7440     /* a8 */
   7441     { Bad_Opcode },
   7442     { Bad_Opcode },
   7443     { Bad_Opcode },
   7444     { Bad_Opcode },
   7445     { Bad_Opcode },
   7446     { Bad_Opcode },
   7447     { Bad_Opcode },
   7448     { Bad_Opcode },
   7449     /* b0 */
   7450     { Bad_Opcode },
   7451     { Bad_Opcode },
   7452     { Bad_Opcode },
   7453     { Bad_Opcode },
   7454     { Bad_Opcode },
   7455     { Bad_Opcode },
   7456     { Bad_Opcode },
   7457     { Bad_Opcode },
   7458     /* b8 */
   7459     { Bad_Opcode },
   7460     { Bad_Opcode },
   7461     { Bad_Opcode },
   7462     { Bad_Opcode },
   7463     { Bad_Opcode },
   7464     { Bad_Opcode },
   7465     { Bad_Opcode },
   7466     { Bad_Opcode },
   7467     /* c0 */
   7468     { Bad_Opcode },
   7469     { Bad_Opcode },
   7470     { Bad_Opcode },
   7471     { Bad_Opcode },
   7472     { Bad_Opcode },
   7473     { Bad_Opcode },
   7474     { Bad_Opcode },
   7475     { Bad_Opcode },
   7476     /* c8 */
   7477     { Bad_Opcode },
   7478     { Bad_Opcode },
   7479     { Bad_Opcode },
   7480     { Bad_Opcode },
   7481     { PREFIX_TABLE (PREFIX_0F3ACC) },
   7482     { Bad_Opcode },
   7483     { Bad_Opcode },
   7484     { Bad_Opcode },
   7485     /* d0 */
   7486     { Bad_Opcode },
   7487     { Bad_Opcode },
   7488     { Bad_Opcode },
   7489     { Bad_Opcode },
   7490     { Bad_Opcode },
   7491     { Bad_Opcode },
   7492     { Bad_Opcode },
   7493     { Bad_Opcode },
   7494     /* d8 */
   7495     { Bad_Opcode },
   7496     { Bad_Opcode },
   7497     { Bad_Opcode },
   7498     { Bad_Opcode },
   7499     { Bad_Opcode },
   7500     { Bad_Opcode },
   7501     { Bad_Opcode },
   7502     { PREFIX_TABLE (PREFIX_0F3ADF) },
   7503     /* e0 */
   7504     { Bad_Opcode },
   7505     { Bad_Opcode },
   7506     { Bad_Opcode },
   7507     { Bad_Opcode },
   7508     { Bad_Opcode },
   7509     { Bad_Opcode },
   7510     { Bad_Opcode },
   7511     { Bad_Opcode },
   7512     /* e8 */
   7513     { Bad_Opcode },
   7514     { Bad_Opcode },
   7515     { Bad_Opcode },
   7516     { Bad_Opcode },
   7517     { Bad_Opcode },
   7518     { Bad_Opcode },
   7519     { Bad_Opcode },
   7520     { Bad_Opcode },
   7521     /* f0 */
   7522     { Bad_Opcode },
   7523     { Bad_Opcode },
   7524     { Bad_Opcode },
   7525     { Bad_Opcode },
   7526     { Bad_Opcode },
   7527     { Bad_Opcode },
   7528     { Bad_Opcode },
   7529     { Bad_Opcode },
   7530     /* f8 */
   7531     { Bad_Opcode },
   7532     { Bad_Opcode },
   7533     { Bad_Opcode },
   7534     { Bad_Opcode },
   7535     { Bad_Opcode },
   7536     { Bad_Opcode },
   7537     { Bad_Opcode },
   7538     { Bad_Opcode },
   7539   },
   7540 
   7541   /* THREE_BYTE_0F7A */
   7542   {
   7543     /* 00 */
   7544     { Bad_Opcode },
   7545     { Bad_Opcode },
   7546     { Bad_Opcode },
   7547     { Bad_Opcode },
   7548     { Bad_Opcode },
   7549     { Bad_Opcode },
   7550     { Bad_Opcode },
   7551     { Bad_Opcode },
   7552     /* 08 */
   7553     { Bad_Opcode },
   7554     { Bad_Opcode },
   7555     { Bad_Opcode },
   7556     { Bad_Opcode },
   7557     { Bad_Opcode },
   7558     { Bad_Opcode },
   7559     { Bad_Opcode },
   7560     { Bad_Opcode },
   7561     /* 10 */
   7562     { Bad_Opcode },
   7563     { Bad_Opcode },
   7564     { Bad_Opcode },
   7565     { Bad_Opcode },
   7566     { Bad_Opcode },
   7567     { Bad_Opcode },
   7568     { Bad_Opcode },
   7569     { Bad_Opcode },
   7570     /* 18 */
   7571     { Bad_Opcode },
   7572     { Bad_Opcode },
   7573     { Bad_Opcode },
   7574     { Bad_Opcode },
   7575     { Bad_Opcode },
   7576     { Bad_Opcode },
   7577     { Bad_Opcode },
   7578     { Bad_Opcode },
   7579     /* 20 */
   7580     { "ptest",		{ XX }, PREFIX_OPCODE },
   7581     { Bad_Opcode },
   7582     { Bad_Opcode },
   7583     { Bad_Opcode },
   7584     { Bad_Opcode },
   7585     { Bad_Opcode },
   7586     { Bad_Opcode },
   7587     { Bad_Opcode },
   7588     /* 28 */
   7589     { Bad_Opcode },
   7590     { Bad_Opcode },
   7591     { Bad_Opcode },
   7592     { Bad_Opcode },
   7593     { Bad_Opcode },
   7594     { Bad_Opcode },
   7595     { Bad_Opcode },
   7596     { Bad_Opcode },
   7597     /* 30 */
   7598     { Bad_Opcode },
   7599     { Bad_Opcode },
   7600     { Bad_Opcode },
   7601     { Bad_Opcode },
   7602     { Bad_Opcode },
   7603     { Bad_Opcode },
   7604     { Bad_Opcode },
   7605     { Bad_Opcode },
   7606     /* 38 */
   7607     { Bad_Opcode },
   7608     { Bad_Opcode },
   7609     { Bad_Opcode },
   7610     { Bad_Opcode },
   7611     { Bad_Opcode },
   7612     { Bad_Opcode },
   7613     { Bad_Opcode },
   7614     { Bad_Opcode },
   7615     /* 40 */
   7616     { Bad_Opcode },
   7617     { "phaddbw",	{ XM, EXq }, PREFIX_OPCODE },
   7618     { "phaddbd",	{ XM, EXq }, PREFIX_OPCODE },
   7619     { "phaddbq",	{ XM, EXq }, PREFIX_OPCODE },
   7620     { Bad_Opcode },
   7621     { Bad_Opcode },
   7622     { "phaddwd",	{ XM, EXq }, PREFIX_OPCODE },
   7623     { "phaddwq",	{ XM, EXq }, PREFIX_OPCODE },
   7624     /* 48 */
   7625     { Bad_Opcode },
   7626     { Bad_Opcode },
   7627     { Bad_Opcode },
   7628     { "phadddq",	{ XM, EXq }, PREFIX_OPCODE },
   7629     { Bad_Opcode },
   7630     { Bad_Opcode },
   7631     { Bad_Opcode },
   7632     { Bad_Opcode },
   7633     /* 50 */
   7634     { Bad_Opcode },
   7635     { "phaddubw",	{ XM, EXq }, PREFIX_OPCODE },
   7636     { "phaddubd",	{ XM, EXq }, PREFIX_OPCODE },
   7637     { "phaddubq",	{ XM, EXq }, PREFIX_OPCODE },
   7638     { Bad_Opcode },
   7639     { Bad_Opcode },
   7640     { "phadduwd",	{ XM, EXq }, PREFIX_OPCODE },
   7641     { "phadduwq",	{ XM, EXq }, PREFIX_OPCODE },
   7642     /* 58 */
   7643     { Bad_Opcode },
   7644     { Bad_Opcode },
   7645     { Bad_Opcode },
   7646     { "phaddudq",	{ XM, EXq }, PREFIX_OPCODE },
   7647     { Bad_Opcode },
   7648     { Bad_Opcode },
   7649     { Bad_Opcode },
   7650     { Bad_Opcode },
   7651     /* 60 */
   7652     { Bad_Opcode },
   7653     { "phsubbw",	{ XM, EXq }, PREFIX_OPCODE },
   7654     { "phsubbd",	{ XM, EXq }, PREFIX_OPCODE },
   7655     { "phsubbq",	{ XM, EXq }, PREFIX_OPCODE },
   7656     { Bad_Opcode },
   7657     { Bad_Opcode },
   7658     { Bad_Opcode },
   7659     { Bad_Opcode },
   7660     /* 68 */
   7661     { Bad_Opcode },
   7662     { Bad_Opcode },
   7663     { Bad_Opcode },
   7664     { Bad_Opcode },
   7665     { Bad_Opcode },
   7666     { Bad_Opcode },
   7667     { Bad_Opcode },
   7668     { Bad_Opcode },
   7669     /* 70 */
   7670     { Bad_Opcode },
   7671     { Bad_Opcode },
   7672     { Bad_Opcode },
   7673     { Bad_Opcode },
   7674     { Bad_Opcode },
   7675     { Bad_Opcode },
   7676     { Bad_Opcode },
   7677     { Bad_Opcode },
   7678     /* 78 */
   7679     { Bad_Opcode },
   7680     { Bad_Opcode },
   7681     { Bad_Opcode },
   7682     { Bad_Opcode },
   7683     { Bad_Opcode },
   7684     { Bad_Opcode },
   7685     { Bad_Opcode },
   7686     { Bad_Opcode },
   7687     /* 80 */
   7688     { Bad_Opcode },
   7689     { Bad_Opcode },
   7690     { Bad_Opcode },
   7691     { Bad_Opcode },
   7692     { Bad_Opcode },
   7693     { Bad_Opcode },
   7694     { Bad_Opcode },
   7695     { Bad_Opcode },
   7696     /* 88 */
   7697     { Bad_Opcode },
   7698     { Bad_Opcode },
   7699     { Bad_Opcode },
   7700     { Bad_Opcode },
   7701     { Bad_Opcode },
   7702     { Bad_Opcode },
   7703     { Bad_Opcode },
   7704     { Bad_Opcode },
   7705     /* 90 */
   7706     { Bad_Opcode },
   7707     { Bad_Opcode },
   7708     { Bad_Opcode },
   7709     { Bad_Opcode },
   7710     { Bad_Opcode },
   7711     { Bad_Opcode },
   7712     { Bad_Opcode },
   7713     { Bad_Opcode },
   7714     /* 98 */
   7715     { Bad_Opcode },
   7716     { Bad_Opcode },
   7717     { Bad_Opcode },
   7718     { Bad_Opcode },
   7719     { Bad_Opcode },
   7720     { Bad_Opcode },
   7721     { Bad_Opcode },
   7722     { Bad_Opcode },
   7723     /* a0 */
   7724     { Bad_Opcode },
   7725     { Bad_Opcode },
   7726     { Bad_Opcode },
   7727     { Bad_Opcode },
   7728     { Bad_Opcode },
   7729     { Bad_Opcode },
   7730     { Bad_Opcode },
   7731     { Bad_Opcode },
   7732     /* a8 */
   7733     { Bad_Opcode },
   7734     { Bad_Opcode },
   7735     { Bad_Opcode },
   7736     { Bad_Opcode },
   7737     { Bad_Opcode },
   7738     { Bad_Opcode },
   7739     { Bad_Opcode },
   7740     { Bad_Opcode },
   7741     /* b0 */
   7742     { Bad_Opcode },
   7743     { Bad_Opcode },
   7744     { Bad_Opcode },
   7745     { Bad_Opcode },
   7746     { Bad_Opcode },
   7747     { Bad_Opcode },
   7748     { Bad_Opcode },
   7749     { Bad_Opcode },
   7750     /* b8 */
   7751     { Bad_Opcode },
   7752     { Bad_Opcode },
   7753     { Bad_Opcode },
   7754     { Bad_Opcode },
   7755     { Bad_Opcode },
   7756     { Bad_Opcode },
   7757     { Bad_Opcode },
   7758     { Bad_Opcode },
   7759     /* c0 */
   7760     { Bad_Opcode },
   7761     { Bad_Opcode },
   7762     { Bad_Opcode },
   7763     { Bad_Opcode },
   7764     { Bad_Opcode },
   7765     { Bad_Opcode },
   7766     { Bad_Opcode },
   7767     { Bad_Opcode },
   7768     /* c8 */
   7769     { Bad_Opcode },
   7770     { Bad_Opcode },
   7771     { Bad_Opcode },
   7772     { Bad_Opcode },
   7773     { Bad_Opcode },
   7774     { Bad_Opcode },
   7775     { Bad_Opcode },
   7776     { Bad_Opcode },
   7777     /* d0 */
   7778     { Bad_Opcode },
   7779     { Bad_Opcode },
   7780     { Bad_Opcode },
   7781     { Bad_Opcode },
   7782     { Bad_Opcode },
   7783     { Bad_Opcode },
   7784     { Bad_Opcode },
   7785     { Bad_Opcode },
   7786     /* d8 */
   7787     { Bad_Opcode },
   7788     { Bad_Opcode },
   7789     { Bad_Opcode },
   7790     { Bad_Opcode },
   7791     { Bad_Opcode },
   7792     { Bad_Opcode },
   7793     { Bad_Opcode },
   7794     { Bad_Opcode },
   7795     /* e0 */
   7796     { Bad_Opcode },
   7797     { Bad_Opcode },
   7798     { Bad_Opcode },
   7799     { Bad_Opcode },
   7800     { Bad_Opcode },
   7801     { Bad_Opcode },
   7802     { Bad_Opcode },
   7803     { Bad_Opcode },
   7804     /* e8 */
   7805     { Bad_Opcode },
   7806     { Bad_Opcode },
   7807     { Bad_Opcode },
   7808     { Bad_Opcode },
   7809     { Bad_Opcode },
   7810     { Bad_Opcode },
   7811     { Bad_Opcode },
   7812     { Bad_Opcode },
   7813     /* f0 */
   7814     { Bad_Opcode },
   7815     { Bad_Opcode },
   7816     { Bad_Opcode },
   7817     { Bad_Opcode },
   7818     { Bad_Opcode },
   7819     { Bad_Opcode },
   7820     { Bad_Opcode },
   7821     { Bad_Opcode },
   7822     /* f8 */
   7823     { Bad_Opcode },
   7824     { Bad_Opcode },
   7825     { Bad_Opcode },
   7826     { Bad_Opcode },
   7827     { Bad_Opcode },
   7828     { Bad_Opcode },
   7829     { Bad_Opcode },
   7830     { Bad_Opcode },
   7831   },
   7832 };
   7833 
   7834 static const struct dis386 xop_table[][256] = {
   7835   /* XOP_08 */
   7836   {
   7837     /* 00 */
   7838     { Bad_Opcode },
   7839     { Bad_Opcode },
   7840     { Bad_Opcode },
   7841     { Bad_Opcode },
   7842     { Bad_Opcode },
   7843     { Bad_Opcode },
   7844     { Bad_Opcode },
   7845     { Bad_Opcode },
   7846     /* 08 */
   7847     { Bad_Opcode },
   7848     { Bad_Opcode },
   7849     { Bad_Opcode },
   7850     { Bad_Opcode },
   7851     { Bad_Opcode },
   7852     { Bad_Opcode },
   7853     { Bad_Opcode },
   7854     { Bad_Opcode },
   7855     /* 10 */
   7856     { Bad_Opcode },
   7857     { Bad_Opcode },
   7858     { Bad_Opcode },
   7859     { Bad_Opcode },
   7860     { Bad_Opcode },
   7861     { Bad_Opcode },
   7862     { Bad_Opcode },
   7863     { Bad_Opcode },
   7864     /* 18 */
   7865     { Bad_Opcode },
   7866     { Bad_Opcode },
   7867     { Bad_Opcode },
   7868     { Bad_Opcode },
   7869     { Bad_Opcode },
   7870     { Bad_Opcode },
   7871     { Bad_Opcode },
   7872     { Bad_Opcode },
   7873     /* 20 */
   7874     { Bad_Opcode },
   7875     { Bad_Opcode },
   7876     { Bad_Opcode },
   7877     { Bad_Opcode },
   7878     { Bad_Opcode },
   7879     { Bad_Opcode },
   7880     { Bad_Opcode },
   7881     { Bad_Opcode },
   7882     /* 28 */
   7883     { Bad_Opcode },
   7884     { Bad_Opcode },
   7885     { Bad_Opcode },
   7886     { Bad_Opcode },
   7887     { Bad_Opcode },
   7888     { Bad_Opcode },
   7889     { Bad_Opcode },
   7890     { Bad_Opcode },
   7891     /* 30 */
   7892     { Bad_Opcode },
   7893     { Bad_Opcode },
   7894     { Bad_Opcode },
   7895     { Bad_Opcode },
   7896     { Bad_Opcode },
   7897     { Bad_Opcode },
   7898     { Bad_Opcode },
   7899     { Bad_Opcode },
   7900     /* 38 */
   7901     { Bad_Opcode },
   7902     { Bad_Opcode },
   7903     { Bad_Opcode },
   7904     { Bad_Opcode },
   7905     { Bad_Opcode },
   7906     { Bad_Opcode },
   7907     { Bad_Opcode },
   7908     { Bad_Opcode },
   7909     /* 40 */
   7910     { Bad_Opcode },
   7911     { Bad_Opcode },
   7912     { Bad_Opcode },
   7913     { Bad_Opcode },
   7914     { Bad_Opcode },
   7915     { Bad_Opcode },
   7916     { Bad_Opcode },
   7917     { Bad_Opcode },
   7918     /* 48 */
   7919     { Bad_Opcode },
   7920     { Bad_Opcode },
   7921     { Bad_Opcode },
   7922     { Bad_Opcode },
   7923     { Bad_Opcode },
   7924     { Bad_Opcode },
   7925     { Bad_Opcode },
   7926     { Bad_Opcode },
   7927     /* 50 */
   7928     { Bad_Opcode },
   7929     { Bad_Opcode },
   7930     { Bad_Opcode },
   7931     { Bad_Opcode },
   7932     { Bad_Opcode },
   7933     { Bad_Opcode },
   7934     { Bad_Opcode },
   7935     { Bad_Opcode },
   7936     /* 58 */
   7937     { Bad_Opcode },
   7938     { Bad_Opcode },
   7939     { Bad_Opcode },
   7940     { Bad_Opcode },
   7941     { Bad_Opcode },
   7942     { Bad_Opcode },
   7943     { Bad_Opcode },
   7944     { Bad_Opcode },
   7945     /* 60 */
   7946     { Bad_Opcode },
   7947     { Bad_Opcode },
   7948     { Bad_Opcode },
   7949     { Bad_Opcode },
   7950     { Bad_Opcode },
   7951     { Bad_Opcode },
   7952     { Bad_Opcode },
   7953     { Bad_Opcode },
   7954     /* 68 */
   7955     { Bad_Opcode },
   7956     { Bad_Opcode },
   7957     { Bad_Opcode },
   7958     { Bad_Opcode },
   7959     { Bad_Opcode },
   7960     { Bad_Opcode },
   7961     { Bad_Opcode },
   7962     { Bad_Opcode },
   7963     /* 70 */
   7964     { Bad_Opcode },
   7965     { Bad_Opcode },
   7966     { Bad_Opcode },
   7967     { Bad_Opcode },
   7968     { Bad_Opcode },
   7969     { Bad_Opcode },
   7970     { Bad_Opcode },
   7971     { Bad_Opcode },
   7972     /* 78 */
   7973     { Bad_Opcode },
   7974     { Bad_Opcode },
   7975     { Bad_Opcode },
   7976     { Bad_Opcode },
   7977     { Bad_Opcode },
   7978     { Bad_Opcode },
   7979     { Bad_Opcode },
   7980     { Bad_Opcode },
   7981     /* 80 */
   7982     { Bad_Opcode },
   7983     { Bad_Opcode },
   7984     { Bad_Opcode },
   7985     { Bad_Opcode },
   7986     { Bad_Opcode },
   7987     { "vpmacssww", 	{ XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
   7988     { "vpmacsswd", 	{ XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
   7989     { "vpmacssdql", 	{ XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
   7990     /* 88 */
   7991     { Bad_Opcode },
   7992     { Bad_Opcode },
   7993     { Bad_Opcode },
   7994     { Bad_Opcode },
   7995     { Bad_Opcode },
   7996     { Bad_Opcode },
   7997     { "vpmacssdd", 	{ XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
   7998     { "vpmacssdqh", 	{ XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
   7999     /* 90 */
   8000     { Bad_Opcode },
   8001     { Bad_Opcode },
   8002     { Bad_Opcode },
   8003     { Bad_Opcode },
   8004     { Bad_Opcode },
   8005     { "vpmacsww", 	{ XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
   8006     { "vpmacswd", 	{ XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
   8007     { "vpmacsdql", 	{ XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
   8008     /* 98 */
   8009     { Bad_Opcode },
   8010     { Bad_Opcode },
   8011     { Bad_Opcode },
   8012     { Bad_Opcode },
   8013     { Bad_Opcode },
   8014     { Bad_Opcode },
   8015     { "vpmacsdd", 	{ XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
   8016     { "vpmacsdqh", 	{ XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
   8017     /* a0 */
   8018     { Bad_Opcode },
   8019     { Bad_Opcode },
   8020     { "vpcmov", 	{ XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
   8021     { "vpperm", 	{ XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
   8022     { Bad_Opcode },
   8023     { Bad_Opcode },
   8024     { "vpmadcsswd", 	{ XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
   8025     { Bad_Opcode },
   8026     /* a8 */
   8027     { Bad_Opcode },
   8028     { Bad_Opcode },
   8029     { Bad_Opcode },
   8030     { Bad_Opcode },
   8031     { Bad_Opcode },
   8032     { Bad_Opcode },
   8033     { Bad_Opcode },
   8034     { Bad_Opcode },
   8035     /* b0 */
   8036     { Bad_Opcode },
   8037     { Bad_Opcode },
   8038     { Bad_Opcode },
   8039     { Bad_Opcode },
   8040     { Bad_Opcode },
   8041     { Bad_Opcode },
   8042     { "vpmadcswd", 	{ XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
   8043     { Bad_Opcode },
   8044     /* b8 */
   8045     { Bad_Opcode },
   8046     { Bad_Opcode },
   8047     { Bad_Opcode },
   8048     { Bad_Opcode },
   8049     { Bad_Opcode },
   8050     { Bad_Opcode },
   8051     { Bad_Opcode },
   8052     { Bad_Opcode },
   8053     /* c0 */
   8054     { "vprotb", 	{ XM, Vex_2src_1, Ib }, 0 },
   8055     { "vprotw", 	{ XM, Vex_2src_1, Ib }, 0 },
   8056     { "vprotd", 	{ XM, Vex_2src_1, Ib }, 0 },
   8057     { "vprotq", 	{ XM, Vex_2src_1, Ib }, 0 },
   8058     { Bad_Opcode },
   8059     { Bad_Opcode },
   8060     { Bad_Opcode },
   8061     { Bad_Opcode },
   8062     /* c8 */
   8063     { Bad_Opcode },
   8064     { Bad_Opcode },
   8065     { Bad_Opcode },
   8066     { Bad_Opcode },
   8067     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
   8068     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
   8069     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
   8070     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
   8071     /* d0 */
   8072     { Bad_Opcode },
   8073     { Bad_Opcode },
   8074     { Bad_Opcode },
   8075     { Bad_Opcode },
   8076     { Bad_Opcode },
   8077     { Bad_Opcode },
   8078     { Bad_Opcode },
   8079     { Bad_Opcode },
   8080     /* d8 */
   8081     { Bad_Opcode },
   8082     { Bad_Opcode },
   8083     { Bad_Opcode },
   8084     { Bad_Opcode },
   8085     { Bad_Opcode },
   8086     { Bad_Opcode },
   8087     { Bad_Opcode },
   8088     { Bad_Opcode },
   8089     /* e0 */
   8090     { Bad_Opcode },
   8091     { Bad_Opcode },
   8092     { Bad_Opcode },
   8093     { Bad_Opcode },
   8094     { Bad_Opcode },
   8095     { Bad_Opcode },
   8096     { Bad_Opcode },
   8097     { Bad_Opcode },
   8098     /* e8 */
   8099     { Bad_Opcode },
   8100     { Bad_Opcode },
   8101     { Bad_Opcode },
   8102     { Bad_Opcode },
   8103     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
   8104     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
   8105     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
   8106     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
   8107     /* f0 */
   8108     { Bad_Opcode },
   8109     { Bad_Opcode },
   8110     { Bad_Opcode },
   8111     { Bad_Opcode },
   8112     { Bad_Opcode },
   8113     { Bad_Opcode },
   8114     { Bad_Opcode },
   8115     { Bad_Opcode },
   8116     /* f8 */
   8117     { Bad_Opcode },
   8118     { Bad_Opcode },
   8119     { Bad_Opcode },
   8120     { Bad_Opcode },
   8121     { Bad_Opcode },
   8122     { Bad_Opcode },
   8123     { Bad_Opcode },
   8124     { Bad_Opcode },
   8125   },
   8126   /* XOP_09 */
   8127   {
   8128     /* 00 */
   8129     { Bad_Opcode },
   8130     { REG_TABLE (REG_XOP_TBM_01) },
   8131     { REG_TABLE (REG_XOP_TBM_02) },
   8132     { Bad_Opcode },
   8133     { Bad_Opcode },
   8134     { Bad_Opcode },
   8135     { Bad_Opcode },
   8136     { Bad_Opcode },
   8137     /* 08 */
   8138     { Bad_Opcode },
   8139     { Bad_Opcode },
   8140     { Bad_Opcode },
   8141     { Bad_Opcode },
   8142     { Bad_Opcode },
   8143     { Bad_Opcode },
   8144     { Bad_Opcode },
   8145     { Bad_Opcode },
   8146     /* 10 */
   8147     { Bad_Opcode },
   8148     { Bad_Opcode },
   8149     { REG_TABLE (REG_XOP_LWPCB) },
   8150     { Bad_Opcode },
   8151     { Bad_Opcode },
   8152     { Bad_Opcode },
   8153     { Bad_Opcode },
   8154     { Bad_Opcode },
   8155     /* 18 */
   8156     { Bad_Opcode },
   8157     { Bad_Opcode },
   8158     { Bad_Opcode },
   8159     { Bad_Opcode },
   8160     { Bad_Opcode },
   8161     { Bad_Opcode },
   8162     { Bad_Opcode },
   8163     { Bad_Opcode },
   8164     /* 20 */
   8165     { Bad_Opcode },
   8166     { Bad_Opcode },
   8167     { Bad_Opcode },
   8168     { Bad_Opcode },
   8169     { Bad_Opcode },
   8170     { Bad_Opcode },
   8171     { Bad_Opcode },
   8172     { Bad_Opcode },
   8173     /* 28 */
   8174     { Bad_Opcode },
   8175     { Bad_Opcode },
   8176     { Bad_Opcode },
   8177     { Bad_Opcode },
   8178     { Bad_Opcode },
   8179     { Bad_Opcode },
   8180     { Bad_Opcode },
   8181     { Bad_Opcode },
   8182     /* 30 */
   8183     { Bad_Opcode },
   8184     { Bad_Opcode },
   8185     { Bad_Opcode },
   8186     { Bad_Opcode },
   8187     { Bad_Opcode },
   8188     { Bad_Opcode },
   8189     { Bad_Opcode },
   8190     { Bad_Opcode },
   8191     /* 38 */
   8192     { Bad_Opcode },
   8193     { Bad_Opcode },
   8194     { Bad_Opcode },
   8195     { Bad_Opcode },
   8196     { Bad_Opcode },
   8197     { Bad_Opcode },
   8198     { Bad_Opcode },
   8199     { Bad_Opcode },
   8200     /* 40 */
   8201     { Bad_Opcode },
   8202     { Bad_Opcode },
   8203     { Bad_Opcode },
   8204     { Bad_Opcode },
   8205     { Bad_Opcode },
   8206     { Bad_Opcode },
   8207     { Bad_Opcode },
   8208     { Bad_Opcode },
   8209     /* 48 */
   8210     { Bad_Opcode },
   8211     { Bad_Opcode },
   8212     { Bad_Opcode },
   8213     { Bad_Opcode },
   8214     { Bad_Opcode },
   8215     { Bad_Opcode },
   8216     { Bad_Opcode },
   8217     { Bad_Opcode },
   8218     /* 50 */
   8219     { Bad_Opcode },
   8220     { Bad_Opcode },
   8221     { Bad_Opcode },
   8222     { Bad_Opcode },
   8223     { Bad_Opcode },
   8224     { Bad_Opcode },
   8225     { Bad_Opcode },
   8226     { Bad_Opcode },
   8227     /* 58 */
   8228     { Bad_Opcode },
   8229     { Bad_Opcode },
   8230     { Bad_Opcode },
   8231     { Bad_Opcode },
   8232     { Bad_Opcode },
   8233     { Bad_Opcode },
   8234     { Bad_Opcode },
   8235     { Bad_Opcode },
   8236     /* 60 */
   8237     { Bad_Opcode },
   8238     { Bad_Opcode },
   8239     { Bad_Opcode },
   8240     { Bad_Opcode },
   8241     { Bad_Opcode },
   8242     { Bad_Opcode },
   8243     { Bad_Opcode },
   8244     { Bad_Opcode },
   8245     /* 68 */
   8246     { Bad_Opcode },
   8247     { Bad_Opcode },
   8248     { Bad_Opcode },
   8249     { Bad_Opcode },
   8250     { Bad_Opcode },
   8251     { Bad_Opcode },
   8252     { Bad_Opcode },
   8253     { Bad_Opcode },
   8254     /* 70 */
   8255     { Bad_Opcode },
   8256     { Bad_Opcode },
   8257     { Bad_Opcode },
   8258     { Bad_Opcode },
   8259     { Bad_Opcode },
   8260     { Bad_Opcode },
   8261     { Bad_Opcode },
   8262     { Bad_Opcode },
   8263     /* 78 */
   8264     { Bad_Opcode },
   8265     { Bad_Opcode },
   8266     { Bad_Opcode },
   8267     { Bad_Opcode },
   8268     { Bad_Opcode },
   8269     { Bad_Opcode },
   8270     { Bad_Opcode },
   8271     { Bad_Opcode },
   8272     /* 80 */
   8273     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) },
   8274     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) },
   8275     { "vfrczss", 	{ XM, EXd }, 0 },
   8276     { "vfrczsd", 	{ XM, EXq }, 0 },
   8277     { Bad_Opcode },
   8278     { Bad_Opcode },
   8279     { Bad_Opcode },
   8280     { Bad_Opcode },
   8281     /* 88 */
   8282     { Bad_Opcode },
   8283     { Bad_Opcode },
   8284     { Bad_Opcode },
   8285     { Bad_Opcode },
   8286     { Bad_Opcode },
   8287     { Bad_Opcode },
   8288     { Bad_Opcode },
   8289     { Bad_Opcode },
   8290     /* 90 */
   8291     { "vprotb",		{ XM, Vex_2src_1, Vex_2src_2 }, 0 },
   8292     { "vprotw",		{ XM, Vex_2src_1, Vex_2src_2 }, 0 },
   8293     { "vprotd",		{ XM, Vex_2src_1, Vex_2src_2 }, 0 },
   8294     { "vprotq",		{ XM, Vex_2src_1, Vex_2src_2 }, 0 },
   8295     { "vpshlb",		{ XM, Vex_2src_1, Vex_2src_2 }, 0 },
   8296     { "vpshlw",		{ XM, Vex_2src_1, Vex_2src_2 }, 0 },
   8297     { "vpshld",		{ XM, Vex_2src_1, Vex_2src_2 }, 0 },
   8298     { "vpshlq",		{ XM, Vex_2src_1, Vex_2src_2 }, 0 },
   8299     /* 98 */
   8300     { "vpshab",		{ XM, Vex_2src_1, Vex_2src_2 }, 0 },
   8301     { "vpshaw",		{ XM, Vex_2src_1, Vex_2src_2 }, 0 },
   8302     { "vpshad",		{ XM, Vex_2src_1, Vex_2src_2 }, 0 },
   8303     { "vpshaq",		{ XM, Vex_2src_1, Vex_2src_2 }, 0 },
   8304     { Bad_Opcode },
   8305     { Bad_Opcode },
   8306     { Bad_Opcode },
   8307     { Bad_Opcode },
   8308     /* a0 */
   8309     { Bad_Opcode },
   8310     { Bad_Opcode },
   8311     { Bad_Opcode },
   8312     { Bad_Opcode },
   8313     { Bad_Opcode },
   8314     { Bad_Opcode },
   8315     { Bad_Opcode },
   8316     { Bad_Opcode },
   8317     /* a8 */
   8318     { Bad_Opcode },
   8319     { Bad_Opcode },
   8320     { Bad_Opcode },
   8321     { Bad_Opcode },
   8322     { Bad_Opcode },
   8323     { Bad_Opcode },
   8324     { Bad_Opcode },
   8325     { Bad_Opcode },
   8326     /* b0 */
   8327     { Bad_Opcode },
   8328     { Bad_Opcode },
   8329     { Bad_Opcode },
   8330     { Bad_Opcode },
   8331     { Bad_Opcode },
   8332     { Bad_Opcode },
   8333     { Bad_Opcode },
   8334     { Bad_Opcode },
   8335     /* b8 */
   8336     { Bad_Opcode },
   8337     { Bad_Opcode },
   8338     { Bad_Opcode },
   8339     { Bad_Opcode },
   8340     { Bad_Opcode },
   8341     { Bad_Opcode },
   8342     { Bad_Opcode },
   8343     { Bad_Opcode },
   8344     /* c0 */
   8345     { Bad_Opcode },
   8346     { "vphaddbw",	{ XM, EXxmm }, 0 },
   8347     { "vphaddbd",	{ XM, EXxmm }, 0 },
   8348     { "vphaddbq",	{ XM, EXxmm }, 0 },
   8349     { Bad_Opcode },
   8350     { Bad_Opcode },
   8351     { "vphaddwd",	{ XM, EXxmm }, 0 },
   8352     { "vphaddwq",	{ XM, EXxmm }, 0 },
   8353     /* c8 */
   8354     { Bad_Opcode },
   8355     { Bad_Opcode },
   8356     { Bad_Opcode },
   8357     { "vphadddq",	{ XM, EXxmm }, 0 },
   8358     { Bad_Opcode },
   8359     { Bad_Opcode },
   8360     { Bad_Opcode },
   8361     { Bad_Opcode },
   8362     /* d0 */
   8363     { Bad_Opcode },
   8364     { "vphaddubw",	{ XM, EXxmm }, 0 },
   8365     { "vphaddubd",	{ XM, EXxmm }, 0 },
   8366     { "vphaddubq",	{ XM, EXxmm }, 0 },
   8367     { Bad_Opcode },
   8368     { Bad_Opcode },
   8369     { "vphadduwd",	{ XM, EXxmm }, 0 },
   8370     { "vphadduwq",	{ XM, EXxmm }, 0 },
   8371     /* d8 */
   8372     { Bad_Opcode },
   8373     { Bad_Opcode },
   8374     { Bad_Opcode },
   8375     { "vphaddudq",	{ XM, EXxmm }, 0 },
   8376     { Bad_Opcode },
   8377     { Bad_Opcode },
   8378     { Bad_Opcode },
   8379     { Bad_Opcode },
   8380     /* e0 */
   8381     { Bad_Opcode },
   8382     { "vphsubbw",	{ XM, EXxmm }, 0 },
   8383     { "vphsubwd",	{ XM, EXxmm }, 0 },
   8384     { "vphsubdq",	{ XM, EXxmm }, 0 },
   8385     { Bad_Opcode },
   8386     { Bad_Opcode },
   8387     { Bad_Opcode },
   8388     { Bad_Opcode },
   8389     /* e8 */
   8390     { Bad_Opcode },
   8391     { Bad_Opcode },
   8392     { Bad_Opcode },
   8393     { Bad_Opcode },
   8394     { Bad_Opcode },
   8395     { Bad_Opcode },
   8396     { Bad_Opcode },
   8397     { Bad_Opcode },
   8398     /* f0 */
   8399     { Bad_Opcode },
   8400     { Bad_Opcode },
   8401     { Bad_Opcode },
   8402     { Bad_Opcode },
   8403     { Bad_Opcode },
   8404     { Bad_Opcode },
   8405     { Bad_Opcode },
   8406     { Bad_Opcode },
   8407     /* f8 */
   8408     { Bad_Opcode },
   8409     { Bad_Opcode },
   8410     { Bad_Opcode },
   8411     { Bad_Opcode },
   8412     { Bad_Opcode },
   8413     { Bad_Opcode },
   8414     { Bad_Opcode },
   8415     { Bad_Opcode },
   8416   },
   8417   /* XOP_0A */
   8418   {
   8419     /* 00 */
   8420     { Bad_Opcode },
   8421     { Bad_Opcode },
   8422     { Bad_Opcode },
   8423     { Bad_Opcode },
   8424     { Bad_Opcode },
   8425     { Bad_Opcode },
   8426     { Bad_Opcode },
   8427     { Bad_Opcode },
   8428     /* 08 */
   8429     { Bad_Opcode },
   8430     { Bad_Opcode },
   8431     { Bad_Opcode },
   8432     { Bad_Opcode },
   8433     { Bad_Opcode },
   8434     { Bad_Opcode },
   8435     { Bad_Opcode },
   8436     { Bad_Opcode },
   8437     /* 10 */
   8438     { "bextr",	{ Gv, Ev, Iq }, 0 },
   8439     { Bad_Opcode },
   8440     { REG_TABLE (REG_XOP_LWP) },
   8441     { Bad_Opcode },
   8442     { Bad_Opcode },
   8443     { Bad_Opcode },
   8444     { Bad_Opcode },
   8445     { Bad_Opcode },
   8446     /* 18 */
   8447     { Bad_Opcode },
   8448     { Bad_Opcode },
   8449     { Bad_Opcode },
   8450     { Bad_Opcode },
   8451     { Bad_Opcode },
   8452     { Bad_Opcode },
   8453     { Bad_Opcode },
   8454     { Bad_Opcode },
   8455     /* 20 */
   8456     { Bad_Opcode },
   8457     { Bad_Opcode },
   8458     { Bad_Opcode },
   8459     { Bad_Opcode },
   8460     { Bad_Opcode },
   8461     { Bad_Opcode },
   8462     { Bad_Opcode },
   8463     { Bad_Opcode },
   8464     /* 28 */
   8465     { Bad_Opcode },
   8466     { Bad_Opcode },
   8467     { Bad_Opcode },
   8468     { Bad_Opcode },
   8469     { Bad_Opcode },
   8470     { Bad_Opcode },
   8471     { Bad_Opcode },
   8472     { Bad_Opcode },
   8473     /* 30 */
   8474     { Bad_Opcode },
   8475     { Bad_Opcode },
   8476     { Bad_Opcode },
   8477     { Bad_Opcode },
   8478     { Bad_Opcode },
   8479     { Bad_Opcode },
   8480     { Bad_Opcode },
   8481     { Bad_Opcode },
   8482     /* 38 */
   8483     { Bad_Opcode },
   8484     { Bad_Opcode },
   8485     { Bad_Opcode },
   8486     { Bad_Opcode },
   8487     { Bad_Opcode },
   8488     { Bad_Opcode },
   8489     { Bad_Opcode },
   8490     { Bad_Opcode },
   8491     /* 40 */
   8492     { Bad_Opcode },
   8493     { Bad_Opcode },
   8494     { Bad_Opcode },
   8495     { Bad_Opcode },
   8496     { Bad_Opcode },
   8497     { Bad_Opcode },
   8498     { Bad_Opcode },
   8499     { Bad_Opcode },
   8500     /* 48 */
   8501     { Bad_Opcode },
   8502     { Bad_Opcode },
   8503     { Bad_Opcode },
   8504     { Bad_Opcode },
   8505     { Bad_Opcode },
   8506     { Bad_Opcode },
   8507     { Bad_Opcode },
   8508     { Bad_Opcode },
   8509     /* 50 */
   8510     { Bad_Opcode },
   8511     { Bad_Opcode },
   8512     { Bad_Opcode },
   8513     { Bad_Opcode },
   8514     { Bad_Opcode },
   8515     { Bad_Opcode },
   8516     { Bad_Opcode },
   8517     { Bad_Opcode },
   8518     /* 58 */
   8519     { Bad_Opcode },
   8520     { Bad_Opcode },
   8521     { Bad_Opcode },
   8522     { Bad_Opcode },
   8523     { Bad_Opcode },
   8524     { Bad_Opcode },
   8525     { Bad_Opcode },
   8526     { Bad_Opcode },
   8527     /* 60 */
   8528     { Bad_Opcode },
   8529     { Bad_Opcode },
   8530     { Bad_Opcode },
   8531     { Bad_Opcode },
   8532     { Bad_Opcode },
   8533     { Bad_Opcode },
   8534     { Bad_Opcode },
   8535     { Bad_Opcode },
   8536     /* 68 */
   8537     { Bad_Opcode },
   8538     { Bad_Opcode },
   8539     { Bad_Opcode },
   8540     { Bad_Opcode },
   8541     { Bad_Opcode },
   8542     { Bad_Opcode },
   8543     { Bad_Opcode },
   8544     { Bad_Opcode },
   8545     /* 70 */
   8546     { Bad_Opcode },
   8547     { Bad_Opcode },
   8548     { Bad_Opcode },
   8549     { Bad_Opcode },
   8550     { Bad_Opcode },
   8551     { Bad_Opcode },
   8552     { Bad_Opcode },
   8553     { Bad_Opcode },
   8554     /* 78 */
   8555     { Bad_Opcode },
   8556     { Bad_Opcode },
   8557     { Bad_Opcode },
   8558     { Bad_Opcode },
   8559     { Bad_Opcode },
   8560     { Bad_Opcode },
   8561     { Bad_Opcode },
   8562     { Bad_Opcode },
   8563     /* 80 */
   8564     { Bad_Opcode },
   8565     { Bad_Opcode },
   8566     { Bad_Opcode },
   8567     { Bad_Opcode },
   8568     { Bad_Opcode },
   8569     { Bad_Opcode },
   8570     { Bad_Opcode },
   8571     { Bad_Opcode },
   8572     /* 88 */
   8573     { Bad_Opcode },
   8574     { Bad_Opcode },
   8575     { Bad_Opcode },
   8576     { Bad_Opcode },
   8577     { Bad_Opcode },
   8578     { Bad_Opcode },
   8579     { Bad_Opcode },
   8580     { Bad_Opcode },
   8581     /* 90 */
   8582     { Bad_Opcode },
   8583     { Bad_Opcode },
   8584     { Bad_Opcode },
   8585     { Bad_Opcode },
   8586     { Bad_Opcode },
   8587     { Bad_Opcode },
   8588     { Bad_Opcode },
   8589     { Bad_Opcode },
   8590     /* 98 */
   8591     { Bad_Opcode },
   8592     { Bad_Opcode },
   8593     { Bad_Opcode },
   8594     { Bad_Opcode },
   8595     { Bad_Opcode },
   8596     { Bad_Opcode },
   8597     { Bad_Opcode },
   8598     { Bad_Opcode },
   8599     /* a0 */
   8600     { Bad_Opcode },
   8601     { Bad_Opcode },
   8602     { Bad_Opcode },
   8603     { Bad_Opcode },
   8604     { Bad_Opcode },
   8605     { Bad_Opcode },
   8606     { Bad_Opcode },
   8607     { Bad_Opcode },
   8608     /* a8 */
   8609     { Bad_Opcode },
   8610     { Bad_Opcode },
   8611     { Bad_Opcode },
   8612     { Bad_Opcode },
   8613     { Bad_Opcode },
   8614     { Bad_Opcode },
   8615     { Bad_Opcode },
   8616     { Bad_Opcode },
   8617     /* b0 */
   8618     { Bad_Opcode },
   8619     { Bad_Opcode },
   8620     { Bad_Opcode },
   8621     { Bad_Opcode },
   8622     { Bad_Opcode },
   8623     { Bad_Opcode },
   8624     { Bad_Opcode },
   8625     { Bad_Opcode },
   8626     /* b8 */
   8627     { Bad_Opcode },
   8628     { Bad_Opcode },
   8629     { Bad_Opcode },
   8630     { Bad_Opcode },
   8631     { Bad_Opcode },
   8632     { Bad_Opcode },
   8633     { Bad_Opcode },
   8634     { Bad_Opcode },
   8635     /* c0 */
   8636     { Bad_Opcode },
   8637     { Bad_Opcode },
   8638     { Bad_Opcode },
   8639     { Bad_Opcode },
   8640     { Bad_Opcode },
   8641     { Bad_Opcode },
   8642     { Bad_Opcode },
   8643     { Bad_Opcode },
   8644     /* c8 */
   8645     { Bad_Opcode },
   8646     { Bad_Opcode },
   8647     { Bad_Opcode },
   8648     { Bad_Opcode },
   8649     { Bad_Opcode },
   8650     { Bad_Opcode },
   8651     { Bad_Opcode },
   8652     { Bad_Opcode },
   8653     /* d0 */
   8654     { Bad_Opcode },
   8655     { Bad_Opcode },
   8656     { Bad_Opcode },
   8657     { Bad_Opcode },
   8658     { Bad_Opcode },
   8659     { Bad_Opcode },
   8660     { Bad_Opcode },
   8661     { Bad_Opcode },
   8662     /* d8 */
   8663     { Bad_Opcode },
   8664     { Bad_Opcode },
   8665     { Bad_Opcode },
   8666     { Bad_Opcode },
   8667     { Bad_Opcode },
   8668     { Bad_Opcode },
   8669     { Bad_Opcode },
   8670     { Bad_Opcode },
   8671     /* e0 */
   8672     { Bad_Opcode },
   8673     { Bad_Opcode },
   8674     { Bad_Opcode },
   8675     { Bad_Opcode },
   8676     { Bad_Opcode },
   8677     { Bad_Opcode },
   8678     { Bad_Opcode },
   8679     { Bad_Opcode },
   8680     /* e8 */
   8681     { Bad_Opcode },
   8682     { Bad_Opcode },
   8683     { Bad_Opcode },
   8684     { Bad_Opcode },
   8685     { Bad_Opcode },
   8686     { Bad_Opcode },
   8687     { Bad_Opcode },
   8688     { Bad_Opcode },
   8689     /* f0 */
   8690     { Bad_Opcode },
   8691     { Bad_Opcode },
   8692     { Bad_Opcode },
   8693     { Bad_Opcode },
   8694     { Bad_Opcode },
   8695     { Bad_Opcode },
   8696     { Bad_Opcode },
   8697     { Bad_Opcode },
   8698     /* f8 */
   8699     { Bad_Opcode },
   8700     { Bad_Opcode },
   8701     { Bad_Opcode },
   8702     { Bad_Opcode },
   8703     { Bad_Opcode },
   8704     { Bad_Opcode },
   8705     { Bad_Opcode },
   8706     { Bad_Opcode },
   8707   },
   8708 };
   8709 
   8710 static const struct dis386 vex_table[][256] = {
   8711   /* VEX_0F */
   8712   {
   8713     /* 00 */
   8714     { Bad_Opcode },
   8715     { Bad_Opcode },
   8716     { Bad_Opcode },
   8717     { Bad_Opcode },
   8718     { Bad_Opcode },
   8719     { Bad_Opcode },
   8720     { Bad_Opcode },
   8721     { Bad_Opcode },
   8722     /* 08 */
   8723     { Bad_Opcode },
   8724     { Bad_Opcode },
   8725     { Bad_Opcode },
   8726     { Bad_Opcode },
   8727     { Bad_Opcode },
   8728     { Bad_Opcode },
   8729     { Bad_Opcode },
   8730     { Bad_Opcode },
   8731     /* 10 */
   8732     { PREFIX_TABLE (PREFIX_VEX_0F10) },
   8733     { PREFIX_TABLE (PREFIX_VEX_0F11) },
   8734     { PREFIX_TABLE (PREFIX_VEX_0F12) },
   8735     { MOD_TABLE (MOD_VEX_0F13) },
   8736     { VEX_W_TABLE (VEX_W_0F14) },
   8737     { VEX_W_TABLE (VEX_W_0F15) },
   8738     { PREFIX_TABLE (PREFIX_VEX_0F16) },
   8739     { MOD_TABLE (MOD_VEX_0F17) },
   8740     /* 18 */
   8741     { Bad_Opcode },
   8742     { Bad_Opcode },
   8743     { Bad_Opcode },
   8744     { Bad_Opcode },
   8745     { Bad_Opcode },
   8746     { Bad_Opcode },
   8747     { Bad_Opcode },
   8748     { Bad_Opcode },
   8749     /* 20 */
   8750     { Bad_Opcode },
   8751     { Bad_Opcode },
   8752     { Bad_Opcode },
   8753     { Bad_Opcode },
   8754     { Bad_Opcode },
   8755     { Bad_Opcode },
   8756     { Bad_Opcode },
   8757     { Bad_Opcode },
   8758     /* 28 */
   8759     { VEX_W_TABLE (VEX_W_0F28) },
   8760     { VEX_W_TABLE (VEX_W_0F29) },
   8761     { PREFIX_TABLE (PREFIX_VEX_0F2A) },
   8762     { MOD_TABLE (MOD_VEX_0F2B) },
   8763     { PREFIX_TABLE (PREFIX_VEX_0F2C) },
   8764     { PREFIX_TABLE (PREFIX_VEX_0F2D) },
   8765     { PREFIX_TABLE (PREFIX_VEX_0F2E) },
   8766     { PREFIX_TABLE (PREFIX_VEX_0F2F) },
   8767     /* 30 */
   8768     { Bad_Opcode },
   8769     { Bad_Opcode },
   8770     { Bad_Opcode },
   8771     { Bad_Opcode },
   8772     { Bad_Opcode },
   8773     { Bad_Opcode },
   8774     { Bad_Opcode },
   8775     { Bad_Opcode },
   8776     /* 38 */
   8777     { Bad_Opcode },
   8778     { Bad_Opcode },
   8779     { Bad_Opcode },
   8780     { Bad_Opcode },
   8781     { Bad_Opcode },
   8782     { Bad_Opcode },
   8783     { Bad_Opcode },
   8784     { Bad_Opcode },
   8785     /* 40 */
   8786     { Bad_Opcode },
   8787     { PREFIX_TABLE (PREFIX_VEX_0F41) },
   8788     { PREFIX_TABLE (PREFIX_VEX_0F42) },
   8789     { Bad_Opcode },
   8790     { PREFIX_TABLE (PREFIX_VEX_0F44) },
   8791     { PREFIX_TABLE (PREFIX_VEX_0F45) },
   8792     { PREFIX_TABLE (PREFIX_VEX_0F46) },
   8793     { PREFIX_TABLE (PREFIX_VEX_0F47) },
   8794     /* 48 */
   8795     { Bad_Opcode },
   8796     { Bad_Opcode },
   8797     { PREFIX_TABLE (PREFIX_VEX_0F4A) },
   8798     { PREFIX_TABLE (PREFIX_VEX_0F4B) },
   8799     { Bad_Opcode },
   8800     { Bad_Opcode },
   8801     { Bad_Opcode },
   8802     { Bad_Opcode },
   8803     /* 50 */
   8804     { MOD_TABLE (MOD_VEX_0F50) },
   8805     { PREFIX_TABLE (PREFIX_VEX_0F51) },
   8806     { PREFIX_TABLE (PREFIX_VEX_0F52) },
   8807     { PREFIX_TABLE (PREFIX_VEX_0F53) },
   8808     { "vandpX",		{ XM, Vex, EXx }, 0 },
   8809     { "vandnpX",	{ XM, Vex, EXx }, 0 },
   8810     { "vorpX",		{ XM, Vex, EXx }, 0 },
   8811     { "vxorpX",		{ XM, Vex, EXx }, 0 },
   8812     /* 58 */
   8813     { PREFIX_TABLE (PREFIX_VEX_0F58) },
   8814     { PREFIX_TABLE (PREFIX_VEX_0F59) },
   8815     { PREFIX_TABLE (PREFIX_VEX_0F5A) },
   8816     { PREFIX_TABLE (PREFIX_VEX_0F5B) },
   8817     { PREFIX_TABLE (PREFIX_VEX_0F5C) },
   8818     { PREFIX_TABLE (PREFIX_VEX_0F5D) },
   8819     { PREFIX_TABLE (PREFIX_VEX_0F5E) },
   8820     { PREFIX_TABLE (PREFIX_VEX_0F5F) },
   8821     /* 60 */
   8822     { PREFIX_TABLE (PREFIX_VEX_0F60) },
   8823     { PREFIX_TABLE (PREFIX_VEX_0F61) },
   8824     { PREFIX_TABLE (PREFIX_VEX_0F62) },
   8825     { PREFIX_TABLE (PREFIX_VEX_0F63) },
   8826     { PREFIX_TABLE (PREFIX_VEX_0F64) },
   8827     { PREFIX_TABLE (PREFIX_VEX_0F65) },
   8828     { PREFIX_TABLE (PREFIX_VEX_0F66) },
   8829     { PREFIX_TABLE (PREFIX_VEX_0F67) },
   8830     /* 68 */
   8831     { PREFIX_TABLE (PREFIX_VEX_0F68) },
   8832     { PREFIX_TABLE (PREFIX_VEX_0F69) },
   8833     { PREFIX_TABLE (PREFIX_VEX_0F6A) },
   8834     { PREFIX_TABLE (PREFIX_VEX_0F6B) },
   8835     { PREFIX_TABLE (PREFIX_VEX_0F6C) },
   8836     { PREFIX_TABLE (PREFIX_VEX_0F6D) },
   8837     { PREFIX_TABLE (PREFIX_VEX_0F6E) },
   8838     { PREFIX_TABLE (PREFIX_VEX_0F6F) },
   8839     /* 70 */
   8840     { PREFIX_TABLE (PREFIX_VEX_0F70) },
   8841     { REG_TABLE (REG_VEX_0F71) },
   8842     { REG_TABLE (REG_VEX_0F72) },
   8843     { REG_TABLE (REG_VEX_0F73) },
   8844     { PREFIX_TABLE (PREFIX_VEX_0F74) },
   8845     { PREFIX_TABLE (PREFIX_VEX_0F75) },
   8846     { PREFIX_TABLE (PREFIX_VEX_0F76) },
   8847     { PREFIX_TABLE (PREFIX_VEX_0F77) },
   8848     /* 78 */
   8849     { Bad_Opcode },
   8850     { Bad_Opcode },
   8851     { Bad_Opcode },
   8852     { Bad_Opcode },
   8853     { PREFIX_TABLE (PREFIX_VEX_0F7C) },
   8854     { PREFIX_TABLE (PREFIX_VEX_0F7D) },
   8855     { PREFIX_TABLE (PREFIX_VEX_0F7E) },
   8856     { PREFIX_TABLE (PREFIX_VEX_0F7F) },
   8857     /* 80 */
   8858     { Bad_Opcode },
   8859     { Bad_Opcode },
   8860     { Bad_Opcode },
   8861     { Bad_Opcode },
   8862     { Bad_Opcode },
   8863     { Bad_Opcode },
   8864     { Bad_Opcode },
   8865     { Bad_Opcode },
   8866     /* 88 */
   8867     { Bad_Opcode },
   8868     { Bad_Opcode },
   8869     { Bad_Opcode },
   8870     { Bad_Opcode },
   8871     { Bad_Opcode },
   8872     { Bad_Opcode },
   8873     { Bad_Opcode },
   8874     { Bad_Opcode },
   8875     /* 90 */
   8876     { PREFIX_TABLE (PREFIX_VEX_0F90) },
   8877     { PREFIX_TABLE (PREFIX_VEX_0F91) },
   8878     { PREFIX_TABLE (PREFIX_VEX_0F92) },
   8879     { PREFIX_TABLE (PREFIX_VEX_0F93) },
   8880     { Bad_Opcode },
   8881     { Bad_Opcode },
   8882     { Bad_Opcode },
   8883     { Bad_Opcode },
   8884     /* 98 */
   8885     { PREFIX_TABLE (PREFIX_VEX_0F98) },
   8886     { PREFIX_TABLE (PREFIX_VEX_0F99) },
   8887     { Bad_Opcode },
   8888     { Bad_Opcode },
   8889     { Bad_Opcode },
   8890     { Bad_Opcode },
   8891     { Bad_Opcode },
   8892     { Bad_Opcode },
   8893     /* a0 */
   8894     { Bad_Opcode },
   8895     { Bad_Opcode },
   8896     { Bad_Opcode },
   8897     { Bad_Opcode },
   8898     { Bad_Opcode },
   8899     { Bad_Opcode },
   8900     { Bad_Opcode },
   8901     { Bad_Opcode },
   8902     /* a8 */
   8903     { Bad_Opcode },
   8904     { Bad_Opcode },
   8905     { Bad_Opcode },
   8906     { Bad_Opcode },
   8907     { Bad_Opcode },
   8908     { Bad_Opcode },
   8909     { REG_TABLE (REG_VEX_0FAE) },
   8910     { Bad_Opcode },
   8911     /* b0 */
   8912     { Bad_Opcode },
   8913     { Bad_Opcode },
   8914     { Bad_Opcode },
   8915     { Bad_Opcode },
   8916     { Bad_Opcode },
   8917     { Bad_Opcode },
   8918     { Bad_Opcode },
   8919     { Bad_Opcode },
   8920     /* b8 */
   8921     { Bad_Opcode },
   8922     { Bad_Opcode },
   8923     { Bad_Opcode },
   8924     { Bad_Opcode },
   8925     { Bad_Opcode },
   8926     { Bad_Opcode },
   8927     { Bad_Opcode },
   8928     { Bad_Opcode },
   8929     /* c0 */
   8930     { Bad_Opcode },
   8931     { Bad_Opcode },
   8932     { PREFIX_TABLE (PREFIX_VEX_0FC2) },
   8933     { Bad_Opcode },
   8934     { PREFIX_TABLE (PREFIX_VEX_0FC4) },
   8935     { PREFIX_TABLE (PREFIX_VEX_0FC5) },
   8936     { "vshufpX",	{ XM, Vex, EXx, Ib }, 0 },
   8937     { Bad_Opcode },
   8938     /* c8 */
   8939     { Bad_Opcode },
   8940     { Bad_Opcode },
   8941     { Bad_Opcode },
   8942     { Bad_Opcode },
   8943     { Bad_Opcode },
   8944     { Bad_Opcode },
   8945     { Bad_Opcode },
   8946     { Bad_Opcode },
   8947     /* d0 */
   8948     { PREFIX_TABLE (PREFIX_VEX_0FD0) },
   8949     { PREFIX_TABLE (PREFIX_VEX_0FD1) },
   8950     { PREFIX_TABLE (PREFIX_VEX_0FD2) },
   8951     { PREFIX_TABLE (PREFIX_VEX_0FD3) },
   8952     { PREFIX_TABLE (PREFIX_VEX_0FD4) },
   8953     { PREFIX_TABLE (PREFIX_VEX_0FD5) },
   8954     { PREFIX_TABLE (PREFIX_VEX_0FD6) },
   8955     { PREFIX_TABLE (PREFIX_VEX_0FD7) },
   8956     /* d8 */
   8957     { PREFIX_TABLE (PREFIX_VEX_0FD8) },
   8958     { PREFIX_TABLE (PREFIX_VEX_0FD9) },
   8959     { PREFIX_TABLE (PREFIX_VEX_0FDA) },
   8960     { PREFIX_TABLE (PREFIX_VEX_0FDB) },
   8961     { PREFIX_TABLE (PREFIX_VEX_0FDC) },
   8962     { PREFIX_TABLE (PREFIX_VEX_0FDD) },
   8963     { PREFIX_TABLE (PREFIX_VEX_0FDE) },
   8964     { PREFIX_TABLE (PREFIX_VEX_0FDF) },
   8965     /* e0 */
   8966     { PREFIX_TABLE (PREFIX_VEX_0FE0) },
   8967     { PREFIX_TABLE (PREFIX_VEX_0FE1) },
   8968     { PREFIX_TABLE (PREFIX_VEX_0FE2) },
   8969     { PREFIX_TABLE (PREFIX_VEX_0FE3) },
   8970     { PREFIX_TABLE (PREFIX_VEX_0FE4) },
   8971     { PREFIX_TABLE (PREFIX_VEX_0FE5) },
   8972     { PREFIX_TABLE (PREFIX_VEX_0FE6) },
   8973     { PREFIX_TABLE (PREFIX_VEX_0FE7) },
   8974     /* e8 */
   8975     { PREFIX_TABLE (PREFIX_VEX_0FE8) },
   8976     { PREFIX_TABLE (PREFIX_VEX_0FE9) },
   8977     { PREFIX_TABLE (PREFIX_VEX_0FEA) },
   8978     { PREFIX_TABLE (PREFIX_VEX_0FEB) },
   8979     { PREFIX_TABLE (PREFIX_VEX_0FEC) },
   8980     { PREFIX_TABLE (PREFIX_VEX_0FED) },
   8981     { PREFIX_TABLE (PREFIX_VEX_0FEE) },
   8982     { PREFIX_TABLE (PREFIX_VEX_0FEF) },
   8983     /* f0 */
   8984     { PREFIX_TABLE (PREFIX_VEX_0FF0) },
   8985     { PREFIX_TABLE (PREFIX_VEX_0FF1) },
   8986     { PREFIX_TABLE (PREFIX_VEX_0FF2) },
   8987     { PREFIX_TABLE (PREFIX_VEX_0FF3) },
   8988     { PREFIX_TABLE (PREFIX_VEX_0FF4) },
   8989     { PREFIX_TABLE (PREFIX_VEX_0FF5) },
   8990     { PREFIX_TABLE (PREFIX_VEX_0FF6) },
   8991     { PREFIX_TABLE (PREFIX_VEX_0FF7) },
   8992     /* f8 */
   8993     { PREFIX_TABLE (PREFIX_VEX_0FF8) },
   8994     { PREFIX_TABLE (PREFIX_VEX_0FF9) },
   8995     { PREFIX_TABLE (PREFIX_VEX_0FFA) },
   8996     { PREFIX_TABLE (PREFIX_VEX_0FFB) },
   8997     { PREFIX_TABLE (PREFIX_VEX_0FFC) },
   8998     { PREFIX_TABLE (PREFIX_VEX_0FFD) },
   8999     { PREFIX_TABLE (PREFIX_VEX_0FFE) },
   9000     { Bad_Opcode },
   9001   },
   9002   /* VEX_0F38 */
   9003   {
   9004     /* 00 */
   9005     { PREFIX_TABLE (PREFIX_VEX_0F3800) },
   9006     { PREFIX_TABLE (PREFIX_VEX_0F3801) },
   9007     { PREFIX_TABLE (PREFIX_VEX_0F3802) },
   9008     { PREFIX_TABLE (PREFIX_VEX_0F3803) },
   9009     { PREFIX_TABLE (PREFIX_VEX_0F3804) },
   9010     { PREFIX_TABLE (PREFIX_VEX_0F3805) },
   9011     { PREFIX_TABLE (PREFIX_VEX_0F3806) },
   9012     { PREFIX_TABLE (PREFIX_VEX_0F3807) },
   9013     /* 08 */
   9014     { PREFIX_TABLE (PREFIX_VEX_0F3808) },
   9015     { PREFIX_TABLE (PREFIX_VEX_0F3809) },
   9016     { PREFIX_TABLE (PREFIX_VEX_0F380A) },
   9017     { PREFIX_TABLE (PREFIX_VEX_0F380B) },
   9018     { PREFIX_TABLE (PREFIX_VEX_0F380C) },
   9019     { PREFIX_TABLE (PREFIX_VEX_0F380D) },
   9020     { PREFIX_TABLE (PREFIX_VEX_0F380E) },
   9021     { PREFIX_TABLE (PREFIX_VEX_0F380F) },
   9022     /* 10 */
   9023     { Bad_Opcode },
   9024     { Bad_Opcode },
   9025     { Bad_Opcode },
   9026     { PREFIX_TABLE (PREFIX_VEX_0F3813) },
   9027     { Bad_Opcode },
   9028     { Bad_Opcode },
   9029     { PREFIX_TABLE (PREFIX_VEX_0F3816) },
   9030     { PREFIX_TABLE (PREFIX_VEX_0F3817) },
   9031     /* 18 */
   9032     { PREFIX_TABLE (PREFIX_VEX_0F3818) },
   9033     { PREFIX_TABLE (PREFIX_VEX_0F3819) },
   9034     { PREFIX_TABLE (PREFIX_VEX_0F381A) },
   9035     { Bad_Opcode },
   9036     { PREFIX_TABLE (PREFIX_VEX_0F381C) },
   9037     { PREFIX_TABLE (PREFIX_VEX_0F381D) },
   9038     { PREFIX_TABLE (PREFIX_VEX_0F381E) },
   9039     { Bad_Opcode },
   9040     /* 20 */
   9041     { PREFIX_TABLE (PREFIX_VEX_0F3820) },
   9042     { PREFIX_TABLE (PREFIX_VEX_0F3821) },
   9043     { PREFIX_TABLE (PREFIX_VEX_0F3822) },
   9044     { PREFIX_TABLE (PREFIX_VEX_0F3823) },
   9045     { PREFIX_TABLE (PREFIX_VEX_0F3824) },
   9046     { PREFIX_TABLE (PREFIX_VEX_0F3825) },
   9047     { Bad_Opcode },
   9048     { Bad_Opcode },
   9049     /* 28 */
   9050     { PREFIX_TABLE (PREFIX_VEX_0F3828) },
   9051     { PREFIX_TABLE (PREFIX_VEX_0F3829) },
   9052     { PREFIX_TABLE (PREFIX_VEX_0F382A) },
   9053     { PREFIX_TABLE (PREFIX_VEX_0F382B) },
   9054     { PREFIX_TABLE (PREFIX_VEX_0F382C) },
   9055     { PREFIX_TABLE (PREFIX_VEX_0F382D) },
   9056     { PREFIX_TABLE (PREFIX_VEX_0F382E) },
   9057     { PREFIX_TABLE (PREFIX_VEX_0F382F) },
   9058     /* 30 */
   9059     { PREFIX_TABLE (PREFIX_VEX_0F3830) },
   9060     { PREFIX_TABLE (PREFIX_VEX_0F3831) },
   9061     { PREFIX_TABLE (PREFIX_VEX_0F3832) },
   9062     { PREFIX_TABLE (PREFIX_VEX_0F3833) },
   9063     { PREFIX_TABLE (PREFIX_VEX_0F3834) },
   9064     { PREFIX_TABLE (PREFIX_VEX_0F3835) },
   9065     { PREFIX_TABLE (PREFIX_VEX_0F3836) },
   9066     { PREFIX_TABLE (PREFIX_VEX_0F3837) },
   9067     /* 38 */
   9068     { PREFIX_TABLE (PREFIX_VEX_0F3838) },
   9069     { PREFIX_TABLE (PREFIX_VEX_0F3839) },
   9070     { PREFIX_TABLE (PREFIX_VEX_0F383A) },
   9071     { PREFIX_TABLE (PREFIX_VEX_0F383B) },
   9072     { PREFIX_TABLE (PREFIX_VEX_0F383C) },
   9073     { PREFIX_TABLE (PREFIX_VEX_0F383D) },
   9074     { PREFIX_TABLE (PREFIX_VEX_0F383E) },
   9075     { PREFIX_TABLE (PREFIX_VEX_0F383F) },
   9076     /* 40 */
   9077     { PREFIX_TABLE (PREFIX_VEX_0F3840) },
   9078     { PREFIX_TABLE (PREFIX_VEX_0F3841) },
   9079     { Bad_Opcode },
   9080     { Bad_Opcode },
   9081     { Bad_Opcode },
   9082     { PREFIX_TABLE (PREFIX_VEX_0F3845) },
   9083     { PREFIX_TABLE (PREFIX_VEX_0F3846) },
   9084     { PREFIX_TABLE (PREFIX_VEX_0F3847) },
   9085     /* 48 */
   9086     { Bad_Opcode },
   9087     { Bad_Opcode },
   9088     { Bad_Opcode },
   9089     { Bad_Opcode },
   9090     { Bad_Opcode },
   9091     { Bad_Opcode },
   9092     { Bad_Opcode },
   9093     { Bad_Opcode },
   9094     /* 50 */
   9095     { Bad_Opcode },
   9096     { Bad_Opcode },
   9097     { Bad_Opcode },
   9098     { Bad_Opcode },
   9099     { Bad_Opcode },
   9100     { Bad_Opcode },
   9101     { Bad_Opcode },
   9102     { Bad_Opcode },
   9103     /* 58 */
   9104     { PREFIX_TABLE (PREFIX_VEX_0F3858) },
   9105     { PREFIX_TABLE (PREFIX_VEX_0F3859) },
   9106     { PREFIX_TABLE (PREFIX_VEX_0F385A) },
   9107     { Bad_Opcode },
   9108     { Bad_Opcode },
   9109     { Bad_Opcode },
   9110     { Bad_Opcode },
   9111     { Bad_Opcode },
   9112     /* 60 */
   9113     { Bad_Opcode },
   9114     { Bad_Opcode },
   9115     { Bad_Opcode },
   9116     { Bad_Opcode },
   9117     { Bad_Opcode },
   9118     { Bad_Opcode },
   9119     { Bad_Opcode },
   9120     { Bad_Opcode },
   9121     /* 68 */
   9122     { Bad_Opcode },
   9123     { Bad_Opcode },
   9124     { Bad_Opcode },
   9125     { Bad_Opcode },
   9126     { Bad_Opcode },
   9127     { Bad_Opcode },
   9128     { Bad_Opcode },
   9129     { Bad_Opcode },
   9130     /* 70 */
   9131     { Bad_Opcode },
   9132     { Bad_Opcode },
   9133     { Bad_Opcode },
   9134     { Bad_Opcode },
   9135     { Bad_Opcode },
   9136     { Bad_Opcode },
   9137     { Bad_Opcode },
   9138     { Bad_Opcode },
   9139     /* 78 */
   9140     { PREFIX_TABLE (PREFIX_VEX_0F3878) },
   9141     { PREFIX_TABLE (PREFIX_VEX_0F3879) },
   9142     { Bad_Opcode },
   9143     { Bad_Opcode },
   9144     { Bad_Opcode },
   9145     { Bad_Opcode },
   9146     { Bad_Opcode },
   9147     { Bad_Opcode },
   9148     /* 80 */
   9149     { Bad_Opcode },
   9150     { Bad_Opcode },
   9151     { Bad_Opcode },
   9152     { Bad_Opcode },
   9153     { Bad_Opcode },
   9154     { Bad_Opcode },
   9155     { Bad_Opcode },
   9156     { Bad_Opcode },
   9157     /* 88 */
   9158     { Bad_Opcode },
   9159     { Bad_Opcode },
   9160     { Bad_Opcode },
   9161     { Bad_Opcode },
   9162     { PREFIX_TABLE (PREFIX_VEX_0F388C) },
   9163     { Bad_Opcode },
   9164     { PREFIX_TABLE (PREFIX_VEX_0F388E) },
   9165     { Bad_Opcode },
   9166     /* 90 */
   9167     { PREFIX_TABLE (PREFIX_VEX_0F3890) },
   9168     { PREFIX_TABLE (PREFIX_VEX_0F3891) },
   9169     { PREFIX_TABLE (PREFIX_VEX_0F3892) },
   9170     { PREFIX_TABLE (PREFIX_VEX_0F3893) },
   9171     { Bad_Opcode },
   9172     { Bad_Opcode },
   9173     { PREFIX_TABLE (PREFIX_VEX_0F3896) },
   9174     { PREFIX_TABLE (PREFIX_VEX_0F3897) },
   9175     /* 98 */
   9176     { PREFIX_TABLE (PREFIX_VEX_0F3898) },
   9177     { PREFIX_TABLE (PREFIX_VEX_0F3899) },
   9178     { PREFIX_TABLE (PREFIX_VEX_0F389A) },
   9179     { PREFIX_TABLE (PREFIX_VEX_0F389B) },
   9180     { PREFIX_TABLE (PREFIX_VEX_0F389C) },
   9181     { PREFIX_TABLE (PREFIX_VEX_0F389D) },
   9182     { PREFIX_TABLE (PREFIX_VEX_0F389E) },
   9183     { PREFIX_TABLE (PREFIX_VEX_0F389F) },
   9184     /* a0 */
   9185     { Bad_Opcode },
   9186     { Bad_Opcode },
   9187     { Bad_Opcode },
   9188     { Bad_Opcode },
   9189     { Bad_Opcode },
   9190     { Bad_Opcode },
   9191     { PREFIX_TABLE (PREFIX_VEX_0F38A6) },
   9192     { PREFIX_TABLE (PREFIX_VEX_0F38A7) },
   9193     /* a8 */
   9194     { PREFIX_TABLE (PREFIX_VEX_0F38A8) },
   9195     { PREFIX_TABLE (PREFIX_VEX_0F38A9) },
   9196     { PREFIX_TABLE (PREFIX_VEX_0F38AA) },
   9197     { PREFIX_TABLE (PREFIX_VEX_0F38AB) },
   9198     { PREFIX_TABLE (PREFIX_VEX_0F38AC) },
   9199     { PREFIX_TABLE (PREFIX_VEX_0F38AD) },
   9200     { PREFIX_TABLE (PREFIX_VEX_0F38AE) },
   9201     { PREFIX_TABLE (PREFIX_VEX_0F38AF) },
   9202     /* b0 */
   9203     { Bad_Opcode },
   9204     { Bad_Opcode },
   9205     { Bad_Opcode },
   9206     { Bad_Opcode },
   9207     { Bad_Opcode },
   9208     { Bad_Opcode },
   9209     { PREFIX_TABLE (PREFIX_VEX_0F38B6) },
   9210     { PREFIX_TABLE (PREFIX_VEX_0F38B7) },
   9211     /* b8 */
   9212     { PREFIX_TABLE (PREFIX_VEX_0F38B8) },
   9213     { PREFIX_TABLE (PREFIX_VEX_0F38B9) },
   9214     { PREFIX_TABLE (PREFIX_VEX_0F38BA) },
   9215     { PREFIX_TABLE (PREFIX_VEX_0F38BB) },
   9216     { PREFIX_TABLE (PREFIX_VEX_0F38BC) },
   9217     { PREFIX_TABLE (PREFIX_VEX_0F38BD) },
   9218     { PREFIX_TABLE (PREFIX_VEX_0F38BE) },
   9219     { PREFIX_TABLE (PREFIX_VEX_0F38BF) },
   9220     /* c0 */
   9221     { Bad_Opcode },
   9222     { Bad_Opcode },
   9223     { Bad_Opcode },
   9224     { Bad_Opcode },
   9225     { Bad_Opcode },
   9226     { Bad_Opcode },
   9227     { Bad_Opcode },
   9228     { Bad_Opcode },
   9229     /* c8 */
   9230     { Bad_Opcode },
   9231     { Bad_Opcode },
   9232     { Bad_Opcode },
   9233     { Bad_Opcode },
   9234     { Bad_Opcode },
   9235     { Bad_Opcode },
   9236     { Bad_Opcode },
   9237     { Bad_Opcode },
   9238     /* d0 */
   9239     { Bad_Opcode },
   9240     { Bad_Opcode },
   9241     { Bad_Opcode },
   9242     { Bad_Opcode },
   9243     { Bad_Opcode },
   9244     { Bad_Opcode },
   9245     { Bad_Opcode },
   9246     { Bad_Opcode },
   9247     /* d8 */
   9248     { Bad_Opcode },
   9249     { Bad_Opcode },
   9250     { Bad_Opcode },
   9251     { PREFIX_TABLE (PREFIX_VEX_0F38DB) },
   9252     { PREFIX_TABLE (PREFIX_VEX_0F38DC) },
   9253     { PREFIX_TABLE (PREFIX_VEX_0F38DD) },
   9254     { PREFIX_TABLE (PREFIX_VEX_0F38DE) },
   9255     { PREFIX_TABLE (PREFIX_VEX_0F38DF) },
   9256     /* e0 */
   9257     { Bad_Opcode },
   9258     { Bad_Opcode },
   9259     { Bad_Opcode },
   9260     { Bad_Opcode },
   9261     { Bad_Opcode },
   9262     { Bad_Opcode },
   9263     { Bad_Opcode },
   9264     { Bad_Opcode },
   9265     /* e8 */
   9266     { Bad_Opcode },
   9267     { Bad_Opcode },
   9268     { Bad_Opcode },
   9269     { Bad_Opcode },
   9270     { Bad_Opcode },
   9271     { Bad_Opcode },
   9272     { Bad_Opcode },
   9273     { Bad_Opcode },
   9274     /* f0 */
   9275     { Bad_Opcode },
   9276     { Bad_Opcode },
   9277     { PREFIX_TABLE (PREFIX_VEX_0F38F2) },
   9278     { REG_TABLE (REG_VEX_0F38F3) },
   9279     { Bad_Opcode },
   9280     { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
   9281     { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
   9282     { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
   9283     /* f8 */
   9284     { Bad_Opcode },
   9285     { Bad_Opcode },
   9286     { Bad_Opcode },
   9287     { Bad_Opcode },
   9288     { Bad_Opcode },
   9289     { Bad_Opcode },
   9290     { Bad_Opcode },
   9291     { Bad_Opcode },
   9292   },
   9293   /* VEX_0F3A */
   9294   {
   9295     /* 00 */
   9296     { PREFIX_TABLE (PREFIX_VEX_0F3A00) },
   9297     { PREFIX_TABLE (PREFIX_VEX_0F3A01) },
   9298     { PREFIX_TABLE (PREFIX_VEX_0F3A02) },
   9299     { Bad_Opcode },
   9300     { PREFIX_TABLE (PREFIX_VEX_0F3A04) },
   9301     { PREFIX_TABLE (PREFIX_VEX_0F3A05) },
   9302     { PREFIX_TABLE (PREFIX_VEX_0F3A06) },
   9303     { Bad_Opcode },
   9304     /* 08 */
   9305     { PREFIX_TABLE (PREFIX_VEX_0F3A08) },
   9306     { PREFIX_TABLE (PREFIX_VEX_0F3A09) },
   9307     { PREFIX_TABLE (PREFIX_VEX_0F3A0A) },
   9308     { PREFIX_TABLE (PREFIX_VEX_0F3A0B) },
   9309     { PREFIX_TABLE (PREFIX_VEX_0F3A0C) },
   9310     { PREFIX_TABLE (PREFIX_VEX_0F3A0D) },
   9311     { PREFIX_TABLE (PREFIX_VEX_0F3A0E) },
   9312     { PREFIX_TABLE (PREFIX_VEX_0F3A0F) },
   9313     /* 10 */
   9314     { Bad_Opcode },
   9315     { Bad_Opcode },
   9316     { Bad_Opcode },
   9317     { Bad_Opcode },
   9318     { PREFIX_TABLE (PREFIX_VEX_0F3A14) },
   9319     { PREFIX_TABLE (PREFIX_VEX_0F3A15) },
   9320     { PREFIX_TABLE (PREFIX_VEX_0F3A16) },
   9321     { PREFIX_TABLE (PREFIX_VEX_0F3A17) },
   9322     /* 18 */
   9323     { PREFIX_TABLE (PREFIX_VEX_0F3A18) },
   9324     { PREFIX_TABLE (PREFIX_VEX_0F3A19) },
   9325     { Bad_Opcode },
   9326     { Bad_Opcode },
   9327     { Bad_Opcode },
   9328     { PREFIX_TABLE (PREFIX_VEX_0F3A1D) },
   9329     { Bad_Opcode },
   9330     { Bad_Opcode },
   9331     /* 20 */
   9332     { PREFIX_TABLE (PREFIX_VEX_0F3A20) },
   9333     { PREFIX_TABLE (PREFIX_VEX_0F3A21) },
   9334     { PREFIX_TABLE (PREFIX_VEX_0F3A22) },
   9335     { Bad_Opcode },
   9336     { Bad_Opcode },
   9337     { Bad_Opcode },
   9338     { Bad_Opcode },
   9339     { Bad_Opcode },
   9340     /* 28 */
   9341     { Bad_Opcode },
   9342     { Bad_Opcode },
   9343     { Bad_Opcode },
   9344     { Bad_Opcode },
   9345     { Bad_Opcode },
   9346     { Bad_Opcode },
   9347     { Bad_Opcode },
   9348     { Bad_Opcode },
   9349     /* 30 */
   9350     { PREFIX_TABLE (PREFIX_VEX_0F3A30) },
   9351     { PREFIX_TABLE (PREFIX_VEX_0F3A31) },
   9352     { PREFIX_TABLE (PREFIX_VEX_0F3A32) },
   9353     { PREFIX_TABLE (PREFIX_VEX_0F3A33) },
   9354     { Bad_Opcode },
   9355     { Bad_Opcode },
   9356     { Bad_Opcode },
   9357     { Bad_Opcode },
   9358     /* 38 */
   9359     { PREFIX_TABLE (PREFIX_VEX_0F3A38) },
   9360     { PREFIX_TABLE (PREFIX_VEX_0F3A39) },
   9361     { Bad_Opcode },
   9362     { Bad_Opcode },
   9363     { Bad_Opcode },
   9364     { Bad_Opcode },
   9365     { Bad_Opcode },
   9366     { Bad_Opcode },
   9367     /* 40 */
   9368     { PREFIX_TABLE (PREFIX_VEX_0F3A40) },
   9369     { PREFIX_TABLE (PREFIX_VEX_0F3A41) },
   9370     { PREFIX_TABLE (PREFIX_VEX_0F3A42) },
   9371     { Bad_Opcode },
   9372     { PREFIX_TABLE (PREFIX_VEX_0F3A44) },
   9373     { Bad_Opcode },
   9374     { PREFIX_TABLE (PREFIX_VEX_0F3A46) },
   9375     { Bad_Opcode },
   9376     /* 48 */
   9377     { PREFIX_TABLE (PREFIX_VEX_0F3A48) },
   9378     { PREFIX_TABLE (PREFIX_VEX_0F3A49) },
   9379     { PREFIX_TABLE (PREFIX_VEX_0F3A4A) },
   9380     { PREFIX_TABLE (PREFIX_VEX_0F3A4B) },
   9381     { PREFIX_TABLE (PREFIX_VEX_0F3A4C) },
   9382     { Bad_Opcode },
   9383     { Bad_Opcode },
   9384     { Bad_Opcode },
   9385     /* 50 */
   9386     { Bad_Opcode },
   9387     { Bad_Opcode },
   9388     { Bad_Opcode },
   9389     { Bad_Opcode },
   9390     { Bad_Opcode },
   9391     { Bad_Opcode },
   9392     { Bad_Opcode },
   9393     { Bad_Opcode },
   9394     /* 58 */
   9395     { Bad_Opcode },
   9396     { Bad_Opcode },
   9397     { Bad_Opcode },
   9398     { Bad_Opcode },
   9399     { PREFIX_TABLE (PREFIX_VEX_0F3A5C) },
   9400     { PREFIX_TABLE (PREFIX_VEX_0F3A5D) },
   9401     { PREFIX_TABLE (PREFIX_VEX_0F3A5E) },
   9402     { PREFIX_TABLE (PREFIX_VEX_0F3A5F) },
   9403     /* 60 */
   9404     { PREFIX_TABLE (PREFIX_VEX_0F3A60) },
   9405     { PREFIX_TABLE (PREFIX_VEX_0F3A61) },
   9406     { PREFIX_TABLE (PREFIX_VEX_0F3A62) },
   9407     { PREFIX_TABLE (PREFIX_VEX_0F3A63) },
   9408     { Bad_Opcode },
   9409     { Bad_Opcode },
   9410     { Bad_Opcode },
   9411     { Bad_Opcode },
   9412     /* 68 */
   9413     { PREFIX_TABLE (PREFIX_VEX_0F3A68) },
   9414     { PREFIX_TABLE (PREFIX_VEX_0F3A69) },
   9415     { PREFIX_TABLE (PREFIX_VEX_0F3A6A) },
   9416     { PREFIX_TABLE (PREFIX_VEX_0F3A6B) },
   9417     { PREFIX_TABLE (PREFIX_VEX_0F3A6C) },
   9418     { PREFIX_TABLE (PREFIX_VEX_0F3A6D) },
   9419     { PREFIX_TABLE (PREFIX_VEX_0F3A6E) },
   9420     { PREFIX_TABLE (PREFIX_VEX_0F3A6F) },
   9421     /* 70 */
   9422     { Bad_Opcode },
   9423     { Bad_Opcode },
   9424     { Bad_Opcode },
   9425     { Bad_Opcode },
   9426     { Bad_Opcode },
   9427     { Bad_Opcode },
   9428     { Bad_Opcode },
   9429     { Bad_Opcode },
   9430     /* 78 */
   9431     { PREFIX_TABLE (PREFIX_VEX_0F3A78) },
   9432     { PREFIX_TABLE (PREFIX_VEX_0F3A79) },
   9433     { PREFIX_TABLE (PREFIX_VEX_0F3A7A) },
   9434     { PREFIX_TABLE (PREFIX_VEX_0F3A7B) },
   9435     { PREFIX_TABLE (PREFIX_VEX_0F3A7C) },
   9436     { PREFIX_TABLE (PREFIX_VEX_0F3A7D) },
   9437     { PREFIX_TABLE (PREFIX_VEX_0F3A7E) },
   9438     { PREFIX_TABLE (PREFIX_VEX_0F3A7F) },
   9439     /* 80 */
   9440     { Bad_Opcode },
   9441     { Bad_Opcode },
   9442     { Bad_Opcode },
   9443     { Bad_Opcode },
   9444     { Bad_Opcode },
   9445     { Bad_Opcode },
   9446     { Bad_Opcode },
   9447     { Bad_Opcode },
   9448     /* 88 */
   9449     { Bad_Opcode },
   9450     { Bad_Opcode },
   9451     { Bad_Opcode },
   9452     { Bad_Opcode },
   9453     { Bad_Opcode },
   9454     { Bad_Opcode },
   9455     { Bad_Opcode },
   9456     { Bad_Opcode },
   9457     /* 90 */
   9458     { Bad_Opcode },
   9459     { Bad_Opcode },
   9460     { Bad_Opcode },
   9461     { Bad_Opcode },
   9462     { Bad_Opcode },
   9463     { Bad_Opcode },
   9464     { Bad_Opcode },
   9465     { Bad_Opcode },
   9466     /* 98 */
   9467     { Bad_Opcode },
   9468     { Bad_Opcode },
   9469     { Bad_Opcode },
   9470     { Bad_Opcode },
   9471     { Bad_Opcode },
   9472     { Bad_Opcode },
   9473     { Bad_Opcode },
   9474     { Bad_Opcode },
   9475     /* a0 */
   9476     { Bad_Opcode },
   9477     { Bad_Opcode },
   9478     { Bad_Opcode },
   9479     { Bad_Opcode },
   9480     { Bad_Opcode },
   9481     { Bad_Opcode },
   9482     { Bad_Opcode },
   9483     { Bad_Opcode },
   9484     /* a8 */
   9485     { Bad_Opcode },
   9486     { Bad_Opcode },
   9487     { Bad_Opcode },
   9488     { Bad_Opcode },
   9489     { Bad_Opcode },
   9490     { Bad_Opcode },
   9491     { Bad_Opcode },
   9492     { Bad_Opcode },
   9493     /* b0 */
   9494     { Bad_Opcode },
   9495     { Bad_Opcode },
   9496     { Bad_Opcode },
   9497     { Bad_Opcode },
   9498     { Bad_Opcode },
   9499     { Bad_Opcode },
   9500     { Bad_Opcode },
   9501     { Bad_Opcode },
   9502     /* b8 */
   9503     { Bad_Opcode },
   9504     { Bad_Opcode },
   9505     { Bad_Opcode },
   9506     { Bad_Opcode },
   9507     { Bad_Opcode },
   9508     { Bad_Opcode },
   9509     { Bad_Opcode },
   9510     { Bad_Opcode },
   9511     /* c0 */
   9512     { Bad_Opcode },
   9513     { Bad_Opcode },
   9514     { Bad_Opcode },
   9515     { Bad_Opcode },
   9516     { Bad_Opcode },
   9517     { Bad_Opcode },
   9518     { Bad_Opcode },
   9519     { Bad_Opcode },
   9520     /* c8 */
   9521     { Bad_Opcode },
   9522     { Bad_Opcode },
   9523     { Bad_Opcode },
   9524     { Bad_Opcode },
   9525     { Bad_Opcode },
   9526     { Bad_Opcode },
   9527     { Bad_Opcode },
   9528     { Bad_Opcode },
   9529     /* d0 */
   9530     { Bad_Opcode },
   9531     { Bad_Opcode },
   9532     { Bad_Opcode },
   9533     { Bad_Opcode },
   9534     { Bad_Opcode },
   9535     { Bad_Opcode },
   9536     { Bad_Opcode },
   9537     { Bad_Opcode },
   9538     /* d8 */
   9539     { Bad_Opcode },
   9540     { Bad_Opcode },
   9541     { Bad_Opcode },
   9542     { Bad_Opcode },
   9543     { Bad_Opcode },
   9544     { Bad_Opcode },
   9545     { Bad_Opcode },
   9546     { PREFIX_TABLE (PREFIX_VEX_0F3ADF) },
   9547     /* e0 */
   9548     { Bad_Opcode },
   9549     { Bad_Opcode },
   9550     { Bad_Opcode },
   9551     { Bad_Opcode },
   9552     { Bad_Opcode },
   9553     { Bad_Opcode },
   9554     { Bad_Opcode },
   9555     { Bad_Opcode },
   9556     /* e8 */
   9557     { Bad_Opcode },
   9558     { Bad_Opcode },
   9559     { Bad_Opcode },
   9560     { Bad_Opcode },
   9561     { Bad_Opcode },
   9562     { Bad_Opcode },
   9563     { Bad_Opcode },
   9564     { Bad_Opcode },
   9565     /* f0 */
   9566     { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
   9567     { Bad_Opcode },
   9568     { Bad_Opcode },
   9569     { Bad_Opcode },
   9570     { Bad_Opcode },
   9571     { Bad_Opcode },
   9572     { Bad_Opcode },
   9573     { Bad_Opcode },
   9574     /* f8 */
   9575     { Bad_Opcode },
   9576     { Bad_Opcode },
   9577     { Bad_Opcode },
   9578     { Bad_Opcode },
   9579     { Bad_Opcode },
   9580     { Bad_Opcode },
   9581     { Bad_Opcode },
   9582     { Bad_Opcode },
   9583   },
   9584 };
   9585 
   9586 #define NEED_OPCODE_TABLE
   9587 #include "i386-dis-evex.h"
   9588 #undef NEED_OPCODE_TABLE
   9589 static const struct dis386 vex_len_table[][2] = {
   9590   /* VEX_LEN_0F10_P_1 */
   9591   {
   9592     { VEX_W_TABLE (VEX_W_0F10_P_1) },
   9593     { VEX_W_TABLE (VEX_W_0F10_P_1) },
   9594   },
   9595 
   9596   /* VEX_LEN_0F10_P_3 */
   9597   {
   9598     { VEX_W_TABLE (VEX_W_0F10_P_3) },
   9599     { VEX_W_TABLE (VEX_W_0F10_P_3) },
   9600   },
   9601 
   9602   /* VEX_LEN_0F11_P_1 */
   9603   {
   9604     { VEX_W_TABLE (VEX_W_0F11_P_1) },
   9605     { VEX_W_TABLE (VEX_W_0F11_P_1) },
   9606   },
   9607 
   9608   /* VEX_LEN_0F11_P_3 */
   9609   {
   9610     { VEX_W_TABLE (VEX_W_0F11_P_3) },
   9611     { VEX_W_TABLE (VEX_W_0F11_P_3) },
   9612   },
   9613 
   9614   /* VEX_LEN_0F12_P_0_M_0 */
   9615   {
   9616     { VEX_W_TABLE (VEX_W_0F12_P_0_M_0) },
   9617   },
   9618 
   9619   /* VEX_LEN_0F12_P_0_M_1 */
   9620   {
   9621     { VEX_W_TABLE (VEX_W_0F12_P_0_M_1) },
   9622   },
   9623 
   9624   /* VEX_LEN_0F12_P_2 */
   9625   {
   9626     { VEX_W_TABLE (VEX_W_0F12_P_2) },
   9627   },
   9628 
   9629   /* VEX_LEN_0F13_M_0 */
   9630   {
   9631     { VEX_W_TABLE (VEX_W_0F13_M_0) },
   9632   },
   9633 
   9634   /* VEX_LEN_0F16_P_0_M_0 */
   9635   {
   9636     { VEX_W_TABLE (VEX_W_0F16_P_0_M_0) },
   9637   },
   9638 
   9639   /* VEX_LEN_0F16_P_0_M_1 */
   9640   {
   9641     { VEX_W_TABLE (VEX_W_0F16_P_0_M_1) },
   9642   },
   9643 
   9644   /* VEX_LEN_0F16_P_2 */
   9645   {
   9646     { VEX_W_TABLE (VEX_W_0F16_P_2) },
   9647   },
   9648 
   9649   /* VEX_LEN_0F17_M_0 */
   9650   {
   9651     { VEX_W_TABLE (VEX_W_0F17_M_0) },
   9652   },
   9653 
   9654   /* VEX_LEN_0F2A_P_1 */
   9655   {
   9656     { "vcvtsi2ss%LQ",	{ XMScalar, VexScalar, Ev }, 0 },
   9657     { "vcvtsi2ss%LQ",	{ XMScalar, VexScalar, Ev }, 0 },
   9658   },
   9659 
   9660   /* VEX_LEN_0F2A_P_3 */
   9661   {
   9662     { "vcvtsi2sd%LQ",	{ XMScalar, VexScalar, Ev }, 0 },
   9663     { "vcvtsi2sd%LQ",	{ XMScalar, VexScalar, Ev }, 0 },
   9664   },
   9665 
   9666   /* VEX_LEN_0F2C_P_1 */
   9667   {
   9668     { "vcvttss2siY",	{ Gv, EXdScalar }, 0 },
   9669     { "vcvttss2siY",	{ Gv, EXdScalar }, 0 },
   9670   },
   9671 
   9672   /* VEX_LEN_0F2C_P_3 */
   9673   {
   9674     { "vcvttsd2siY",	{ Gv, EXqScalar }, 0 },
   9675     { "vcvttsd2siY",	{ Gv, EXqScalar }, 0 },
   9676   },
   9677 
   9678   /* VEX_LEN_0F2D_P_1 */
   9679   {
   9680     { "vcvtss2siY",	{ Gv, EXdScalar }, 0 },
   9681     { "vcvtss2siY",	{ Gv, EXdScalar }, 0 },
   9682   },
   9683 
   9684   /* VEX_LEN_0F2D_P_3 */
   9685   {
   9686     { "vcvtsd2siY",	{ Gv, EXqScalar }, 0 },
   9687     { "vcvtsd2siY",	{ Gv, EXqScalar }, 0 },
   9688   },
   9689 
   9690   /* VEX_LEN_0F2E_P_0 */
   9691   {
   9692     { VEX_W_TABLE (VEX_W_0F2E_P_0) },
   9693     { VEX_W_TABLE (VEX_W_0F2E_P_0) },
   9694   },
   9695 
   9696   /* VEX_LEN_0F2E_P_2 */
   9697   {
   9698     { VEX_W_TABLE (VEX_W_0F2E_P_2) },
   9699     { VEX_W_TABLE (VEX_W_0F2E_P_2) },
   9700   },
   9701 
   9702   /* VEX_LEN_0F2F_P_0 */
   9703   {
   9704     { VEX_W_TABLE (VEX_W_0F2F_P_0) },
   9705     { VEX_W_TABLE (VEX_W_0F2F_P_0) },
   9706   },
   9707 
   9708   /* VEX_LEN_0F2F_P_2 */
   9709   {
   9710     { VEX_W_TABLE (VEX_W_0F2F_P_2) },
   9711     { VEX_W_TABLE (VEX_W_0F2F_P_2) },
   9712   },
   9713 
   9714   /* VEX_LEN_0F41_P_0 */
   9715   {
   9716     { Bad_Opcode },
   9717     { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) },
   9718   },
   9719   /* VEX_LEN_0F41_P_2 */
   9720   {
   9721     { Bad_Opcode },
   9722     { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) },
   9723   },
   9724   /* VEX_LEN_0F42_P_0 */
   9725   {
   9726     { Bad_Opcode },
   9727     { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) },
   9728   },
   9729   /* VEX_LEN_0F42_P_2 */
   9730   {
   9731     { Bad_Opcode },
   9732     { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) },
   9733   },
   9734   /* VEX_LEN_0F44_P_0 */
   9735   {
   9736     { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) },
   9737   },
   9738   /* VEX_LEN_0F44_P_2 */
   9739   {
   9740     { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) },
   9741   },
   9742   /* VEX_LEN_0F45_P_0 */
   9743   {
   9744     { Bad_Opcode },
   9745     { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) },
   9746   },
   9747   /* VEX_LEN_0F45_P_2 */
   9748   {
   9749     { Bad_Opcode },
   9750     { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) },
   9751   },
   9752   /* VEX_LEN_0F46_P_0 */
   9753   {
   9754     { Bad_Opcode },
   9755     { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) },
   9756   },
   9757   /* VEX_LEN_0F46_P_2 */
   9758   {
   9759     { Bad_Opcode },
   9760     { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) },
   9761   },
   9762   /* VEX_LEN_0F47_P_0 */
   9763   {
   9764     { Bad_Opcode },
   9765     { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) },
   9766   },
   9767   /* VEX_LEN_0F47_P_2 */
   9768   {
   9769     { Bad_Opcode },
   9770     { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) },
   9771   },
   9772   /* VEX_LEN_0F4A_P_0 */
   9773   {
   9774     { Bad_Opcode },
   9775     { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) },
   9776   },
   9777   /* VEX_LEN_0F4A_P_2 */
   9778   {
   9779     { Bad_Opcode },
   9780     { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) },
   9781   },
   9782   /* VEX_LEN_0F4B_P_0 */
   9783   {
   9784     { Bad_Opcode },
   9785     { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) },
   9786   },
   9787   /* VEX_LEN_0F4B_P_2 */
   9788   {
   9789     { Bad_Opcode },
   9790     { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) },
   9791   },
   9792 
   9793   /* VEX_LEN_0F51_P_1 */
   9794   {
   9795     { VEX_W_TABLE (VEX_W_0F51_P_1) },
   9796     { VEX_W_TABLE (VEX_W_0F51_P_1) },
   9797   },
   9798 
   9799   /* VEX_LEN_0F51_P_3 */
   9800   {
   9801     { VEX_W_TABLE (VEX_W_0F51_P_3) },
   9802     { VEX_W_TABLE (VEX_W_0F51_P_3) },
   9803   },
   9804 
   9805   /* VEX_LEN_0F52_P_1 */
   9806   {
   9807     { VEX_W_TABLE (VEX_W_0F52_P_1) },
   9808     { VEX_W_TABLE (VEX_W_0F52_P_1) },
   9809   },
   9810 
   9811   /* VEX_LEN_0F53_P_1 */
   9812   {
   9813     { VEX_W_TABLE (VEX_W_0F53_P_1) },
   9814     { VEX_W_TABLE (VEX_W_0F53_P_1) },
   9815   },
   9816 
   9817   /* VEX_LEN_0F58_P_1 */
   9818   {
   9819     { VEX_W_TABLE (VEX_W_0F58_P_1) },
   9820     { VEX_W_TABLE (VEX_W_0F58_P_1) },
   9821   },
   9822 
   9823   /* VEX_LEN_0F58_P_3 */
   9824   {
   9825     { VEX_W_TABLE (VEX_W_0F58_P_3) },
   9826     { VEX_W_TABLE (VEX_W_0F58_P_3) },
   9827   },
   9828 
   9829   /* VEX_LEN_0F59_P_1 */
   9830   {
   9831     { VEX_W_TABLE (VEX_W_0F59_P_1) },
   9832     { VEX_W_TABLE (VEX_W_0F59_P_1) },
   9833   },
   9834 
   9835   /* VEX_LEN_0F59_P_3 */
   9836   {
   9837     { VEX_W_TABLE (VEX_W_0F59_P_3) },
   9838     { VEX_W_TABLE (VEX_W_0F59_P_3) },
   9839   },
   9840 
   9841   /* VEX_LEN_0F5A_P_1 */
   9842   {
   9843     { VEX_W_TABLE (VEX_W_0F5A_P_1) },
   9844     { VEX_W_TABLE (VEX_W_0F5A_P_1) },
   9845   },
   9846 
   9847   /* VEX_LEN_0F5A_P_3 */
   9848   {
   9849     { VEX_W_TABLE (VEX_W_0F5A_P_3) },
   9850     { VEX_W_TABLE (VEX_W_0F5A_P_3) },
   9851   },
   9852 
   9853   /* VEX_LEN_0F5C_P_1 */
   9854   {
   9855     { VEX_W_TABLE (VEX_W_0F5C_P_1) },
   9856     { VEX_W_TABLE (VEX_W_0F5C_P_1) },
   9857   },
   9858 
   9859   /* VEX_LEN_0F5C_P_3 */
   9860   {
   9861     { VEX_W_TABLE (VEX_W_0F5C_P_3) },
   9862     { VEX_W_TABLE (VEX_W_0F5C_P_3) },
   9863   },
   9864 
   9865   /* VEX_LEN_0F5D_P_1 */
   9866   {
   9867     { VEX_W_TABLE (VEX_W_0F5D_P_1) },
   9868     { VEX_W_TABLE (VEX_W_0F5D_P_1) },
   9869   },
   9870 
   9871   /* VEX_LEN_0F5D_P_3 */
   9872   {
   9873     { VEX_W_TABLE (VEX_W_0F5D_P_3) },
   9874     { VEX_W_TABLE (VEX_W_0F5D_P_3) },
   9875   },
   9876 
   9877   /* VEX_LEN_0F5E_P_1 */
   9878   {
   9879     { VEX_W_TABLE (VEX_W_0F5E_P_1) },
   9880     { VEX_W_TABLE (VEX_W_0F5E_P_1) },
   9881   },
   9882 
   9883   /* VEX_LEN_0F5E_P_3 */
   9884   {
   9885     { VEX_W_TABLE (VEX_W_0F5E_P_3) },
   9886     { VEX_W_TABLE (VEX_W_0F5E_P_3) },
   9887   },
   9888 
   9889   /* VEX_LEN_0F5F_P_1 */
   9890   {
   9891     { VEX_W_TABLE (VEX_W_0F5F_P_1) },
   9892     { VEX_W_TABLE (VEX_W_0F5F_P_1) },
   9893   },
   9894 
   9895   /* VEX_LEN_0F5F_P_3 */
   9896   {
   9897     { VEX_W_TABLE (VEX_W_0F5F_P_3) },
   9898     { VEX_W_TABLE (VEX_W_0F5F_P_3) },
   9899   },
   9900 
   9901   /* VEX_LEN_0F6E_P_2 */
   9902   {
   9903     { "vmovK",		{ XMScalar, Edq }, 0 },
   9904     { "vmovK",		{ XMScalar, Edq }, 0 },
   9905   },
   9906 
   9907   /* VEX_LEN_0F7E_P_1 */
   9908   {
   9909     { VEX_W_TABLE (VEX_W_0F7E_P_1) },
   9910     { VEX_W_TABLE (VEX_W_0F7E_P_1) },
   9911   },
   9912 
   9913   /* VEX_LEN_0F7E_P_2 */
   9914   {
   9915     { "vmovK",		{ Edq, XMScalar }, 0 },
   9916     { "vmovK",		{ Edq, XMScalar }, 0 },
   9917   },
   9918 
   9919   /* VEX_LEN_0F90_P_0 */
   9920   {
   9921     { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) },
   9922   },
   9923 
   9924   /* VEX_LEN_0F90_P_2 */
   9925   {
   9926     { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) },
   9927   },
   9928 
   9929   /* VEX_LEN_0F91_P_0 */
   9930   {
   9931     { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) },
   9932   },
   9933 
   9934   /* VEX_LEN_0F91_P_2 */
   9935   {
   9936     { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) },
   9937   },
   9938 
   9939   /* VEX_LEN_0F92_P_0 */
   9940   {
   9941     { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) },
   9942   },
   9943 
   9944   /* VEX_LEN_0F92_P_2 */
   9945   {
   9946     { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) },
   9947   },
   9948 
   9949   /* VEX_LEN_0F92_P_3 */
   9950   {
   9951     { VEX_W_TABLE (VEX_W_0F92_P_3_LEN_0) },
   9952   },
   9953 
   9954   /* VEX_LEN_0F93_P_0 */
   9955   {
   9956     { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) },
   9957   },
   9958 
   9959   /* VEX_LEN_0F93_P_2 */
   9960   {
   9961     { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) },
   9962   },
   9963 
   9964   /* VEX_LEN_0F93_P_3 */
   9965   {
   9966     { VEX_W_TABLE (VEX_W_0F93_P_3_LEN_0) },
   9967   },
   9968 
   9969   /* VEX_LEN_0F98_P_0 */
   9970   {
   9971     { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) },
   9972   },
   9973 
   9974   /* VEX_LEN_0F98_P_2 */
   9975   {
   9976     { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) },
   9977   },
   9978 
   9979   /* VEX_LEN_0F99_P_0 */
   9980   {
   9981     { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) },
   9982   },
   9983 
   9984   /* VEX_LEN_0F99_P_2 */
   9985   {
   9986     { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) },
   9987   },
   9988 
   9989   /* VEX_LEN_0FAE_R_2_M_0 */
   9990   {
   9991     { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0) },
   9992   },
   9993 
   9994   /* VEX_LEN_0FAE_R_3_M_0 */
   9995   {
   9996     { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0) },
   9997   },
   9998 
   9999   /* VEX_LEN_0FC2_P_1 */
   10000   {
   10001     { VEX_W_TABLE (VEX_W_0FC2_P_1) },
   10002     { VEX_W_TABLE (VEX_W_0FC2_P_1) },
   10003   },
   10004 
   10005   /* VEX_LEN_0FC2_P_3 */
   10006   {
   10007     { VEX_W_TABLE (VEX_W_0FC2_P_3) },
   10008     { VEX_W_TABLE (VEX_W_0FC2_P_3) },
   10009   },
   10010 
   10011   /* VEX_LEN_0FC4_P_2 */
   10012   {
   10013     { VEX_W_TABLE (VEX_W_0FC4_P_2) },
   10014   },
   10015 
   10016   /* VEX_LEN_0FC5_P_2 */
   10017   {
   10018     { VEX_W_TABLE (VEX_W_0FC5_P_2) },
   10019   },
   10020 
   10021   /* VEX_LEN_0FD6_P_2 */
   10022   {
   10023     { VEX_W_TABLE (VEX_W_0FD6_P_2) },
   10024     { VEX_W_TABLE (VEX_W_0FD6_P_2) },
   10025   },
   10026 
   10027   /* VEX_LEN_0FF7_P_2 */
   10028   {
   10029     { VEX_W_TABLE (VEX_W_0FF7_P_2) },
   10030   },
   10031 
   10032   /* VEX_LEN_0F3816_P_2 */
   10033   {
   10034     { Bad_Opcode },
   10035     { VEX_W_TABLE (VEX_W_0F3816_P_2) },
   10036   },
   10037 
   10038   /* VEX_LEN_0F3819_P_2 */
   10039   {
   10040     { Bad_Opcode },
   10041     { VEX_W_TABLE (VEX_W_0F3819_P_2) },
   10042   },
   10043 
   10044   /* VEX_LEN_0F381A_P_2_M_0 */
   10045   {
   10046     { Bad_Opcode },
   10047     { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) },
   10048   },
   10049 
   10050   /* VEX_LEN_0F3836_P_2 */
   10051   {
   10052     { Bad_Opcode },
   10053     { VEX_W_TABLE (VEX_W_0F3836_P_2) },
   10054   },
   10055 
   10056   /* VEX_LEN_0F3841_P_2 */
   10057   {
   10058     { VEX_W_TABLE (VEX_W_0F3841_P_2) },
   10059   },
   10060 
   10061   /* VEX_LEN_0F385A_P_2_M_0 */
   10062   {
   10063     { Bad_Opcode },
   10064     { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) },
   10065   },
   10066 
   10067   /* VEX_LEN_0F38DB_P_2 */
   10068   {
   10069     { VEX_W_TABLE (VEX_W_0F38DB_P_2) },
   10070   },
   10071 
   10072   /* VEX_LEN_0F38DC_P_2 */
   10073   {
   10074     { VEX_W_TABLE (VEX_W_0F38DC_P_2) },
   10075   },
   10076 
   10077   /* VEX_LEN_0F38DD_P_2 */
   10078   {
   10079     { VEX_W_TABLE (VEX_W_0F38DD_P_2) },
   10080   },
   10081 
   10082   /* VEX_LEN_0F38DE_P_2 */
   10083   {
   10084     { VEX_W_TABLE (VEX_W_0F38DE_P_2) },
   10085   },
   10086 
   10087   /* VEX_LEN_0F38DF_P_2 */
   10088   {
   10089     { VEX_W_TABLE (VEX_W_0F38DF_P_2) },
   10090   },
   10091 
   10092   /* VEX_LEN_0F38F2_P_0 */
   10093   {
   10094     { "andnS",		{ Gdq, VexGdq, Edq }, 0 },
   10095   },
   10096 
   10097   /* VEX_LEN_0F38F3_R_1_P_0 */
   10098   {
   10099     { "blsrS",		{ VexGdq, Edq }, 0 },
   10100   },
   10101 
   10102   /* VEX_LEN_0F38F3_R_2_P_0 */
   10103   {
   10104     { "blsmskS",	{ VexGdq, Edq }, 0 },
   10105   },
   10106 
   10107   /* VEX_LEN_0F38F3_R_3_P_0 */
   10108   {
   10109     { "blsiS",		{ VexGdq, Edq }, 0 },
   10110   },
   10111 
   10112   /* VEX_LEN_0F38F5_P_0 */
   10113   {
   10114     { "bzhiS",		{ Gdq, Edq, VexGdq }, 0 },
   10115   },
   10116 
   10117   /* VEX_LEN_0F38F5_P_1 */
   10118   {
   10119     { "pextS",		{ Gdq, VexGdq, Edq }, 0 },
   10120   },
   10121 
   10122   /* VEX_LEN_0F38F5_P_3 */
   10123   {
   10124     { "pdepS",		{ Gdq, VexGdq, Edq }, 0 },
   10125   },
   10126 
   10127   /* VEX_LEN_0F38F6_P_3 */
   10128   {
   10129     { "mulxS",		{ Gdq, VexGdq, Edq }, 0 },
   10130   },
   10131 
   10132   /* VEX_LEN_0F38F7_P_0 */
   10133   {
   10134     { "bextrS",		{ Gdq, Edq, VexGdq }, 0 },
   10135   },
   10136 
   10137   /* VEX_LEN_0F38F7_P_1 */
   10138   {
   10139     { "sarxS",		{ Gdq, Edq, VexGdq }, 0 },
   10140   },
   10141 
   10142   /* VEX_LEN_0F38F7_P_2 */
   10143   {
   10144     { "shlxS",		{ Gdq, Edq, VexGdq }, 0 },
   10145   },
   10146 
   10147   /* VEX_LEN_0F38F7_P_3 */
   10148   {
   10149     { "shrxS",		{ Gdq, Edq, VexGdq }, 0 },
   10150   },
   10151 
   10152   /* VEX_LEN_0F3A00_P_2 */
   10153   {
   10154     { Bad_Opcode },
   10155     { VEX_W_TABLE (VEX_W_0F3A00_P_2) },
   10156   },
   10157 
   10158   /* VEX_LEN_0F3A01_P_2 */
   10159   {
   10160     { Bad_Opcode },
   10161     { VEX_W_TABLE (VEX_W_0F3A01_P_2) },
   10162   },
   10163 
   10164   /* VEX_LEN_0F3A06_P_2 */
   10165   {
   10166     { Bad_Opcode },
   10167     { VEX_W_TABLE (VEX_W_0F3A06_P_2) },
   10168   },
   10169 
   10170   /* VEX_LEN_0F3A0A_P_2 */
   10171   {
   10172     { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
   10173     { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
   10174   },
   10175 
   10176   /* VEX_LEN_0F3A0B_P_2 */
   10177   {
   10178     { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
   10179     { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
   10180   },
   10181 
   10182   /* VEX_LEN_0F3A14_P_2 */
   10183   {
   10184     { VEX_W_TABLE (VEX_W_0F3A14_P_2) },
   10185   },
   10186 
   10187   /* VEX_LEN_0F3A15_P_2 */
   10188   {
   10189     { VEX_W_TABLE (VEX_W_0F3A15_P_2) },
   10190   },
   10191 
   10192   /* VEX_LEN_0F3A16_P_2  */
   10193   {
   10194     { "vpextrK",	{ Edq, XM, Ib }, 0 },
   10195   },
   10196 
   10197   /* VEX_LEN_0F3A17_P_2 */
   10198   {
   10199     { "vextractps",	{ Edqd, XM, Ib }, 0 },
   10200   },
   10201 
   10202   /* VEX_LEN_0F3A18_P_2 */
   10203   {
   10204     { Bad_Opcode },
   10205     { VEX_W_TABLE (VEX_W_0F3A18_P_2) },
   10206   },
   10207 
   10208   /* VEX_LEN_0F3A19_P_2 */
   10209   {
   10210     { Bad_Opcode },
   10211     { VEX_W_TABLE (VEX_W_0F3A19_P_2) },
   10212   },
   10213 
   10214   /* VEX_LEN_0F3A20_P_2 */
   10215   {
   10216     { VEX_W_TABLE (VEX_W_0F3A20_P_2) },
   10217   },
   10218 
   10219   /* VEX_LEN_0F3A21_P_2 */
   10220   {
   10221     { VEX_W_TABLE (VEX_W_0F3A21_P_2) },
   10222   },
   10223 
   10224   /* VEX_LEN_0F3A22_P_2 */
   10225   {
   10226     { "vpinsrK",	{ XM, Vex128, Edq, Ib }, 0 },
   10227   },
   10228 
   10229   /* VEX_LEN_0F3A30_P_2 */
   10230   {
   10231     { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) },
   10232   },
   10233 
   10234   /* VEX_LEN_0F3A31_P_2 */
   10235   {
   10236     { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) },
   10237   },
   10238 
   10239   /* VEX_LEN_0F3A32_P_2 */
   10240   {
   10241     { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) },
   10242   },
   10243 
   10244   /* VEX_LEN_0F3A33_P_2 */
   10245   {
   10246     { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) },
   10247   },
   10248 
   10249   /* VEX_LEN_0F3A38_P_2 */
   10250   {
   10251     { Bad_Opcode },
   10252     { VEX_W_TABLE (VEX_W_0F3A38_P_2) },
   10253   },
   10254 
   10255   /* VEX_LEN_0F3A39_P_2 */
   10256   {
   10257     { Bad_Opcode },
   10258     { VEX_W_TABLE (VEX_W_0F3A39_P_2) },
   10259   },
   10260 
   10261   /* VEX_LEN_0F3A41_P_2 */
   10262   {
   10263     { VEX_W_TABLE (VEX_W_0F3A41_P_2) },
   10264   },
   10265 
   10266   /* VEX_LEN_0F3A44_P_2 */
   10267   {
   10268     { VEX_W_TABLE (VEX_W_0F3A44_P_2) },
   10269   },
   10270 
   10271   /* VEX_LEN_0F3A46_P_2 */
   10272   {
   10273     { Bad_Opcode },
   10274     { VEX_W_TABLE (VEX_W_0F3A46_P_2) },
   10275   },
   10276 
   10277   /* VEX_LEN_0F3A60_P_2 */
   10278   {
   10279     { VEX_W_TABLE (VEX_W_0F3A60_P_2) },
   10280   },
   10281 
   10282   /* VEX_LEN_0F3A61_P_2 */
   10283   {
   10284     { VEX_W_TABLE (VEX_W_0F3A61_P_2) },
   10285   },
   10286 
   10287   /* VEX_LEN_0F3A62_P_2 */
   10288   {
   10289     { VEX_W_TABLE (VEX_W_0F3A62_P_2) },
   10290   },
   10291 
   10292   /* VEX_LEN_0F3A63_P_2 */
   10293   {
   10294     { VEX_W_TABLE (VEX_W_0F3A63_P_2) },
   10295   },
   10296 
   10297   /* VEX_LEN_0F3A6A_P_2 */
   10298   {
   10299     { "vfmaddss",	{ XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
   10300   },
   10301 
   10302   /* VEX_LEN_0F3A6B_P_2 */
   10303   {
   10304     { "vfmaddsd",	{ XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
   10305   },
   10306 
   10307   /* VEX_LEN_0F3A6E_P_2 */
   10308   {
   10309     { "vfmsubss",	{ XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
   10310   },
   10311 
   10312   /* VEX_LEN_0F3A6F_P_2 */
   10313   {
   10314     { "vfmsubsd",	{ XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
   10315   },
   10316 
   10317   /* VEX_LEN_0F3A7A_P_2 */
   10318   {
   10319     { "vfnmaddss",	{ XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
   10320   },
   10321 
   10322   /* VEX_LEN_0F3A7B_P_2 */
   10323   {
   10324     { "vfnmaddsd",	{ XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
   10325   },
   10326 
   10327   /* VEX_LEN_0F3A7E_P_2 */
   10328   {
   10329     { "vfnmsubss",	{ XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
   10330   },
   10331 
   10332   /* VEX_LEN_0F3A7F_P_2 */
   10333   {
   10334     { "vfnmsubsd",	{ XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
   10335   },
   10336 
   10337   /* VEX_LEN_0F3ADF_P_2 */
   10338   {
   10339     { VEX_W_TABLE (VEX_W_0F3ADF_P_2) },
   10340   },
   10341 
   10342   /* VEX_LEN_0F3AF0_P_3 */
   10343   {
   10344     { "rorxS",		{ Gdq, Edq, Ib }, 0 },
   10345   },
   10346 
   10347   /* VEX_LEN_0FXOP_08_CC */
   10348   {
   10349      { "vpcomb",	{ XM, Vex128, EXx, Ib }, 0 },
   10350   },
   10351 
   10352   /* VEX_LEN_0FXOP_08_CD */
   10353   {
   10354      { "vpcomw",	{ XM, Vex128, EXx, Ib }, 0 },
   10355   },
   10356 
   10357   /* VEX_LEN_0FXOP_08_CE */
   10358   {
   10359      { "vpcomd",	{ XM, Vex128, EXx, Ib }, 0 },
   10360   },
   10361 
   10362   /* VEX_LEN_0FXOP_08_CF */
   10363   {
   10364      { "vpcomq",	{ XM, Vex128, EXx, Ib }, 0 },
   10365   },
   10366 
   10367   /* VEX_LEN_0FXOP_08_EC */
   10368   {
   10369      { "vpcomub",	{ XM, Vex128, EXx, Ib }, 0 },
   10370   },
   10371 
   10372   /* VEX_LEN_0FXOP_08_ED */
   10373   {
   10374      { "vpcomuw",	{ XM, Vex128, EXx, Ib }, 0 },
   10375   },
   10376 
   10377   /* VEX_LEN_0FXOP_08_EE */
   10378   {
   10379      { "vpcomud",	{ XM, Vex128, EXx, Ib }, 0 },
   10380   },
   10381 
   10382   /* VEX_LEN_0FXOP_08_EF */
   10383   {
   10384      { "vpcomuq",	{ XM, Vex128, EXx, Ib }, 0 },
   10385   },
   10386 
   10387   /* VEX_LEN_0FXOP_09_80 */
   10388   {
   10389     { "vfrczps",	{ XM, EXxmm }, 0 },
   10390     { "vfrczps",	{ XM, EXymmq }, 0 },
   10391   },
   10392 
   10393   /* VEX_LEN_0FXOP_09_81 */
   10394   {
   10395     { "vfrczpd",	{ XM, EXxmm }, 0 },
   10396     { "vfrczpd",	{ XM, EXymmq }, 0 },
   10397   },
   10398 };
   10399 
   10400 static const struct dis386 vex_w_table[][2] = {
   10401   {
   10402     /* VEX_W_0F10_P_0 */
   10403     { "vmovups",	{ XM, EXx }, 0 },
   10404   },
   10405   {
   10406     /* VEX_W_0F10_P_1 */
   10407     { "vmovss",		{ XMVexScalar, VexScalar, EXdScalar }, 0 },
   10408   },
   10409   {
   10410     /* VEX_W_0F10_P_2 */
   10411     { "vmovupd",	{ XM, EXx }, 0 },
   10412   },
   10413   {
   10414     /* VEX_W_0F10_P_3 */
   10415     { "vmovsd",		{ XMVexScalar, VexScalar, EXqScalar }, 0 },
   10416   },
   10417   {
   10418     /* VEX_W_0F11_P_0 */
   10419     { "vmovups",	{ EXxS, XM }, 0 },
   10420   },
   10421   {
   10422     /* VEX_W_0F11_P_1 */
   10423     { "vmovss",		{ EXdVexScalarS, VexScalar, XMScalar }, 0 },
   10424   },
   10425   {
   10426     /* VEX_W_0F11_P_2 */
   10427     { "vmovupd",	{ EXxS, XM }, 0 },
   10428   },
   10429   {
   10430     /* VEX_W_0F11_P_3 */
   10431     { "vmovsd",		{ EXqVexScalarS, VexScalar, XMScalar }, 0 },
   10432   },
   10433   {
   10434     /* VEX_W_0F12_P_0_M_0 */
   10435     { "vmovlps",	{ XM, Vex128, EXq }, 0 },
   10436   },
   10437   {
   10438     /* VEX_W_0F12_P_0_M_1 */
   10439     { "vmovhlps",	{ XM, Vex128, EXq }, 0 },
   10440   },
   10441   {
   10442     /* VEX_W_0F12_P_1 */
   10443     { "vmovsldup",	{ XM, EXx }, 0 },
   10444   },
   10445   {
   10446     /* VEX_W_0F12_P_2 */
   10447     { "vmovlpd",	{ XM, Vex128, EXq }, 0 },
   10448   },
   10449   {
   10450     /* VEX_W_0F12_P_3 */
   10451     { "vmovddup",	{ XM, EXymmq }, 0 },
   10452   },
   10453   {
   10454     /* VEX_W_0F13_M_0 */
   10455     { "vmovlpX",	{ EXq, XM }, 0 },
   10456   },
   10457   {
   10458     /* VEX_W_0F14 */
   10459     { "vunpcklpX",	{ XM, Vex, EXx }, 0 },
   10460   },
   10461   {
   10462     /* VEX_W_0F15 */
   10463     { "vunpckhpX",	{ XM, Vex, EXx }, 0 },
   10464   },
   10465   {
   10466     /* VEX_W_0F16_P_0_M_0 */
   10467     { "vmovhps",	{ XM, Vex128, EXq }, 0 },
   10468   },
   10469   {
   10470     /* VEX_W_0F16_P_0_M_1 */
   10471     { "vmovlhps",	{ XM, Vex128, EXq }, 0 },
   10472   },
   10473   {
   10474     /* VEX_W_0F16_P_1 */
   10475     { "vmovshdup",	{ XM, EXx }, 0 },
   10476   },
   10477   {
   10478     /* VEX_W_0F16_P_2 */
   10479     { "vmovhpd",	{ XM, Vex128, EXq }, 0 },
   10480   },
   10481   {
   10482     /* VEX_W_0F17_M_0 */
   10483     { "vmovhpX",	{ EXq, XM }, 0 },
   10484   },
   10485   {
   10486     /* VEX_W_0F28 */
   10487     { "vmovapX",	{ XM, EXx }, 0 },
   10488   },
   10489   {
   10490     /* VEX_W_0F29 */
   10491     { "vmovapX",	{ EXxS, XM }, 0 },
   10492   },
   10493   {
   10494     /* VEX_W_0F2B_M_0 */
   10495     { "vmovntpX",	{ Mx, XM }, 0 },
   10496   },
   10497   {
   10498     /* VEX_W_0F2E_P_0 */
   10499     { "vucomiss",	{ XMScalar, EXdScalar }, 0 },
   10500   },
   10501   {
   10502     /* VEX_W_0F2E_P_2 */
   10503     { "vucomisd",	{ XMScalar, EXqScalar }, 0 },
   10504   },
   10505   {
   10506     /* VEX_W_0F2F_P_0 */
   10507     { "vcomiss",	{ XMScalar, EXdScalar }, 0 },
   10508   },
   10509   {
   10510     /* VEX_W_0F2F_P_2 */
   10511     { "vcomisd",	{ XMScalar, EXqScalar }, 0 },
   10512   },
   10513   {
   10514     /* VEX_W_0F41_P_0_LEN_1 */
   10515     { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1) },
   10516     { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1) },
   10517   },
   10518   {
   10519     /* VEX_W_0F41_P_2_LEN_1 */
   10520     { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1) },
   10521     { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1) }
   10522   },
   10523   {
   10524     /* VEX_W_0F42_P_0_LEN_1 */
   10525     { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1) },
   10526     { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1) },
   10527   },
   10528   {
   10529     /* VEX_W_0F42_P_2_LEN_1 */
   10530     { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1) },
   10531     { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1) },
   10532   },
   10533   {
   10534     /* VEX_W_0F44_P_0_LEN_0 */
   10535     { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1) },
   10536     { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1) },
   10537   },
   10538   {
   10539     /* VEX_W_0F44_P_2_LEN_0 */
   10540     { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1) },
   10541     { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1) },
   10542   },
   10543   {
   10544     /* VEX_W_0F45_P_0_LEN_1 */
   10545     { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1) },
   10546     { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1) },
   10547   },
   10548   {
   10549     /* VEX_W_0F45_P_2_LEN_1 */
   10550     { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1) },
   10551     { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1) },
   10552   },
   10553   {
   10554     /* VEX_W_0F46_P_0_LEN_1 */
   10555     { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1) },
   10556     { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1) },
   10557   },
   10558   {
   10559     /* VEX_W_0F46_P_2_LEN_1 */
   10560     { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1) },
   10561     { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1) },
   10562   },
   10563   {
   10564     /* VEX_W_0F47_P_0_LEN_1 */
   10565     { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1) },
   10566     { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1) },
   10567   },
   10568   {
   10569     /* VEX_W_0F47_P_2_LEN_1 */
   10570     { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1) },
   10571     { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1) },
   10572   },
   10573   {
   10574     /* VEX_W_0F4A_P_0_LEN_1 */
   10575     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1) },
   10576     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1) },
   10577   },
   10578   {
   10579     /* VEX_W_0F4A_P_2_LEN_1 */
   10580     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1) },
   10581     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1) },
   10582   },
   10583   {
   10584     /* VEX_W_0F4B_P_0_LEN_1 */
   10585     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1) },
   10586     { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1) },
   10587   },
   10588   {
   10589     /* VEX_W_0F4B_P_2_LEN_1 */
   10590     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1) },
   10591   },
   10592   {
   10593     /* VEX_W_0F50_M_0 */
   10594     { "vmovmskpX",	{ Gdq, XS }, 0 },
   10595   },
   10596   {
   10597     /* VEX_W_0F51_P_0 */
   10598     { "vsqrtps",	{ XM, EXx }, 0 },
   10599   },
   10600   {
   10601     /* VEX_W_0F51_P_1 */
   10602     { "vsqrtss",	{ XMScalar, VexScalar, EXdScalar }, 0 },
   10603   },
   10604   {
   10605     /* VEX_W_0F51_P_2  */
   10606     { "vsqrtpd",	{ XM, EXx }, 0 },
   10607   },
   10608   {
   10609     /* VEX_W_0F51_P_3 */
   10610     { "vsqrtsd",	{ XMScalar, VexScalar, EXqScalar }, 0 },
   10611   },
   10612   {
   10613     /* VEX_W_0F52_P_0 */
   10614     { "vrsqrtps",	{ XM, EXx }, 0 },
   10615   },
   10616   {
   10617     /* VEX_W_0F52_P_1 */
   10618     { "vrsqrtss",	{ XMScalar, VexScalar, EXdScalar }, 0 },
   10619   },
   10620   {
   10621     /* VEX_W_0F53_P_0  */
   10622     { "vrcpps",		{ XM, EXx }, 0 },
   10623   },
   10624   {
   10625     /* VEX_W_0F53_P_1  */
   10626     { "vrcpss",		{ XMScalar, VexScalar, EXdScalar }, 0 },
   10627   },
   10628   {
   10629     /* VEX_W_0F58_P_0  */
   10630     { "vaddps",		{ XM, Vex, EXx }, 0 },
   10631   },
   10632   {
   10633     /* VEX_W_0F58_P_1  */
   10634     { "vaddss",		{ XMScalar, VexScalar, EXdScalar }, 0 },
   10635   },
   10636   {
   10637     /* VEX_W_0F58_P_2  */
   10638     { "vaddpd",		{ XM, Vex, EXx }, 0 },
   10639   },
   10640   {
   10641     /* VEX_W_0F58_P_3  */
   10642     { "vaddsd",		{ XMScalar, VexScalar, EXqScalar }, 0 },
   10643   },
   10644   {
   10645     /* VEX_W_0F59_P_0  */
   10646     { "vmulps",		{ XM, Vex, EXx }, 0 },
   10647   },
   10648   {
   10649     /* VEX_W_0F59_P_1  */
   10650     { "vmulss",		{ XMScalar, VexScalar, EXdScalar }, 0 },
   10651   },
   10652   {
   10653     /* VEX_W_0F59_P_2  */
   10654     { "vmulpd",		{ XM, Vex, EXx }, 0 },
   10655   },
   10656   {
   10657     /* VEX_W_0F59_P_3  */
   10658     { "vmulsd",		{ XMScalar, VexScalar, EXqScalar }, 0 },
   10659   },
   10660   {
   10661     /* VEX_W_0F5A_P_0  */
   10662     { "vcvtps2pd",	{ XM, EXxmmq }, 0 },
   10663   },
   10664   {
   10665     /* VEX_W_0F5A_P_1  */
   10666     { "vcvtss2sd",	{ XMScalar, VexScalar, EXdScalar }, 0 },
   10667   },
   10668   {
   10669     /* VEX_W_0F5A_P_3  */
   10670     { "vcvtsd2ss",	{ XMScalar, VexScalar, EXqScalar }, 0 },
   10671   },
   10672   {
   10673     /* VEX_W_0F5B_P_0  */
   10674     { "vcvtdq2ps",	{ XM, EXx }, 0 },
   10675   },
   10676   {
   10677     /* VEX_W_0F5B_P_1  */
   10678     { "vcvttps2dq",	{ XM, EXx }, 0 },
   10679   },
   10680   {
   10681     /* VEX_W_0F5B_P_2  */
   10682     { "vcvtps2dq",	{ XM, EXx }, 0 },
   10683   },
   10684   {
   10685     /* VEX_W_0F5C_P_0  */
   10686     { "vsubps",		{ XM, Vex, EXx }, 0 },
   10687   },
   10688   {
   10689     /* VEX_W_0F5C_P_1  */
   10690     { "vsubss",		{ XMScalar, VexScalar, EXdScalar }, 0 },
   10691   },
   10692   {
   10693     /* VEX_W_0F5C_P_2  */
   10694     { "vsubpd",		{ XM, Vex, EXx }, 0 },
   10695   },
   10696   {
   10697     /* VEX_W_0F5C_P_3  */
   10698     { "vsubsd",		{ XMScalar, VexScalar, EXqScalar }, 0 },
   10699   },
   10700   {
   10701     /* VEX_W_0F5D_P_0  */
   10702     { "vminps",		{ XM, Vex, EXx }, 0 },
   10703   },
   10704   {
   10705     /* VEX_W_0F5D_P_1  */
   10706     { "vminss",		{ XMScalar, VexScalar, EXdScalar }, 0 },
   10707   },
   10708   {
   10709     /* VEX_W_0F5D_P_2  */
   10710     { "vminpd",		{ XM, Vex, EXx }, 0 },
   10711   },
   10712   {
   10713     /* VEX_W_0F5D_P_3  */
   10714     { "vminsd",		{ XMScalar, VexScalar, EXqScalar }, 0 },
   10715   },
   10716   {
   10717     /* VEX_W_0F5E_P_0  */
   10718     { "vdivps",		{ XM, Vex, EXx }, 0 },
   10719   },
   10720   {
   10721     /* VEX_W_0F5E_P_1  */
   10722     { "vdivss",		{ XMScalar, VexScalar, EXdScalar }, 0 },
   10723   },
   10724   {
   10725     /* VEX_W_0F5E_P_2  */
   10726     { "vdivpd",		{ XM, Vex, EXx }, 0 },
   10727   },
   10728   {
   10729     /* VEX_W_0F5E_P_3  */
   10730     { "vdivsd",		{ XMScalar, VexScalar, EXqScalar }, 0 },
   10731   },
   10732   {
   10733     /* VEX_W_0F5F_P_0  */
   10734     { "vmaxps",		{ XM, Vex, EXx }, 0 },
   10735   },
   10736   {
   10737     /* VEX_W_0F5F_P_1  */
   10738     { "vmaxss",		{ XMScalar, VexScalar, EXdScalar }, 0 },
   10739   },
   10740   {
   10741     /* VEX_W_0F5F_P_2  */
   10742     { "vmaxpd",		{ XM, Vex, EXx }, 0 },
   10743   },
   10744   {
   10745     /* VEX_W_0F5F_P_3  */
   10746     { "vmaxsd",		{ XMScalar, VexScalar, EXqScalar }, 0 },
   10747   },
   10748   {
   10749     /* VEX_W_0F60_P_2  */
   10750     { "vpunpcklbw",	{ XM, Vex, EXx }, 0 },
   10751   },
   10752   {
   10753     /* VEX_W_0F61_P_2  */
   10754     { "vpunpcklwd",	{ XM, Vex, EXx }, 0 },
   10755   },
   10756   {
   10757     /* VEX_W_0F62_P_2  */
   10758     { "vpunpckldq",	{ XM, Vex, EXx }, 0 },
   10759   },
   10760   {
   10761     /* VEX_W_0F63_P_2  */
   10762     { "vpacksswb",	{ XM, Vex, EXx }, 0 },
   10763   },
   10764   {
   10765     /* VEX_W_0F64_P_2  */
   10766     { "vpcmpgtb",	{ XM, Vex, EXx }, 0 },
   10767   },
   10768   {
   10769     /* VEX_W_0F65_P_2  */
   10770     { "vpcmpgtw",	{ XM, Vex, EXx }, 0 },
   10771   },
   10772   {
   10773     /* VEX_W_0F66_P_2  */
   10774     { "vpcmpgtd",	{ XM, Vex, EXx }, 0 },
   10775   },
   10776   {
   10777     /* VEX_W_0F67_P_2  */
   10778     { "vpackuswb",	{ XM, Vex, EXx }, 0 },
   10779   },
   10780   {
   10781     /* VEX_W_0F68_P_2  */
   10782     { "vpunpckhbw",	{ XM, Vex, EXx }, 0 },
   10783   },
   10784   {
   10785     /* VEX_W_0F69_P_2  */
   10786     { "vpunpckhwd",	{ XM, Vex, EXx }, 0 },
   10787   },
   10788   {
   10789     /* VEX_W_0F6A_P_2  */
   10790     { "vpunpckhdq",	{ XM, Vex, EXx }, 0 },
   10791   },
   10792   {
   10793     /* VEX_W_0F6B_P_2  */
   10794     { "vpackssdw",	{ XM, Vex, EXx }, 0 },
   10795   },
   10796   {
   10797     /* VEX_W_0F6C_P_2  */
   10798     { "vpunpcklqdq",	{ XM, Vex, EXx }, 0 },
   10799   },
   10800   {
   10801     /* VEX_W_0F6D_P_2  */
   10802     { "vpunpckhqdq",	{ XM, Vex, EXx }, 0 },
   10803   },
   10804   {
   10805     /* VEX_W_0F6F_P_1  */
   10806     { "vmovdqu",	{ XM, EXx }, 0 },
   10807   },
   10808   {
   10809     /* VEX_W_0F6F_P_2  */
   10810     { "vmovdqa",	{ XM, EXx }, 0 },
   10811   },
   10812   {
   10813     /* VEX_W_0F70_P_1 */
   10814     { "vpshufhw",	{ XM, EXx, Ib }, 0 },
   10815   },
   10816   {
   10817     /* VEX_W_0F70_P_2 */
   10818     { "vpshufd",	{ XM, EXx, Ib }, 0 },
   10819   },
   10820   {
   10821     /* VEX_W_0F70_P_3 */
   10822     { "vpshuflw",	{ XM, EXx, Ib }, 0 },
   10823   },
   10824   {
   10825     /* VEX_W_0F71_R_2_P_2  */
   10826     { "vpsrlw",		{ Vex, XS, Ib }, 0 },
   10827   },
   10828   {
   10829     /* VEX_W_0F71_R_4_P_2  */
   10830     { "vpsraw",		{ Vex, XS, Ib }, 0 },
   10831   },
   10832   {
   10833     /* VEX_W_0F71_R_6_P_2  */
   10834     { "vpsllw",		{ Vex, XS, Ib }, 0 },
   10835   },
   10836   {
   10837     /* VEX_W_0F72_R_2_P_2  */
   10838     { "vpsrld",		{ Vex, XS, Ib }, 0 },
   10839   },
   10840   {
   10841     /* VEX_W_0F72_R_4_P_2  */
   10842     { "vpsrad",		{ Vex, XS, Ib }, 0 },
   10843   },
   10844   {
   10845     /* VEX_W_0F72_R_6_P_2  */
   10846     { "vpslld",		{ Vex, XS, Ib }, 0 },
   10847   },
   10848   {
   10849     /* VEX_W_0F73_R_2_P_2  */
   10850     { "vpsrlq",		{ Vex, XS, Ib }, 0 },
   10851   },
   10852   {
   10853     /* VEX_W_0F73_R_3_P_2  */
   10854     { "vpsrldq",	{ Vex, XS, Ib }, 0 },
   10855   },
   10856   {
   10857     /* VEX_W_0F73_R_6_P_2  */
   10858     { "vpsllq",		{ Vex, XS, Ib }, 0 },
   10859   },
   10860   {
   10861     /* VEX_W_0F73_R_7_P_2  */
   10862     { "vpslldq",	{ Vex, XS, Ib }, 0 },
   10863   },
   10864   {
   10865     /* VEX_W_0F74_P_2 */
   10866     { "vpcmpeqb",	{ XM, Vex, EXx }, 0 },
   10867   },
   10868   {
   10869     /* VEX_W_0F75_P_2 */
   10870     { "vpcmpeqw",	{ XM, Vex, EXx }, 0 },
   10871   },
   10872   {
   10873     /* VEX_W_0F76_P_2 */
   10874     { "vpcmpeqd",	{ XM, Vex, EXx }, 0 },
   10875   },
   10876   {
   10877     /* VEX_W_0F77_P_0 */
   10878     { "",		{ VZERO }, 0 },
   10879   },
   10880   {
   10881     /* VEX_W_0F7C_P_2 */
   10882     { "vhaddpd",	{ XM, Vex, EXx }, 0 },
   10883   },
   10884   {
   10885     /* VEX_W_0F7C_P_3 */
   10886     { "vhaddps",	{ XM, Vex, EXx }, 0 },
   10887   },
   10888   {
   10889     /* VEX_W_0F7D_P_2 */
   10890     { "vhsubpd",	{ XM, Vex, EXx }, 0 },
   10891   },
   10892   {
   10893     /* VEX_W_0F7D_P_3 */
   10894     { "vhsubps",	{ XM, Vex, EXx }, 0 },
   10895   },
   10896   {
   10897     /* VEX_W_0F7E_P_1 */
   10898     { "vmovq",		{ XMScalar, EXqScalar }, 0 },
   10899   },
   10900   {
   10901     /* VEX_W_0F7F_P_1 */
   10902     { "vmovdqu",	{ EXxS, XM }, 0 },
   10903   },
   10904   {
   10905     /* VEX_W_0F7F_P_2 */
   10906     { "vmovdqa",	{ EXxS, XM }, 0 },
   10907   },
   10908   {
   10909     /* VEX_W_0F90_P_0_LEN_0 */
   10910     { "kmovw",		{ MaskG, MaskE }, 0 },
   10911     { "kmovq",		{ MaskG, MaskE }, 0 },
   10912   },
   10913   {
   10914     /* VEX_W_0F90_P_2_LEN_0 */
   10915     { "kmovb",		{ MaskG, MaskBDE }, 0 },
   10916     { "kmovd",		{ MaskG, MaskBDE }, 0 },
   10917   },
   10918   {
   10919     /* VEX_W_0F91_P_0_LEN_0 */
   10920     { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) },
   10921     { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) },
   10922   },
   10923   {
   10924     /* VEX_W_0F91_P_2_LEN_0 */
   10925     { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) },
   10926     { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) },
   10927   },
   10928   {
   10929     /* VEX_W_0F92_P_0_LEN_0 */
   10930     { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) },
   10931   },
   10932   {
   10933     /* VEX_W_0F92_P_2_LEN_0 */
   10934     { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) },
   10935   },
   10936   {
   10937     /* VEX_W_0F92_P_3_LEN_0 */
   10938     { MOD_TABLE (MOD_VEX_W_0_0F92_P_3_LEN_0) },
   10939     { MOD_TABLE (MOD_VEX_W_1_0F92_P_3_LEN_0) },
   10940   },
   10941   {
   10942     /* VEX_W_0F93_P_0_LEN_0 */
   10943     { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) },
   10944   },
   10945   {
   10946     /* VEX_W_0F93_P_2_LEN_0 */
   10947     { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) },
   10948   },
   10949   {
   10950     /* VEX_W_0F93_P_3_LEN_0 */
   10951     { MOD_TABLE (MOD_VEX_W_0_0F93_P_3_LEN_0) },
   10952     { MOD_TABLE (MOD_VEX_W_1_0F93_P_3_LEN_0) },
   10953   },
   10954   {
   10955     /* VEX_W_0F98_P_0_LEN_0 */
   10956     { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) },
   10957     { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) },
   10958   },
   10959   {
   10960     /* VEX_W_0F98_P_2_LEN_0 */
   10961     { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) },
   10962     { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) },
   10963   },
   10964   {
   10965     /* VEX_W_0F99_P_0_LEN_0 */
   10966     { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) },
   10967     { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) },
   10968   },
   10969   {
   10970     /* VEX_W_0F99_P_2_LEN_0 */
   10971     { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) },
   10972     { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) },
   10973   },
   10974   {
   10975     /* VEX_W_0FAE_R_2_M_0 */
   10976     { "vldmxcsr",	{ Md }, 0 },
   10977   },
   10978   {
   10979     /* VEX_W_0FAE_R_3_M_0 */
   10980     { "vstmxcsr",	{ Md }, 0 },
   10981   },
   10982   {
   10983     /* VEX_W_0FC2_P_0 */
   10984     { "vcmpps",		{ XM, Vex, EXx, VCMP }, 0 },
   10985   },
   10986   {
   10987     /* VEX_W_0FC2_P_1 */
   10988     { "vcmpss",		{ XMScalar, VexScalar, EXdScalar, VCMP }, 0 },
   10989   },
   10990   {
   10991     /* VEX_W_0FC2_P_2 */
   10992     { "vcmppd",		{ XM, Vex, EXx, VCMP }, 0 },
   10993   },
   10994   {
   10995     /* VEX_W_0FC2_P_3 */
   10996     { "vcmpsd",		{ XMScalar, VexScalar, EXqScalar, VCMP }, 0 },
   10997   },
   10998   {
   10999     /* VEX_W_0FC4_P_2 */
   11000     { "vpinsrw",	{ XM, Vex128, Edqw, Ib }, 0 },
   11001   },
   11002   {
   11003     /* VEX_W_0FC5_P_2 */
   11004     { "vpextrw",	{ Gdq, XS, Ib }, 0 },
   11005   },
   11006   {
   11007     /* VEX_W_0FD0_P_2 */
   11008     { "vaddsubpd",	{ XM, Vex, EXx }, 0 },
   11009   },
   11010   {
   11011     /* VEX_W_0FD0_P_3 */
   11012     { "vaddsubps",	{ XM, Vex, EXx }, 0 },
   11013   },
   11014   {
   11015     /* VEX_W_0FD1_P_2 */
   11016     { "vpsrlw",		{ XM, Vex, EXxmm }, 0 },
   11017   },
   11018   {
   11019     /* VEX_W_0FD2_P_2 */
   11020     { "vpsrld",		{ XM, Vex, EXxmm }, 0 },
   11021   },
   11022   {
   11023     /* VEX_W_0FD3_P_2 */
   11024     { "vpsrlq",		{ XM, Vex, EXxmm }, 0 },
   11025   },
   11026   {
   11027     /* VEX_W_0FD4_P_2 */
   11028     { "vpaddq",		{ XM, Vex, EXx }, 0 },
   11029   },
   11030   {
   11031     /* VEX_W_0FD5_P_2 */
   11032     { "vpmullw",	{ XM, Vex, EXx }, 0 },
   11033   },
   11034   {
   11035     /* VEX_W_0FD6_P_2 */
   11036     { "vmovq",		{ EXqScalarS, XMScalar }, 0 },
   11037   },
   11038   {
   11039     /* VEX_W_0FD7_P_2_M_1 */
   11040     { "vpmovmskb",	{ Gdq, XS }, 0 },
   11041   },
   11042   {
   11043     /* VEX_W_0FD8_P_2 */
   11044     { "vpsubusb",	{ XM, Vex, EXx }, 0 },
   11045   },
   11046   {
   11047     /* VEX_W_0FD9_P_2 */
   11048     { "vpsubusw",	{ XM, Vex, EXx }, 0 },
   11049   },
   11050   {
   11051     /* VEX_W_0FDA_P_2 */
   11052     { "vpminub",	{ XM, Vex, EXx }, 0 },
   11053   },
   11054   {
   11055     /* VEX_W_0FDB_P_2 */
   11056     { "vpand",		{ XM, Vex, EXx }, 0 },
   11057   },
   11058   {
   11059     /* VEX_W_0FDC_P_2 */
   11060     { "vpaddusb",	{ XM, Vex, EXx }, 0 },
   11061   },
   11062   {
   11063     /* VEX_W_0FDD_P_2 */
   11064     { "vpaddusw",	{ XM, Vex, EXx }, 0 },
   11065   },
   11066   {
   11067     /* VEX_W_0FDE_P_2 */
   11068     { "vpmaxub",	{ XM, Vex, EXx }, 0 },
   11069   },
   11070   {
   11071     /* VEX_W_0FDF_P_2 */
   11072     { "vpandn",		{ XM, Vex, EXx }, 0 },
   11073   },
   11074   {
   11075     /* VEX_W_0FE0_P_2  */
   11076     { "vpavgb",		{ XM, Vex, EXx }, 0 },
   11077   },
   11078   {
   11079     /* VEX_W_0FE1_P_2  */
   11080     { "vpsraw",		{ XM, Vex, EXxmm }, 0 },
   11081   },
   11082   {
   11083     /* VEX_W_0FE2_P_2  */
   11084     { "vpsrad",		{ XM, Vex, EXxmm }, 0 },
   11085   },
   11086   {
   11087     /* VEX_W_0FE3_P_2  */
   11088     { "vpavgw",		{ XM, Vex, EXx }, 0 },
   11089   },
   11090   {
   11091     /* VEX_W_0FE4_P_2  */
   11092     { "vpmulhuw",	{ XM, Vex, EXx }, 0 },
   11093   },
   11094   {
   11095     /* VEX_W_0FE5_P_2  */
   11096     { "vpmulhw",	{ XM, Vex, EXx }, 0 },
   11097   },
   11098   {
   11099     /* VEX_W_0FE6_P_1  */
   11100     { "vcvtdq2pd",	{ XM, EXxmmq }, 0 },
   11101   },
   11102   {
   11103     /* VEX_W_0FE6_P_2  */
   11104     { "vcvttpd2dq%XY",	{ XMM, EXx }, 0 },
   11105   },
   11106   {
   11107     /* VEX_W_0FE6_P_3  */
   11108     { "vcvtpd2dq%XY",	{ XMM, EXx }, 0 },
   11109   },
   11110   {
   11111     /* VEX_W_0FE7_P_2_M_0 */
   11112     { "vmovntdq",	{ Mx, XM }, 0 },
   11113   },
   11114   {
   11115     /* VEX_W_0FE8_P_2  */
   11116     { "vpsubsb",	{ XM, Vex, EXx }, 0 },
   11117   },
   11118   {
   11119     /* VEX_W_0FE9_P_2  */
   11120     { "vpsubsw",	{ XM, Vex, EXx }, 0 },
   11121   },
   11122   {
   11123     /* VEX_W_0FEA_P_2  */
   11124     { "vpminsw",	{ XM, Vex, EXx }, 0 },
   11125   },
   11126   {
   11127     /* VEX_W_0FEB_P_2  */
   11128     { "vpor",		{ XM, Vex, EXx }, 0 },
   11129   },
   11130   {
   11131     /* VEX_W_0FEC_P_2  */
   11132     { "vpaddsb",	{ XM, Vex, EXx }, 0 },
   11133   },
   11134   {
   11135     /* VEX_W_0FED_P_2  */
   11136     { "vpaddsw",	{ XM, Vex, EXx }, 0 },
   11137   },
   11138   {
   11139     /* VEX_W_0FEE_P_2  */
   11140     { "vpmaxsw",	{ XM, Vex, EXx }, 0 },
   11141   },
   11142   {
   11143     /* VEX_W_0FEF_P_2  */
   11144     { "vpxor",		{ XM, Vex, EXx }, 0 },
   11145   },
   11146   {
   11147     /* VEX_W_0FF0_P_3_M_0 */
   11148     { "vlddqu",		{ XM, M }, 0 },
   11149   },
   11150   {
   11151     /* VEX_W_0FF1_P_2 */
   11152     { "vpsllw",		{ XM, Vex, EXxmm }, 0 },
   11153   },
   11154   {
   11155     /* VEX_W_0FF2_P_2 */
   11156     { "vpslld",		{ XM, Vex, EXxmm }, 0 },
   11157   },
   11158   {
   11159     /* VEX_W_0FF3_P_2 */
   11160     { "vpsllq",		{ XM, Vex, EXxmm }, 0 },
   11161   },
   11162   {
   11163     /* VEX_W_0FF4_P_2 */
   11164     { "vpmuludq",	{ XM, Vex, EXx }, 0 },
   11165   },
   11166   {
   11167     /* VEX_W_0FF5_P_2 */
   11168     { "vpmaddwd",	{ XM, Vex, EXx }, 0 },
   11169   },
   11170   {
   11171     /* VEX_W_0FF6_P_2 */
   11172     { "vpsadbw",	{ XM, Vex, EXx }, 0 },
   11173   },
   11174   {
   11175     /* VEX_W_0FF7_P_2 */
   11176     { "vmaskmovdqu",	{ XM, XS }, 0 },
   11177   },
   11178   {
   11179     /* VEX_W_0FF8_P_2 */
   11180     { "vpsubb",		{ XM, Vex, EXx }, 0 },
   11181   },
   11182   {
   11183     /* VEX_W_0FF9_P_2 */
   11184     { "vpsubw",		{ XM, Vex, EXx }, 0 },
   11185   },
   11186   {
   11187     /* VEX_W_0FFA_P_2 */
   11188     { "vpsubd",		{ XM, Vex, EXx }, 0 },
   11189   },
   11190   {
   11191     /* VEX_W_0FFB_P_2 */
   11192     { "vpsubq",		{ XM, Vex, EXx }, 0 },
   11193   },
   11194   {
   11195     /* VEX_W_0FFC_P_2 */
   11196     { "vpaddb",		{ XM, Vex, EXx }, 0 },
   11197   },
   11198   {
   11199     /* VEX_W_0FFD_P_2 */
   11200     { "vpaddw",		{ XM, Vex, EXx }, 0 },
   11201   },
   11202   {
   11203     /* VEX_W_0FFE_P_2 */
   11204     { "vpaddd",		{ XM, Vex, EXx }, 0 },
   11205   },
   11206   {
   11207     /* VEX_W_0F3800_P_2  */
   11208     { "vpshufb",	{ XM, Vex, EXx }, 0 },
   11209   },
   11210   {
   11211     /* VEX_W_0F3801_P_2  */
   11212     { "vphaddw",	{ XM, Vex, EXx }, 0 },
   11213   },
   11214   {
   11215     /* VEX_W_0F3802_P_2  */
   11216     { "vphaddd",	{ XM, Vex, EXx }, 0 },
   11217   },
   11218   {
   11219     /* VEX_W_0F3803_P_2  */
   11220     { "vphaddsw",	{ XM, Vex, EXx }, 0 },
   11221   },
   11222   {
   11223     /* VEX_W_0F3804_P_2  */
   11224     { "vpmaddubsw",	{ XM, Vex, EXx }, 0 },
   11225   },
   11226   {
   11227     /* VEX_W_0F3805_P_2  */
   11228     { "vphsubw",	{ XM, Vex, EXx }, 0 },
   11229   },
   11230   {
   11231     /* VEX_W_0F3806_P_2  */
   11232     { "vphsubd",	{ XM, Vex, EXx }, 0 },
   11233   },
   11234   {
   11235     /* VEX_W_0F3807_P_2  */
   11236     { "vphsubsw",	{ XM, Vex, EXx }, 0 },
   11237   },
   11238   {
   11239     /* VEX_W_0F3808_P_2  */
   11240     { "vpsignb",	{ XM, Vex, EXx }, 0 },
   11241   },
   11242   {
   11243     /* VEX_W_0F3809_P_2  */
   11244     { "vpsignw",	{ XM, Vex, EXx }, 0 },
   11245   },
   11246   {
   11247     /* VEX_W_0F380A_P_2  */
   11248     { "vpsignd",	{ XM, Vex, EXx }, 0 },
   11249   },
   11250   {
   11251     /* VEX_W_0F380B_P_2  */
   11252     { "vpmulhrsw",	{ XM, Vex, EXx }, 0 },
   11253   },
   11254   {
   11255     /* VEX_W_0F380C_P_2  */
   11256     { "vpermilps",	{ XM, Vex, EXx }, 0 },
   11257   },
   11258   {
   11259     /* VEX_W_0F380D_P_2  */
   11260     { "vpermilpd",	{ XM, Vex, EXx }, 0 },
   11261   },
   11262   {
   11263     /* VEX_W_0F380E_P_2  */
   11264     { "vtestps",	{ XM, EXx }, 0 },
   11265   },
   11266   {
   11267     /* VEX_W_0F380F_P_2  */
   11268     { "vtestpd",	{ XM, EXx }, 0 },
   11269   },
   11270   {
   11271     /* VEX_W_0F3816_P_2  */
   11272     { "vpermps",	{ XM, Vex, EXx }, 0 },
   11273   },
   11274   {
   11275     /* VEX_W_0F3817_P_2 */
   11276     { "vptest",		{ XM, EXx }, 0 },
   11277   },
   11278   {
   11279     /* VEX_W_0F3818_P_2 */
   11280     { "vbroadcastss",	{ XM, EXxmm_md }, 0 },
   11281   },
   11282   {
   11283     /* VEX_W_0F3819_P_2 */
   11284     { "vbroadcastsd",	{ XM, EXxmm_mq }, 0 },
   11285   },
   11286   {
   11287     /* VEX_W_0F381A_P_2_M_0 */
   11288     { "vbroadcastf128",	{ XM, Mxmm }, 0 },
   11289   },
   11290   {
   11291     /* VEX_W_0F381C_P_2 */
   11292     { "vpabsb",		{ XM, EXx }, 0 },
   11293   },
   11294   {
   11295     /* VEX_W_0F381D_P_2 */
   11296     { "vpabsw",		{ XM, EXx }, 0 },
   11297   },
   11298   {
   11299     /* VEX_W_0F381E_P_2 */
   11300     { "vpabsd",		{ XM, EXx }, 0 },
   11301   },
   11302   {
   11303     /* VEX_W_0F3820_P_2 */
   11304     { "vpmovsxbw",	{ XM, EXxmmq }, 0 },
   11305   },
   11306   {
   11307     /* VEX_W_0F3821_P_2 */
   11308     { "vpmovsxbd",	{ XM, EXxmmqd }, 0 },
   11309   },
   11310   {
   11311     /* VEX_W_0F3822_P_2 */
   11312     { "vpmovsxbq",	{ XM, EXxmmdw }, 0 },
   11313   },
   11314   {
   11315     /* VEX_W_0F3823_P_2 */
   11316     { "vpmovsxwd",	{ XM, EXxmmq }, 0 },
   11317   },
   11318   {
   11319     /* VEX_W_0F3824_P_2 */
   11320     { "vpmovsxwq",	{ XM, EXxmmqd }, 0 },
   11321   },
   11322   {
   11323     /* VEX_W_0F3825_P_2 */
   11324     { "vpmovsxdq",	{ XM, EXxmmq }, 0 },
   11325   },
   11326   {
   11327     /* VEX_W_0F3828_P_2 */
   11328     { "vpmuldq",	{ XM, Vex, EXx }, 0 },
   11329   },
   11330   {
   11331     /* VEX_W_0F3829_P_2 */
   11332     { "vpcmpeqq",	{ XM, Vex, EXx }, 0 },
   11333   },
   11334   {
   11335     /* VEX_W_0F382A_P_2_M_0 */
   11336     { "vmovntdqa",	{ XM, Mx }, 0 },
   11337   },
   11338   {
   11339     /* VEX_W_0F382B_P_2 */
   11340     { "vpackusdw",	{ XM, Vex, EXx }, 0 },
   11341   },
   11342   {
   11343     /* VEX_W_0F382C_P_2_M_0 */
   11344     { "vmaskmovps",	{ XM, Vex, Mx }, 0 },
   11345   },
   11346   {
   11347     /* VEX_W_0F382D_P_2_M_0 */
   11348     { "vmaskmovpd",	{ XM, Vex, Mx }, 0 },
   11349   },
   11350   {
   11351     /* VEX_W_0F382E_P_2_M_0 */
   11352     { "vmaskmovps",	{ Mx, Vex, XM }, 0 },
   11353   },
   11354   {
   11355     /* VEX_W_0F382F_P_2_M_0 */
   11356     { "vmaskmovpd",	{ Mx, Vex, XM }, 0 },
   11357   },
   11358   {
   11359     /* VEX_W_0F3830_P_2 */
   11360     { "vpmovzxbw",	{ XM, EXxmmq }, 0 },
   11361   },
   11362   {
   11363     /* VEX_W_0F3831_P_2 */
   11364     { "vpmovzxbd",	{ XM, EXxmmqd }, 0 },
   11365   },
   11366   {
   11367     /* VEX_W_0F3832_P_2 */
   11368     { "vpmovzxbq",	{ XM, EXxmmdw }, 0 },
   11369   },
   11370   {
   11371     /* VEX_W_0F3833_P_2 */
   11372     { "vpmovzxwd",	{ XM, EXxmmq }, 0 },
   11373   },
   11374   {
   11375     /* VEX_W_0F3834_P_2 */
   11376     { "vpmovzxwq",	{ XM, EXxmmqd }, 0 },
   11377   },
   11378   {
   11379     /* VEX_W_0F3835_P_2 */
   11380     { "vpmovzxdq",	{ XM, EXxmmq }, 0 },
   11381   },
   11382   {
   11383     /* VEX_W_0F3836_P_2  */
   11384     { "vpermd",		{ XM, Vex, EXx }, 0 },
   11385   },
   11386   {
   11387     /* VEX_W_0F3837_P_2 */
   11388     { "vpcmpgtq",	{ XM, Vex, EXx }, 0 },
   11389   },
   11390   {
   11391     /* VEX_W_0F3838_P_2 */
   11392     { "vpminsb",	{ XM, Vex, EXx }, 0 },
   11393   },
   11394   {
   11395     /* VEX_W_0F3839_P_2 */
   11396     { "vpminsd",	{ XM, Vex, EXx }, 0 },
   11397   },
   11398   {
   11399     /* VEX_W_0F383A_P_2 */
   11400     { "vpminuw",	{ XM, Vex, EXx }, 0 },
   11401   },
   11402   {
   11403     /* VEX_W_0F383B_P_2 */
   11404     { "vpminud",	{ XM, Vex, EXx }, 0 },
   11405   },
   11406   {
   11407     /* VEX_W_0F383C_P_2 */
   11408     { "vpmaxsb",	{ XM, Vex, EXx }, 0 },
   11409   },
   11410   {
   11411     /* VEX_W_0F383D_P_2 */
   11412     { "vpmaxsd",	{ XM, Vex, EXx }, 0 },
   11413   },
   11414   {
   11415     /* VEX_W_0F383E_P_2 */
   11416     { "vpmaxuw",	{ XM, Vex, EXx }, 0 },
   11417   },
   11418   {
   11419     /* VEX_W_0F383F_P_2 */
   11420     { "vpmaxud",	{ XM, Vex, EXx }, 0 },
   11421   },
   11422   {
   11423     /* VEX_W_0F3840_P_2 */
   11424     { "vpmulld",	{ XM, Vex, EXx }, 0 },
   11425   },
   11426   {
   11427     /* VEX_W_0F3841_P_2 */
   11428     { "vphminposuw",	{ XM, EXx }, 0 },
   11429   },
   11430   {
   11431     /* VEX_W_0F3846_P_2 */
   11432     { "vpsravd",	{ XM, Vex, EXx }, 0 },
   11433   },
   11434   {
   11435     /* VEX_W_0F3858_P_2 */
   11436     { "vpbroadcastd", { XM, EXxmm_md }, 0 },
   11437   },
   11438   {
   11439     /* VEX_W_0F3859_P_2 */
   11440     { "vpbroadcastq",	{ XM, EXxmm_mq }, 0 },
   11441   },
   11442   {
   11443     /* VEX_W_0F385A_P_2_M_0 */
   11444     { "vbroadcasti128", { XM, Mxmm }, 0 },
   11445   },
   11446   {
   11447     /* VEX_W_0F3878_P_2 */
   11448     { "vpbroadcastb",	{ XM, EXxmm_mb }, 0 },
   11449   },
   11450   {
   11451     /* VEX_W_0F3879_P_2 */
   11452     { "vpbroadcastw",	{ XM, EXxmm_mw }, 0 },
   11453   },
   11454   {
   11455     /* VEX_W_0F38DB_P_2 */
   11456     { "vaesimc",	{ XM, EXx }, 0 },
   11457   },
   11458   {
   11459     /* VEX_W_0F38DC_P_2 */
   11460     { "vaesenc",	{ XM, Vex128, EXx }, 0 },
   11461   },
   11462   {
   11463     /* VEX_W_0F38DD_P_2 */
   11464     { "vaesenclast",	{ XM, Vex128, EXx }, 0 },
   11465   },
   11466   {
   11467     /* VEX_W_0F38DE_P_2 */
   11468     { "vaesdec",	{ XM, Vex128, EXx }, 0 },
   11469   },
   11470   {
   11471     /* VEX_W_0F38DF_P_2 */
   11472     { "vaesdeclast",	{ XM, Vex128, EXx }, 0 },
   11473   },
   11474   {
   11475     /* VEX_W_0F3A00_P_2 */
   11476     { Bad_Opcode },
   11477     { "vpermq",		{ XM, EXx, Ib }, 0 },
   11478   },
   11479   {
   11480     /* VEX_W_0F3A01_P_2 */
   11481     { Bad_Opcode },
   11482     { "vpermpd",	{ XM, EXx, Ib }, 0 },
   11483   },
   11484   {
   11485     /* VEX_W_0F3A02_P_2 */
   11486     { "vpblendd",	{ XM, Vex, EXx, Ib }, 0 },
   11487   },
   11488   {
   11489     /* VEX_W_0F3A04_P_2 */
   11490     { "vpermilps",	{ XM, EXx, Ib }, 0 },
   11491   },
   11492   {
   11493     /* VEX_W_0F3A05_P_2 */
   11494     { "vpermilpd",	{ XM, EXx, Ib }, 0 },
   11495   },
   11496   {
   11497     /* VEX_W_0F3A06_P_2 */
   11498     { "vperm2f128",	{ XM, Vex256, EXx, Ib }, 0 },
   11499   },
   11500   {
   11501     /* VEX_W_0F3A08_P_2 */
   11502     { "vroundps",	{ XM, EXx, Ib }, 0 },
   11503   },
   11504   {
   11505     /* VEX_W_0F3A09_P_2 */
   11506     { "vroundpd",	{ XM, EXx, Ib }, 0 },
   11507   },
   11508   {
   11509     /* VEX_W_0F3A0A_P_2 */
   11510     { "vroundss",	{ XMScalar, VexScalar, EXdScalar, Ib }, 0 },
   11511   },
   11512   {
   11513     /* VEX_W_0F3A0B_P_2 */
   11514     { "vroundsd",	{ XMScalar, VexScalar, EXqScalar, Ib }, 0 },
   11515   },
   11516   {
   11517     /* VEX_W_0F3A0C_P_2 */
   11518     { "vblendps",	{ XM, Vex, EXx, Ib }, 0 },
   11519   },
   11520   {
   11521     /* VEX_W_0F3A0D_P_2 */
   11522     { "vblendpd",	{ XM, Vex, EXx, Ib }, 0 },
   11523   },
   11524   {
   11525     /* VEX_W_0F3A0E_P_2 */
   11526     { "vpblendw",	{ XM, Vex, EXx, Ib }, 0 },
   11527   },
   11528   {
   11529     /* VEX_W_0F3A0F_P_2 */
   11530     { "vpalignr",	{ XM, Vex, EXx, Ib }, 0 },
   11531   },
   11532   {
   11533     /* VEX_W_0F3A14_P_2 */
   11534     { "vpextrb",	{ Edqb, XM, Ib }, 0 },
   11535   },
   11536   {
   11537     /* VEX_W_0F3A15_P_2 */
   11538     { "vpextrw",	{ Edqw, XM, Ib }, 0 },
   11539   },
   11540   {
   11541     /* VEX_W_0F3A18_P_2 */
   11542     { "vinsertf128",	{ XM, Vex256, EXxmm, Ib }, 0 },
   11543   },
   11544   {
   11545     /* VEX_W_0F3A19_P_2 */
   11546     { "vextractf128",	{ EXxmm, XM, Ib }, 0 },
   11547   },
   11548   {
   11549     /* VEX_W_0F3A20_P_2 */
   11550     { "vpinsrb",	{ XM, Vex128, Edqb, Ib }, 0 },
   11551   },
   11552   {
   11553     /* VEX_W_0F3A21_P_2 */
   11554     { "vinsertps",	{ XM, Vex128, EXd, Ib }, 0 },
   11555   },
   11556   {
   11557     /* VEX_W_0F3A30_P_2_LEN_0 */
   11558     { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0) },
   11559     { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0) },
   11560   },
   11561   {
   11562     /* VEX_W_0F3A31_P_2_LEN_0 */
   11563     { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0) },
   11564     { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0) },
   11565   },
   11566   {
   11567     /* VEX_W_0F3A32_P_2_LEN_0 */
   11568     { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0) },
   11569     { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0) },
   11570   },
   11571   {
   11572     /* VEX_W_0F3A33_P_2_LEN_0 */
   11573     { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0) },
   11574     { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0) },
   11575   },
   11576   {
   11577     /* VEX_W_0F3A38_P_2 */
   11578     { "vinserti128",	{ XM, Vex256, EXxmm, Ib }, 0 },
   11579   },
   11580   {
   11581     /* VEX_W_0F3A39_P_2 */
   11582     { "vextracti128",	{ EXxmm, XM, Ib }, 0 },
   11583   },
   11584   {
   11585     /* VEX_W_0F3A40_P_2 */
   11586     { "vdpps",		{ XM, Vex, EXx, Ib }, 0 },
   11587   },
   11588   {
   11589     /* VEX_W_0F3A41_P_2 */
   11590     { "vdppd",		{ XM, Vex128, EXx, Ib }, 0 },
   11591   },
   11592   {
   11593     /* VEX_W_0F3A42_P_2 */
   11594     { "vmpsadbw",	{ XM, Vex, EXx, Ib }, 0 },
   11595   },
   11596   {
   11597     /* VEX_W_0F3A44_P_2 */
   11598     { "vpclmulqdq",	{ XM, Vex128, EXx, PCLMUL }, 0 },
   11599   },
   11600   {
   11601     /* VEX_W_0F3A46_P_2 */
   11602     { "vperm2i128",	{ XM, Vex256, EXx, Ib }, 0 },
   11603   },
   11604   {
   11605     /* VEX_W_0F3A48_P_2 */
   11606     { "vpermil2ps",	{ XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
   11607     { "vpermil2ps",	{ XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
   11608   },
   11609   {
   11610     /* VEX_W_0F3A49_P_2 */
   11611     { "vpermil2pd",	{ XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
   11612     { "vpermil2pd",	{ XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
   11613   },
   11614   {
   11615     /* VEX_W_0F3A4A_P_2 */
   11616     { "vblendvps",	{ XM, Vex, EXx, XMVexI4 }, 0 },
   11617   },
   11618   {
   11619     /* VEX_W_0F3A4B_P_2 */
   11620     { "vblendvpd",	{ XM, Vex, EXx, XMVexI4 }, 0 },
   11621   },
   11622   {
   11623     /* VEX_W_0F3A4C_P_2 */
   11624     { "vpblendvb",	{ XM, Vex, EXx, XMVexI4 }, 0 },
   11625   },
   11626   {
   11627     /* VEX_W_0F3A60_P_2 */
   11628     { "vpcmpestrm",	{ XM, EXx, Ib }, 0 },
   11629   },
   11630   {
   11631     /* VEX_W_0F3A61_P_2 */
   11632     { "vpcmpestri",	{ XM, EXx, Ib }, 0 },
   11633   },
   11634   {
   11635     /* VEX_W_0F3A62_P_2 */
   11636     { "vpcmpistrm",	{ XM, EXx, Ib }, 0 },
   11637   },
   11638   {
   11639     /* VEX_W_0F3A63_P_2 */
   11640     { "vpcmpistri",	{ XM, EXx, Ib }, 0 },
   11641   },
   11642   {
   11643     /* VEX_W_0F3ADF_P_2 */
   11644     { "vaeskeygenassist", { XM, EXx, Ib }, 0 },
   11645   },
   11646 #define NEED_VEX_W_TABLE
   11647 #include "i386-dis-evex.h"
   11648 #undef NEED_VEX_W_TABLE
   11649 };
   11650 
   11651 static const struct dis386 mod_table[][2] = {
   11652   {
   11653     /* MOD_8D */
   11654     { "leaS",		{ Gv, M }, 0 },
   11655   },
   11656   {
   11657     /* MOD_C6_REG_7 */
   11658     { Bad_Opcode },
   11659     { RM_TABLE (RM_C6_REG_7) },
   11660   },
   11661   {
   11662     /* MOD_C7_REG_7 */
   11663     { Bad_Opcode },
   11664     { RM_TABLE (RM_C7_REG_7) },
   11665   },
   11666   {
   11667     /* MOD_FF_REG_3 */
   11668     { "Jcall^", { indirEp }, 0 },
   11669   },
   11670   {
   11671     /* MOD_FF_REG_5 */
   11672     { "Jjmp^", { indirEp }, 0 },
   11673   },
   11674   {
   11675     /* MOD_0F01_REG_0 */
   11676     { X86_64_TABLE (X86_64_0F01_REG_0) },
   11677     { RM_TABLE (RM_0F01_REG_0) },
   11678   },
   11679   {
   11680     /* MOD_0F01_REG_1 */
   11681     { X86_64_TABLE (X86_64_0F01_REG_1) },
   11682     { RM_TABLE (RM_0F01_REG_1) },
   11683   },
   11684   {
   11685     /* MOD_0F01_REG_2 */
   11686     { X86_64_TABLE (X86_64_0F01_REG_2) },
   11687     { RM_TABLE (RM_0F01_REG_2) },
   11688   },
   11689   {
   11690     /* MOD_0F01_REG_3 */
   11691     { X86_64_TABLE (X86_64_0F01_REG_3) },
   11692     { RM_TABLE (RM_0F01_REG_3) },
   11693   },
   11694   {
   11695     /* MOD_0F01_REG_5 */
   11696     { Bad_Opcode },
   11697     { RM_TABLE (RM_0F01_REG_5) },
   11698   },
   11699   {
   11700     /* MOD_0F01_REG_7 */
   11701     { "invlpg",		{ Mb }, 0 },
   11702     { RM_TABLE (RM_0F01_REG_7) },
   11703   },
   11704   {
   11705     /* MOD_0F12_PREFIX_0 */
   11706     { "movlps",		{ XM, EXq }, PREFIX_OPCODE },
   11707     { "movhlps",	{ XM, EXq }, PREFIX_OPCODE },
   11708   },
   11709   {
   11710     /* MOD_0F13 */
   11711     { "movlpX",		{ EXq, XM }, PREFIX_OPCODE },
   11712   },
   11713   {
   11714     /* MOD_0F16_PREFIX_0 */
   11715     { "movhps",		{ XM, EXq }, 0 },
   11716     { "movlhps",	{ XM, EXq }, 0 },
   11717   },
   11718   {
   11719     /* MOD_0F17 */
   11720     { "movhpX",		{ EXq, XM }, PREFIX_OPCODE },
   11721   },
   11722   {
   11723     /* MOD_0F18_REG_0 */
   11724     { "prefetchnta",	{ Mb }, 0 },
   11725   },
   11726   {
   11727     /* MOD_0F18_REG_1 */
   11728     { "prefetcht0",	{ Mb }, 0 },
   11729   },
   11730   {
   11731     /* MOD_0F18_REG_2 */
   11732     { "prefetcht1",	{ Mb }, 0 },
   11733   },
   11734   {
   11735     /* MOD_0F18_REG_3 */
   11736     { "prefetcht2",	{ Mb }, 0 },
   11737   },
   11738   {
   11739     /* MOD_0F18_REG_4 */
   11740     { "nop/reserved",	{ Mb }, 0 },
   11741   },
   11742   {
   11743     /* MOD_0F18_REG_5 */
   11744     { "nop/reserved",	{ Mb }, 0 },
   11745   },
   11746   {
   11747     /* MOD_0F18_REG_6 */
   11748     { "nop/reserved",	{ Mb }, 0 },
   11749   },
   11750   {
   11751     /* MOD_0F18_REG_7 */
   11752     { "nop/reserved",	{ Mb }, 0 },
   11753   },
   11754   {
   11755     /* MOD_0F1A_PREFIX_0 */
   11756     { "bndldx",		{ Gbnd, Ev_bnd }, 0 },
   11757     { "nopQ",		{ Ev }, 0 },
   11758   },
   11759   {
   11760     /* MOD_0F1B_PREFIX_0 */
   11761     { "bndstx",		{ Ev_bnd, Gbnd }, 0 },
   11762     { "nopQ",		{ Ev }, 0 },
   11763   },
   11764   {
   11765     /* MOD_0F1B_PREFIX_1 */
   11766     { "bndmk",		{ Gbnd, Ev_bnd }, 0 },
   11767     { "nopQ",		{ Ev }, 0 },
   11768   },
   11769   {
   11770     /* MOD_0F24 */
   11771     { Bad_Opcode },
   11772     { "movL",		{ Rd, Td }, 0 },
   11773   },
   11774   {
   11775     /* MOD_0F26 */
   11776     { Bad_Opcode },
   11777     { "movL",		{ Td, Rd }, 0 },
   11778   },
   11779   {
   11780     /* MOD_0F2B_PREFIX_0 */
   11781     {"movntps",		{ Mx, XM }, PREFIX_OPCODE },
   11782   },
   11783   {
   11784     /* MOD_0F2B_PREFIX_1 */
   11785     {"movntss",		{ Md, XM }, PREFIX_OPCODE },
   11786   },
   11787   {
   11788     /* MOD_0F2B_PREFIX_2 */
   11789     {"movntpd",		{ Mx, XM }, PREFIX_OPCODE },
   11790   },
   11791   {
   11792     /* MOD_0F2B_PREFIX_3 */
   11793     {"movntsd",		{ Mq, XM }, PREFIX_OPCODE },
   11794   },
   11795   {
   11796     /* MOD_0F51 */
   11797     { Bad_Opcode },
   11798     { "movmskpX",	{ Gdq, XS }, PREFIX_OPCODE },
   11799   },
   11800   {
   11801     /* MOD_0F71_REG_2 */
   11802     { Bad_Opcode },
   11803     { "psrlw",		{ MS, Ib }, 0 },
   11804   },
   11805   {
   11806     /* MOD_0F71_REG_4 */
   11807     { Bad_Opcode },
   11808     { "psraw",		{ MS, Ib }, 0 },
   11809   },
   11810   {
   11811     /* MOD_0F71_REG_6 */
   11812     { Bad_Opcode },
   11813     { "psllw",		{ MS, Ib }, 0 },
   11814   },
   11815   {
   11816     /* MOD_0F72_REG_2 */
   11817     { Bad_Opcode },
   11818     { "psrld",		{ MS, Ib }, 0 },
   11819   },
   11820   {
   11821     /* MOD_0F72_REG_4 */
   11822     { Bad_Opcode },
   11823     { "psrad",		{ MS, Ib }, 0 },
   11824   },
   11825   {
   11826     /* MOD_0F72_REG_6 */
   11827     { Bad_Opcode },
   11828     { "pslld",		{ MS, Ib }, 0 },
   11829   },
   11830   {
   11831     /* MOD_0F73_REG_2 */
   11832     { Bad_Opcode },
   11833     { "psrlq",		{ MS, Ib }, 0 },
   11834   },
   11835   {
   11836     /* MOD_0F73_REG_3 */
   11837     { Bad_Opcode },
   11838     { PREFIX_TABLE (PREFIX_0F73_REG_3) },
   11839   },
   11840   {
   11841     /* MOD_0F73_REG_6 */
   11842     { Bad_Opcode },
   11843     { "psllq",		{ MS, Ib }, 0 },
   11844   },
   11845   {
   11846     /* MOD_0F73_REG_7 */
   11847     { Bad_Opcode },
   11848     { PREFIX_TABLE (PREFIX_0F73_REG_7) },
   11849   },
   11850   {
   11851     /* MOD_0FAE_REG_0 */
   11852     { "fxsave",		{ FXSAVE }, 0 },
   11853     { PREFIX_TABLE (PREFIX_0FAE_REG_0) },
   11854   },
   11855   {
   11856     /* MOD_0FAE_REG_1 */
   11857     { "fxrstor",	{ FXSAVE }, 0 },
   11858     { PREFIX_TABLE (PREFIX_0FAE_REG_1) },
   11859   },
   11860   {
   11861     /* MOD_0FAE_REG_2 */
   11862     { "ldmxcsr",	{ Md }, 0 },
   11863     { PREFIX_TABLE (PREFIX_0FAE_REG_2) },
   11864   },
   11865   {
   11866     /* MOD_0FAE_REG_3 */
   11867     { "stmxcsr",	{ Md }, 0 },
   11868     { PREFIX_TABLE (PREFIX_0FAE_REG_3) },
   11869   },
   11870   {
   11871     /* MOD_0FAE_REG_4 */
   11872     { "xsave",		{ FXSAVE }, 0 },
   11873   },
   11874   {
   11875     /* MOD_0FAE_REG_5 */
   11876     { "xrstor",		{ FXSAVE }, 0 },
   11877     { RM_TABLE (RM_0FAE_REG_5) },
   11878   },
   11879   {
   11880     /* MOD_0FAE_REG_6 */
   11881     { PREFIX_TABLE (PREFIX_0FAE_REG_6) },
   11882     { RM_TABLE (RM_0FAE_REG_6) },
   11883   },
   11884   {
   11885     /* MOD_0FAE_REG_7 */
   11886     { PREFIX_TABLE (PREFIX_0FAE_REG_7) },
   11887     { RM_TABLE (RM_0FAE_REG_7) },
   11888   },
   11889   {
   11890     /* MOD_0FB2 */
   11891     { "lssS",		{ Gv, Mp }, 0 },
   11892   },
   11893   {
   11894     /* MOD_0FB4 */
   11895     { "lfsS",		{ Gv, Mp }, 0 },
   11896   },
   11897   {
   11898     /* MOD_0FB5 */
   11899     { "lgsS",		{ Gv, Mp }, 0 },
   11900   },
   11901   {
   11902     /* MOD_0FC3 */
   11903     { PREFIX_TABLE (PREFIX_MOD_0_0FC3) },
   11904   },
   11905   {
   11906     /* MOD_0FC7_REG_3 */
   11907     { "xrstors",	{ FXSAVE }, 0 },
   11908   },
   11909   {
   11910     /* MOD_0FC7_REG_4 */
   11911     { "xsavec",		{ FXSAVE }, 0 },
   11912   },
   11913   {
   11914     /* MOD_0FC7_REG_5 */
   11915     { "xsaves",		{ FXSAVE }, 0 },
   11916   },
   11917   {
   11918     /* MOD_0FC7_REG_6 */
   11919     { PREFIX_TABLE (PREFIX_MOD_0_0FC7_REG_6) },
   11920     { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_6) }
   11921   },
   11922   {
   11923     /* MOD_0FC7_REG_7 */
   11924     { "vmptrst",	{ Mq }, 0 },
   11925     { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_7) }
   11926   },
   11927   {
   11928     /* MOD_0FD7 */
   11929     { Bad_Opcode },
   11930     { "pmovmskb",	{ Gdq, MS }, 0 },
   11931   },
   11932   {
   11933     /* MOD_0FE7_PREFIX_2 */
   11934     { "movntdq",	{ Mx, XM }, 0 },
   11935   },
   11936   {
   11937     /* MOD_0FF0_PREFIX_3 */
   11938     { "lddqu",		{ XM, M }, 0 },
   11939   },
   11940   {
   11941     /* MOD_0F382A_PREFIX_2 */
   11942     { "movntdqa",	{ XM, Mx }, 0 },
   11943   },
   11944   {
   11945     /* MOD_62_32BIT */
   11946     { "bound{S|}",	{ Gv, Ma }, 0 },
   11947     { EVEX_TABLE (EVEX_0F) },
   11948   },
   11949   {
   11950     /* MOD_C4_32BIT */
   11951     { "lesS",		{ Gv, Mp }, 0 },
   11952     { VEX_C4_TABLE (VEX_0F) },
   11953   },
   11954   {
   11955     /* MOD_C5_32BIT */
   11956     { "ldsS",		{ Gv, Mp }, 0 },
   11957     { VEX_C5_TABLE (VEX_0F) },
   11958   },
   11959   {
   11960     /* MOD_VEX_0F12_PREFIX_0 */
   11961     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
   11962     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
   11963   },
   11964   {
   11965     /* MOD_VEX_0F13 */
   11966     { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
   11967   },
   11968   {
   11969     /* MOD_VEX_0F16_PREFIX_0 */
   11970     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
   11971     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
   11972   },
   11973   {
   11974     /* MOD_VEX_0F17 */
   11975     { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
   11976   },
   11977   {
   11978     /* MOD_VEX_0F2B */
   11979     { VEX_W_TABLE (VEX_W_0F2B_M_0) },
   11980   },
   11981   {
   11982     /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
   11983     { Bad_Opcode },
   11984     { "kandw",          { MaskG, MaskVex, MaskR }, 0 },
   11985   },
   11986   {
   11987     /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
   11988     { Bad_Opcode },
   11989     { "kandq",          { MaskG, MaskVex, MaskR }, 0 },
   11990   },
   11991   {
   11992     /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
   11993     { Bad_Opcode },
   11994     { "kandb",          { MaskG, MaskVex, MaskR }, 0 },
   11995   },
   11996   {
   11997     /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
   11998     { Bad_Opcode },
   11999     { "kandd",          { MaskG, MaskVex, MaskR }, 0 },
   12000   },
   12001   {
   12002     /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
   12003     { Bad_Opcode },
   12004     { "kandnw",         { MaskG, MaskVex, MaskR }, 0 },
   12005   },
   12006   {
   12007     /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
   12008     { Bad_Opcode },
   12009     { "kandnq",         { MaskG, MaskVex, MaskR }, 0 },
   12010   },
   12011   {
   12012     /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
   12013     { Bad_Opcode },
   12014     { "kandnb",         { MaskG, MaskVex, MaskR }, 0 },
   12015   },
   12016   {
   12017     /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
   12018     { Bad_Opcode },
   12019     { "kandnd",         { MaskG, MaskVex, MaskR }, 0 },
   12020   },
   12021   {
   12022     /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
   12023     { Bad_Opcode },
   12024     { "knotw",          { MaskG, MaskR }, 0 },
   12025   },
   12026   {
   12027     /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
   12028     { Bad_Opcode },
   12029     { "knotq",          { MaskG, MaskR }, 0 },
   12030   },
   12031   {
   12032     /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
   12033     { Bad_Opcode },
   12034     { "knotb",          { MaskG, MaskR }, 0 },
   12035   },
   12036   {
   12037     /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
   12038     { Bad_Opcode },
   12039     { "knotd",          { MaskG, MaskR }, 0 },
   12040   },
   12041   {
   12042     /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
   12043     { Bad_Opcode },
   12044     { "korw",       { MaskG, MaskVex, MaskR }, 0 },
   12045   },
   12046   {
   12047     /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
   12048     { Bad_Opcode },
   12049     { "korq",       { MaskG, MaskVex, MaskR }, 0 },
   12050   },
   12051   {
   12052     /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
   12053     { Bad_Opcode },
   12054     { "korb",       { MaskG, MaskVex, MaskR }, 0 },
   12055   },
   12056   {
   12057     /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
   12058     { Bad_Opcode },
   12059     { "kord",       { MaskG, MaskVex, MaskR }, 0 },
   12060   },
   12061  {
   12062     /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
   12063     { Bad_Opcode },
   12064     { "kxnorw",     { MaskG, MaskVex, MaskR }, 0 },
   12065   },
   12066   {
   12067     /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
   12068     { Bad_Opcode },
   12069     { "kxnorq",     { MaskG, MaskVex, MaskR }, 0 },
   12070   },
   12071   {
   12072     /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
   12073     { Bad_Opcode },
   12074     { "kxnorb",     { MaskG, MaskVex, MaskR }, 0 },
   12075   },
   12076   {
   12077     /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
   12078     { Bad_Opcode },
   12079     { "kxnord",     { MaskG, MaskVex, MaskR }, 0 },
   12080   },
   12081   {
   12082     /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
   12083     { Bad_Opcode },
   12084     { "kxorw",      { MaskG, MaskVex, MaskR }, 0 },
   12085   },
   12086   {
   12087     /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
   12088     { Bad_Opcode },
   12089     { "kxorq",      { MaskG, MaskVex, MaskR }, 0 },
   12090   },
   12091   {
   12092     /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
   12093     { Bad_Opcode },
   12094     { "kxorb",      { MaskG, MaskVex, MaskR }, 0 },
   12095   },
   12096   {
   12097     /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
   12098     { Bad_Opcode },
   12099     { "kxord",      { MaskG, MaskVex, MaskR }, 0 },
   12100   },
   12101   {
   12102     /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
   12103     { Bad_Opcode },
   12104     { "kaddw",          { MaskG, MaskVex, MaskR }, 0 },
   12105   },
   12106   {
   12107     /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
   12108     { Bad_Opcode },
   12109     { "kaddq",          { MaskG, MaskVex, MaskR }, 0 },
   12110   },
   12111   {
   12112     /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
   12113     { Bad_Opcode },
   12114     { "kaddb",          { MaskG, MaskVex, MaskR }, 0 },
   12115   },
   12116   {
   12117     /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
   12118     { Bad_Opcode },
   12119     { "kaddd",          { MaskG, MaskVex, MaskR }, 0 },
   12120   },
   12121   {
   12122     /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
   12123     { Bad_Opcode },
   12124     { "kunpckwd",   { MaskG, MaskVex, MaskR }, 0 },
   12125   },
   12126   {
   12127     /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
   12128     { Bad_Opcode },
   12129     { "kunpckdq",   { MaskG, MaskVex, MaskR }, 0 },
   12130   },
   12131   {
   12132     /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
   12133     { Bad_Opcode },
   12134     { "kunpckbw",   { MaskG, MaskVex, MaskR }, 0 },
   12135   },
   12136   {
   12137     /* MOD_VEX_0F50 */
   12138     { Bad_Opcode },
   12139     { VEX_W_TABLE (VEX_W_0F50_M_0) },
   12140   },
   12141   {
   12142     /* MOD_VEX_0F71_REG_2 */
   12143     { Bad_Opcode },
   12144     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) },
   12145   },
   12146   {
   12147     /* MOD_VEX_0F71_REG_4 */
   12148     { Bad_Opcode },
   12149     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) },
   12150   },
   12151   {
   12152     /* MOD_VEX_0F71_REG_6 */
   12153     { Bad_Opcode },
   12154     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) },
   12155   },
   12156   {
   12157     /* MOD_VEX_0F72_REG_2 */
   12158     { Bad_Opcode },
   12159     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) },
   12160   },
   12161   {
   12162     /* MOD_VEX_0F72_REG_4 */
   12163     { Bad_Opcode },
   12164     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) },
   12165   },
   12166   {
   12167     /* MOD_VEX_0F72_REG_6 */
   12168     { Bad_Opcode },
   12169     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) },
   12170   },
   12171   {
   12172     /* MOD_VEX_0F73_REG_2 */
   12173     { Bad_Opcode },
   12174     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) },
   12175   },
   12176   {
   12177     /* MOD_VEX_0F73_REG_3 */
   12178     { Bad_Opcode },
   12179     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) },
   12180   },
   12181   {
   12182     /* MOD_VEX_0F73_REG_6 */
   12183     { Bad_Opcode },
   12184     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) },
   12185   },
   12186   {
   12187     /* MOD_VEX_0F73_REG_7 */
   12188     { Bad_Opcode },
   12189     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) },
   12190   },
   12191   {
   12192     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
   12193     { "kmovw",		{ Ew, MaskG }, 0 },
   12194     { Bad_Opcode },
   12195   },
   12196   {
   12197     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
   12198     { "kmovq",		{ Eq, MaskG }, 0 },
   12199     { Bad_Opcode },
   12200   },
   12201   {
   12202     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
   12203     { "kmovb",		{ Eb, MaskG }, 0 },
   12204     { Bad_Opcode },
   12205   },
   12206   {
   12207     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
   12208     { "kmovd",		{ Ed, MaskG }, 0 },
   12209     { Bad_Opcode },
   12210   },
   12211   {
   12212     /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
   12213     { Bad_Opcode },
   12214     { "kmovw",		{ MaskG, Rdq }, 0 },
   12215   },
   12216   {
   12217     /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
   12218     { Bad_Opcode },
   12219     { "kmovb",		{ MaskG, Rdq }, 0 },
   12220   },
   12221   {
   12222     /* MOD_VEX_W_0_0F92_P_3_LEN_0 */
   12223     { Bad_Opcode },
   12224     { "kmovd",		{ MaskG, Rdq }, 0 },
   12225   },
   12226   {
   12227     /* MOD_VEX_W_1_0F92_P_3_LEN_0 */
   12228     { Bad_Opcode },
   12229     { "kmovq",		{ MaskG, Rdq }, 0 },
   12230   },
   12231   {
   12232     /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
   12233     { Bad_Opcode },
   12234     { "kmovw",		{ Gdq, MaskR }, 0 },
   12235   },
   12236   {
   12237     /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
   12238     { Bad_Opcode },
   12239     { "kmovb",		{ Gdq, MaskR }, 0 },
   12240   },
   12241   {
   12242     /* MOD_VEX_W_0_0F93_P_3_LEN_0 */
   12243     { Bad_Opcode },
   12244     { "kmovd",		{ Gdq, MaskR }, 0 },
   12245   },
   12246   {
   12247     /* MOD_VEX_W_1_0F93_P_3_LEN_0 */
   12248     { Bad_Opcode },
   12249     { "kmovq",		{ Gdq, MaskR }, 0 },
   12250   },
   12251   {
   12252     /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
   12253     { Bad_Opcode },
   12254     { "kortestw", { MaskG, MaskR }, 0 },
   12255   },
   12256   {
   12257     /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
   12258     { Bad_Opcode },
   12259     { "kortestq", { MaskG, MaskR }, 0 },
   12260   },
   12261   {
   12262     /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
   12263     { Bad_Opcode },
   12264     { "kortestb", { MaskG, MaskR }, 0 },
   12265   },
   12266   {
   12267     /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
   12268     { Bad_Opcode },
   12269     { "kortestd", { MaskG, MaskR }, 0 },
   12270   },
   12271   {
   12272     /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
   12273     { Bad_Opcode },
   12274     { "ktestw", { MaskG, MaskR }, 0 },
   12275   },
   12276   {
   12277     /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
   12278     { Bad_Opcode },
   12279     { "ktestq", { MaskG, MaskR }, 0 },
   12280   },
   12281   {
   12282     /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
   12283     { Bad_Opcode },
   12284     { "ktestb", { MaskG, MaskR }, 0 },
   12285   },
   12286   {
   12287     /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
   12288     { Bad_Opcode },
   12289     { "ktestd", { MaskG, MaskR }, 0 },
   12290   },
   12291   {
   12292     /* MOD_VEX_0FAE_REG_2 */
   12293     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
   12294   },
   12295   {
   12296     /* MOD_VEX_0FAE_REG_3 */
   12297     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
   12298   },
   12299   {
   12300     /* MOD_VEX_0FD7_PREFIX_2 */
   12301     { Bad_Opcode },
   12302     { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1) },
   12303   },
   12304   {
   12305     /* MOD_VEX_0FE7_PREFIX_2 */
   12306     { VEX_W_TABLE (VEX_W_0FE7_P_2_M_0) },
   12307   },
   12308   {
   12309     /* MOD_VEX_0FF0_PREFIX_3 */
   12310     { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0) },
   12311   },
   12312   {
   12313     /* MOD_VEX_0F381A_PREFIX_2 */
   12314     { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) },
   12315   },
   12316   {
   12317     /* MOD_VEX_0F382A_PREFIX_2 */
   12318     { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0) },
   12319   },
   12320   {
   12321     /* MOD_VEX_0F382C_PREFIX_2 */
   12322     { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) },
   12323   },
   12324   {
   12325     /* MOD_VEX_0F382D_PREFIX_2 */
   12326     { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) },
   12327   },
   12328   {
   12329     /* MOD_VEX_0F382E_PREFIX_2 */
   12330     { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) },
   12331   },
   12332   {
   12333     /* MOD_VEX_0F382F_PREFIX_2 */
   12334     { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) },
   12335   },
   12336   {
   12337     /* MOD_VEX_0F385A_PREFIX_2 */
   12338     { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) },
   12339   },
   12340   {
   12341     /* MOD_VEX_0F388C_PREFIX_2 */
   12342     { "vpmaskmov%LW",	{ XM, Vex, Mx }, 0 },
   12343   },
   12344   {
   12345     /* MOD_VEX_0F388E_PREFIX_2 */
   12346     { "vpmaskmov%LW",	{ Mx, Vex, XM }, 0 },
   12347   },
   12348   {
   12349     /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */
   12350     { Bad_Opcode },
   12351     { "kshiftrb",       { MaskG, MaskR, Ib }, 0 },
   12352   },
   12353   {
   12354     /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */
   12355     { Bad_Opcode },
   12356     { "kshiftrw",       { MaskG, MaskR, Ib }, 0 },
   12357   },
   12358   {
   12359     /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */
   12360     { Bad_Opcode },
   12361     { "kshiftrd",       { MaskG, MaskR, Ib }, 0 },
   12362   },
   12363   {
   12364     /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */
   12365     { Bad_Opcode },
   12366     { "kshiftrq",       { MaskG, MaskR, Ib }, 0 },
   12367   },
   12368   {
   12369     /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */
   12370     { Bad_Opcode },
   12371     { "kshiftlb",       { MaskG, MaskR, Ib }, 0 },
   12372   },
   12373   {
   12374     /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */
   12375     { Bad_Opcode },
   12376     { "kshiftlw",       { MaskG, MaskR, Ib }, 0 },
   12377   },
   12378   {
   12379     /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */
   12380     { Bad_Opcode },
   12381     { "kshiftld",       { MaskG, MaskR, Ib }, 0 },
   12382   },
   12383   {
   12384     /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */
   12385     { Bad_Opcode },
   12386     { "kshiftlq",       { MaskG, MaskR, Ib }, 0 },
   12387   },
   12388 #define NEED_MOD_TABLE
   12389 #include "i386-dis-evex.h"
   12390 #undef NEED_MOD_TABLE
   12391 };
   12392 
   12393 static const struct dis386 rm_table[][8] = {
   12394   {
   12395     /* RM_C6_REG_7 */
   12396     { "xabort",		{ Skip_MODRM, Ib }, 0 },
   12397   },
   12398   {
   12399     /* RM_C7_REG_7 */
   12400     { "xbeginT",	{ Skip_MODRM, Jv }, 0 },
   12401   },
   12402   {
   12403     /* RM_0F01_REG_0 */
   12404     { Bad_Opcode },
   12405     { "vmcall",		{ Skip_MODRM }, 0 },
   12406     { "vmlaunch",	{ Skip_MODRM }, 0 },
   12407     { "vmresume",	{ Skip_MODRM }, 0 },
   12408     { "vmxoff",		{ Skip_MODRM }, 0 },
   12409   },
   12410   {
   12411     /* RM_0F01_REG_1 */
   12412     { "monitor",	{ { OP_Monitor, 0 } }, 0 },
   12413     { "mwait",		{ { OP_Mwait, 0 } }, 0 },
   12414     { "clac",		{ Skip_MODRM }, 0 },
   12415     { "stac",		{ Skip_MODRM }, 0 },
   12416     { Bad_Opcode },
   12417     { Bad_Opcode },
   12418     { Bad_Opcode },
   12419     { "encls",		{ Skip_MODRM }, 0 },
   12420   },
   12421   {
   12422     /* RM_0F01_REG_2 */
   12423     { "xgetbv",		{ Skip_MODRM }, 0 },
   12424     { "xsetbv",		{ Skip_MODRM }, 0 },
   12425     { Bad_Opcode },
   12426     { Bad_Opcode },
   12427     { "vmfunc",		{ Skip_MODRM }, 0 },
   12428     { "xend",		{ Skip_MODRM }, 0 },
   12429     { "xtest",		{ Skip_MODRM }, 0 },
   12430     { "enclu",		{ Skip_MODRM }, 0 },
   12431   },
   12432   {
   12433     /* RM_0F01_REG_3 */
   12434     { "vmrun",		{ Skip_MODRM }, 0 },
   12435     { "vmmcall",	{ Skip_MODRM }, 0 },
   12436     { "vmload",		{ Skip_MODRM }, 0 },
   12437     { "vmsave",		{ Skip_MODRM }, 0 },
   12438     { "stgi",		{ Skip_MODRM }, 0 },
   12439     { "clgi",		{ Skip_MODRM }, 0 },
   12440     { "skinit",		{ Skip_MODRM }, 0 },
   12441     { "invlpga",	{ Skip_MODRM }, 0 },
   12442   },
   12443   {
   12444     /* RM_0F01_REG_5 */
   12445     { Bad_Opcode },
   12446     { Bad_Opcode },
   12447     { Bad_Opcode },
   12448     { Bad_Opcode },
   12449     { Bad_Opcode },
   12450     { Bad_Opcode },
   12451     { "rdpkru",		{ Skip_MODRM }, 0 },
   12452     { "wrpkru",		{ Skip_MODRM }, 0 },
   12453   },
   12454   {
   12455     /* RM_0F01_REG_7 */
   12456     { "swapgs",		{ Skip_MODRM }, 0  },
   12457     { "rdtscp",		{ Skip_MODRM }, 0  },
   12458     { "monitorx",	{ { OP_Monitor, 0 } }, 0  },
   12459     { "mwaitx",		{ { OP_Mwaitx,  0 } }, 0  },
   12460     { "clzero",		{ Skip_MODRM }, 0  },
   12461   },
   12462   {
   12463     /* RM_0FAE_REG_5 */
   12464     { "lfence",		{ Skip_MODRM }, 0 },
   12465   },
   12466   {
   12467     /* RM_0FAE_REG_6 */
   12468     { "mfence",		{ Skip_MODRM }, 0 },
   12469   },
   12470   {
   12471     /* RM_0FAE_REG_7 */
   12472     { PREFIX_TABLE (PREFIX_RM_0_0FAE_REG_7) },
   12473   },
   12474 };
   12475 
   12476 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
   12477 
   12478 /* We use the high bit to indicate different name for the same
   12479    prefix.  */
   12480 #define REP_PREFIX	(0xf3 | 0x100)
   12481 #define XACQUIRE_PREFIX	(0xf2 | 0x200)
   12482 #define XRELEASE_PREFIX	(0xf3 | 0x400)
   12483 #define BND_PREFIX	(0xf2 | 0x400)
   12484 
   12485 static int
   12486 ckprefix (void)
   12487 {
   12488   int newrex, i, length;
   12489   rex = 0;
   12490   rex_ignored = 0;
   12491   prefixes = 0;
   12492   used_prefixes = 0;
   12493   rex_used = 0;
   12494   last_lock_prefix = -1;
   12495   last_repz_prefix = -1;
   12496   last_repnz_prefix = -1;
   12497   last_data_prefix = -1;
   12498   last_addr_prefix = -1;
   12499   last_rex_prefix = -1;
   12500   last_seg_prefix = -1;
   12501   fwait_prefix = -1;
   12502   active_seg_prefix = 0;
   12503   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
   12504     all_prefixes[i] = 0;
   12505   i = 0;
   12506   length = 0;
   12507   /* The maximum instruction length is 15bytes.  */
   12508   while (length < MAX_CODE_LENGTH - 1)
   12509     {
   12510       FETCH_DATA (the_info, codep + 1);
   12511       newrex = 0;
   12512       switch (*codep)
   12513 	{
   12514 	/* REX prefixes family.  */
   12515 	case 0x40:
   12516 	case 0x41:
   12517 	case 0x42:
   12518 	case 0x43:
   12519 	case 0x44:
   12520 	case 0x45:
   12521 	case 0x46:
   12522 	case 0x47:
   12523 	case 0x48:
   12524 	case 0x49:
   12525 	case 0x4a:
   12526 	case 0x4b:
   12527 	case 0x4c:
   12528 	case 0x4d:
   12529 	case 0x4e:
   12530 	case 0x4f:
   12531 	  if (address_mode == mode_64bit)
   12532 	    newrex = *codep;
   12533 	  else
   12534 	    return 1;
   12535 	  last_rex_prefix = i;
   12536 	  break;
   12537 	case 0xf3:
   12538 	  prefixes |= PREFIX_REPZ;
   12539 	  last_repz_prefix = i;
   12540 	  break;
   12541 	case 0xf2:
   12542 	  prefixes |= PREFIX_REPNZ;
   12543 	  last_repnz_prefix = i;
   12544 	  break;
   12545 	case 0xf0:
   12546 	  prefixes |= PREFIX_LOCK;
   12547 	  last_lock_prefix = i;
   12548 	  break;
   12549 	case 0x2e:
   12550 	  prefixes |= PREFIX_CS;
   12551 	  last_seg_prefix = i;
   12552 	  active_seg_prefix = PREFIX_CS;
   12553 	  break;
   12554 	case 0x36:
   12555 	  prefixes |= PREFIX_SS;
   12556 	  last_seg_prefix = i;
   12557 	  active_seg_prefix = PREFIX_SS;
   12558 	  break;
   12559 	case 0x3e:
   12560 	  prefixes |= PREFIX_DS;
   12561 	  last_seg_prefix = i;
   12562 	  active_seg_prefix = PREFIX_DS;
   12563 	  break;
   12564 	case 0x26:
   12565 	  prefixes |= PREFIX_ES;
   12566 	  last_seg_prefix = i;
   12567 	  active_seg_prefix = PREFIX_ES;
   12568 	  break;
   12569 	case 0x64:
   12570 	  prefixes |= PREFIX_FS;
   12571 	  last_seg_prefix = i;
   12572 	  active_seg_prefix = PREFIX_FS;
   12573 	  break;
   12574 	case 0x65:
   12575 	  prefixes |= PREFIX_GS;
   12576 	  last_seg_prefix = i;
   12577 	  active_seg_prefix = PREFIX_GS;
   12578 	  break;
   12579 	case 0x66:
   12580 	  prefixes |= PREFIX_DATA;
   12581 	  last_data_prefix = i;
   12582 	  break;
   12583 	case 0x67:
   12584 	  prefixes |= PREFIX_ADDR;
   12585 	  last_addr_prefix = i;
   12586 	  break;
   12587 	case FWAIT_OPCODE:
   12588 	  /* fwait is really an instruction.  If there are prefixes
   12589 	     before the fwait, they belong to the fwait, *not* to the
   12590 	     following instruction.  */
   12591 	  fwait_prefix = i;
   12592 	  if (prefixes || rex)
   12593 	    {
   12594 	      prefixes |= PREFIX_FWAIT;
   12595 	      codep++;
   12596 	      /* This ensures that the previous REX prefixes are noticed
   12597 		 as unused prefixes, as in the return case below.  */
   12598 	      rex_used = rex;
   12599 	      return 1;
   12600 	    }
   12601 	  prefixes = PREFIX_FWAIT;
   12602 	  break;
   12603 	default:
   12604 	  return 1;
   12605 	}
   12606       /* Rex is ignored when followed by another prefix.  */
   12607       if (rex)
   12608 	{
   12609 	  rex_used = rex;
   12610 	  return 1;
   12611 	}
   12612       if (*codep != FWAIT_OPCODE)
   12613 	all_prefixes[i++] = *codep;
   12614       rex = newrex;
   12615       codep++;
   12616       length++;
   12617     }
   12618   return 0;
   12619 }
   12620 
   12621 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
   12622    prefix byte.  */
   12623 
   12624 static const char *
   12625 prefix_name (int pref, int sizeflag)
   12626 {
   12627   static const char *rexes [16] =
   12628     {
   12629       "rex",		/* 0x40 */
   12630       "rex.B",		/* 0x41 */
   12631       "rex.X",		/* 0x42 */
   12632       "rex.XB",		/* 0x43 */
   12633       "rex.R",		/* 0x44 */
   12634       "rex.RB",		/* 0x45 */
   12635       "rex.RX",		/* 0x46 */
   12636       "rex.RXB",	/* 0x47 */
   12637       "rex.W",		/* 0x48 */
   12638       "rex.WB",		/* 0x49 */
   12639       "rex.WX",		/* 0x4a */
   12640       "rex.WXB",	/* 0x4b */
   12641       "rex.WR",		/* 0x4c */
   12642       "rex.WRB",	/* 0x4d */
   12643       "rex.WRX",	/* 0x4e */
   12644       "rex.WRXB",	/* 0x4f */
   12645     };
   12646 
   12647   switch (pref)
   12648     {
   12649     /* REX prefixes family.  */
   12650     case 0x40:
   12651     case 0x41:
   12652     case 0x42:
   12653     case 0x43:
   12654     case 0x44:
   12655     case 0x45:
   12656     case 0x46:
   12657     case 0x47:
   12658     case 0x48:
   12659     case 0x49:
   12660     case 0x4a:
   12661     case 0x4b:
   12662     case 0x4c:
   12663     case 0x4d:
   12664     case 0x4e:
   12665     case 0x4f:
   12666       return rexes [pref - 0x40];
   12667     case 0xf3:
   12668       return "repz";
   12669     case 0xf2:
   12670       return "repnz";
   12671     case 0xf0:
   12672       return "lock";
   12673     case 0x2e:
   12674       return "cs";
   12675     case 0x36:
   12676       return "ss";
   12677     case 0x3e:
   12678       return "ds";
   12679     case 0x26:
   12680       return "es";
   12681     case 0x64:
   12682       return "fs";
   12683     case 0x65:
   12684       return "gs";
   12685     case 0x66:
   12686       return (sizeflag & DFLAG) ? "data16" : "data32";
   12687     case 0x67:
   12688       if (address_mode == mode_64bit)
   12689 	return (sizeflag & AFLAG) ? "addr32" : "addr64";
   12690       else
   12691 	return (sizeflag & AFLAG) ? "addr16" : "addr32";
   12692     case FWAIT_OPCODE:
   12693       return "fwait";
   12694     case REP_PREFIX:
   12695       return "rep";
   12696     case XACQUIRE_PREFIX:
   12697       return "xacquire";
   12698     case XRELEASE_PREFIX:
   12699       return "xrelease";
   12700     case BND_PREFIX:
   12701       return "bnd";
   12702     default:
   12703       return NULL;
   12704     }
   12705 }
   12706 
   12707 static char op_out[MAX_OPERANDS][100];
   12708 static int op_ad, op_index[MAX_OPERANDS];
   12709 static int two_source_ops;
   12710 static bfd_vma op_address[MAX_OPERANDS];
   12711 static bfd_vma op_riprel[MAX_OPERANDS];
   12712 static bfd_vma start_pc;
   12713 
   12714 /*
   12715  *   On the 386's of 1988, the maximum length of an instruction is 15 bytes.
   12716  *   (see topic "Redundant prefixes" in the "Differences from 8086"
   12717  *   section of the "Virtual 8086 Mode" chapter.)
   12718  * 'pc' should be the address of this instruction, it will
   12719  *   be used to print the target address if this is a relative jump or call
   12720  * The function returns the length of this instruction in bytes.
   12721  */
   12722 
   12723 static char intel_syntax;
   12724 static char intel_mnemonic = !SYSV386_COMPAT;
   12725 static char open_char;
   12726 static char close_char;
   12727 static char separator_char;
   12728 static char scale_char;
   12729 
   12730 enum x86_64_isa
   12731 {
   12732   amd64 = 0,
   12733   intel64
   12734 };
   12735 
   12736 static enum x86_64_isa isa64;
   12737 
   12738 /* Here for backwards compatibility.  When gdb stops using
   12739    print_insn_i386_att and print_insn_i386_intel these functions can
   12740    disappear, and print_insn_i386 be merged into print_insn.  */
   12741 int
   12742 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
   12743 {
   12744   intel_syntax = 0;
   12745 
   12746   return print_insn (pc, info);
   12747 }
   12748 
   12749 int
   12750 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
   12751 {
   12752   intel_syntax = 1;
   12753 
   12754   return print_insn (pc, info);
   12755 }
   12756 
   12757 int
   12758 print_insn_i386 (bfd_vma pc, disassemble_info *info)
   12759 {
   12760   intel_syntax = -1;
   12761 
   12762   return print_insn (pc, info);
   12763 }
   12764 
   12765 void
   12766 print_i386_disassembler_options (FILE *stream)
   12767 {
   12768   fprintf (stream, _("\n\
   12769 The following i386/x86-64 specific disassembler options are supported for use\n\
   12770 with the -M switch (multiple options should be separated by commas):\n"));
   12771 
   12772   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
   12773   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
   12774   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
   12775   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
   12776   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
   12777   fprintf (stream, _("  att-mnemonic\n"
   12778 		     "              Display instruction in AT&T mnemonic\n"));
   12779   fprintf (stream, _("  intel-mnemonic\n"
   12780 		     "              Display instruction in Intel mnemonic\n"));
   12781   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
   12782   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
   12783   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
   12784   fprintf (stream, _("  data32      Assume 32bit data size\n"));
   12785   fprintf (stream, _("  data16      Assume 16bit data size\n"));
   12786   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
   12787   fprintf (stream, _("  amd64       Display instruction in AMD64 ISA\n"));
   12788   fprintf (stream, _("  intel64     Display instruction in Intel64 ISA\n"));
   12789 }
   12790 
   12791 /* Bad opcode.  */
   12792 static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
   12793 
   12794 /* Get a pointer to struct dis386 with a valid name.  */
   12795 
   12796 static const struct dis386 *
   12797 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
   12798 {
   12799   int vindex, vex_table_index;
   12800 
   12801   if (dp->name != NULL)
   12802     return dp;
   12803 
   12804   switch (dp->op[0].bytemode)
   12805     {
   12806     case USE_REG_TABLE:
   12807       dp = &reg_table[dp->op[1].bytemode][modrm.reg];
   12808       break;
   12809 
   12810     case USE_MOD_TABLE:
   12811       vindex = modrm.mod == 0x3 ? 1 : 0;
   12812       dp = &mod_table[dp->op[1].bytemode][vindex];
   12813       break;
   12814 
   12815     case USE_RM_TABLE:
   12816       dp = &rm_table[dp->op[1].bytemode][modrm.rm];
   12817       break;
   12818 
   12819     case USE_PREFIX_TABLE:
   12820       if (need_vex)
   12821 	{
   12822 	  /* The prefix in VEX is implicit.  */
   12823 	  switch (vex.prefix)
   12824 	    {
   12825 	    case 0:
   12826 	      vindex = 0;
   12827 	      break;
   12828 	    case REPE_PREFIX_OPCODE:
   12829 	      vindex = 1;
   12830 	      break;
   12831 	    case DATA_PREFIX_OPCODE:
   12832 	      vindex = 2;
   12833 	      break;
   12834 	    case REPNE_PREFIX_OPCODE:
   12835 	      vindex = 3;
   12836 	      break;
   12837 	    default:
   12838 	      abort ();
   12839 	      break;
   12840 	    }
   12841 	}
   12842       else
   12843 	{
   12844 	  int last_prefix = -1;
   12845 	  int prefix = 0;
   12846 	  vindex = 0;
   12847 	  /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
   12848 	     When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
   12849 	     last one wins.  */
   12850 	  if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
   12851 	    {
   12852 	      if (last_repz_prefix > last_repnz_prefix)
   12853 		{
   12854 		  vindex = 1;
   12855 		  prefix = PREFIX_REPZ;
   12856 		  last_prefix = last_repz_prefix;
   12857 		}
   12858 	      else
   12859 		{
   12860 		  vindex = 3;
   12861 		  prefix = PREFIX_REPNZ;
   12862 		  last_prefix = last_repnz_prefix;
   12863 		}
   12864 
   12865 	      /* Check if prefix should be ignored.  */
   12866 	      if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement
   12867 		     & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT)
   12868 		   & prefix) != 0)
   12869 		vindex = 0;
   12870 	    }
   12871 
   12872 	  if (vindex == 0 && (prefixes & PREFIX_DATA) != 0)
   12873 	    {
   12874 	      vindex = 2;
   12875 	      prefix = PREFIX_DATA;
   12876 	      last_prefix = last_data_prefix;
   12877 	    }
   12878 
   12879 	  if (vindex != 0)
   12880 	    {
   12881 	      used_prefixes |= prefix;
   12882 	      all_prefixes[last_prefix] = 0;
   12883 	    }
   12884 	}
   12885       dp = &prefix_table[dp->op[1].bytemode][vindex];
   12886       break;
   12887 
   12888     case USE_X86_64_TABLE:
   12889       vindex = address_mode == mode_64bit ? 1 : 0;
   12890       dp = &x86_64_table[dp->op[1].bytemode][vindex];
   12891       break;
   12892 
   12893     case USE_3BYTE_TABLE:
   12894       FETCH_DATA (info, codep + 2);
   12895       vindex = *codep++;
   12896       dp = &three_byte_table[dp->op[1].bytemode][vindex];
   12897       end_codep = codep;
   12898       modrm.mod = (*codep >> 6) & 3;
   12899       modrm.reg = (*codep >> 3) & 7;
   12900       modrm.rm = *codep & 7;
   12901       break;
   12902 
   12903     case USE_VEX_LEN_TABLE:
   12904       if (!need_vex)
   12905 	abort ();
   12906 
   12907       switch (vex.length)
   12908 	{
   12909 	case 128:
   12910 	  vindex = 0;
   12911 	  break;
   12912 	case 256:
   12913 	  vindex = 1;
   12914 	  break;
   12915 	default:
   12916 	  abort ();
   12917 	  break;
   12918 	}
   12919 
   12920       dp = &vex_len_table[dp->op[1].bytemode][vindex];
   12921       break;
   12922 
   12923     case USE_XOP_8F_TABLE:
   12924       FETCH_DATA (info, codep + 3);
   12925       /* All bits in the REX prefix are ignored.  */
   12926       rex_ignored = rex;
   12927       rex = ~(*codep >> 5) & 0x7;
   12928 
   12929       /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm".  */
   12930       switch ((*codep & 0x1f))
   12931 	{
   12932 	default:
   12933 	  dp = &bad_opcode;
   12934 	  return dp;
   12935 	case 0x8:
   12936 	  vex_table_index = XOP_08;
   12937 	  break;
   12938 	case 0x9:
   12939 	  vex_table_index = XOP_09;
   12940 	  break;
   12941 	case 0xa:
   12942 	  vex_table_index = XOP_0A;
   12943 	  break;
   12944 	}
   12945       codep++;
   12946       vex.w = *codep & 0x80;
   12947       if (vex.w && address_mode == mode_64bit)
   12948 	rex |= REX_W;
   12949 
   12950       vex.register_specifier = (~(*codep >> 3)) & 0xf;
   12951       if (address_mode != mode_64bit
   12952 	  && vex.register_specifier > 0x7)
   12953 	{
   12954 	  dp = &bad_opcode;
   12955 	  return dp;
   12956 	}
   12957 
   12958       vex.length = (*codep & 0x4) ? 256 : 128;
   12959       switch ((*codep & 0x3))
   12960 	{
   12961 	case 0:
   12962 	  vex.prefix = 0;
   12963 	  break;
   12964 	case 1:
   12965 	  vex.prefix = DATA_PREFIX_OPCODE;
   12966 	  break;
   12967 	case 2:
   12968 	  vex.prefix = REPE_PREFIX_OPCODE;
   12969 	  break;
   12970 	case 3:
   12971 	  vex.prefix = REPNE_PREFIX_OPCODE;
   12972 	  break;
   12973 	}
   12974       need_vex = 1;
   12975       need_vex_reg = 1;
   12976       codep++;
   12977       vindex = *codep++;
   12978       dp = &xop_table[vex_table_index][vindex];
   12979 
   12980       end_codep = codep;
   12981       FETCH_DATA (info, codep + 1);
   12982       modrm.mod = (*codep >> 6) & 3;
   12983       modrm.reg = (*codep >> 3) & 7;
   12984       modrm.rm = *codep & 7;
   12985       break;
   12986 
   12987     case USE_VEX_C4_TABLE:
   12988       /* VEX prefix.  */
   12989       FETCH_DATA (info, codep + 3);
   12990       /* All bits in the REX prefix are ignored.  */
   12991       rex_ignored = rex;
   12992       rex = ~(*codep >> 5) & 0x7;
   12993       switch ((*codep & 0x1f))
   12994 	{
   12995 	default:
   12996 	  dp = &bad_opcode;
   12997 	  return dp;
   12998 	case 0x1:
   12999 	  vex_table_index = VEX_0F;
   13000 	  break;
   13001 	case 0x2:
   13002 	  vex_table_index = VEX_0F38;
   13003 	  break;
   13004 	case 0x3:
   13005 	  vex_table_index = VEX_0F3A;
   13006 	  break;
   13007 	}
   13008       codep++;
   13009       vex.w = *codep & 0x80;
   13010       if (vex.w && address_mode == mode_64bit)
   13011 	rex |= REX_W;
   13012 
   13013       vex.register_specifier = (~(*codep >> 3)) & 0xf;
   13014       if (address_mode != mode_64bit
   13015 	  && vex.register_specifier > 0x7)
   13016 	{
   13017 	  dp = &bad_opcode;
   13018 	  return dp;
   13019 	}
   13020 
   13021       vex.length = (*codep & 0x4) ? 256 : 128;
   13022       switch ((*codep & 0x3))
   13023 	{
   13024 	case 0:
   13025 	  vex.prefix = 0;
   13026 	  break;
   13027 	case 1:
   13028 	  vex.prefix = DATA_PREFIX_OPCODE;
   13029 	  break;
   13030 	case 2:
   13031 	  vex.prefix = REPE_PREFIX_OPCODE;
   13032 	  break;
   13033 	case 3:
   13034 	  vex.prefix = REPNE_PREFIX_OPCODE;
   13035 	  break;
   13036 	}
   13037       need_vex = 1;
   13038       need_vex_reg = 1;
   13039       codep++;
   13040       vindex = *codep++;
   13041       dp = &vex_table[vex_table_index][vindex];
   13042       end_codep = codep;
   13043       /* There is no MODRM byte for VEX [82|77].  */
   13044       if (vindex != 0x77 && vindex != 0x82)
   13045 	{
   13046 	  FETCH_DATA (info, codep + 1);
   13047 	  modrm.mod = (*codep >> 6) & 3;
   13048 	  modrm.reg = (*codep >> 3) & 7;
   13049 	  modrm.rm = *codep & 7;
   13050 	}
   13051       break;
   13052 
   13053     case USE_VEX_C5_TABLE:
   13054       /* VEX prefix.  */
   13055       FETCH_DATA (info, codep + 2);
   13056       /* All bits in the REX prefix are ignored.  */
   13057       rex_ignored = rex;
   13058       rex = (*codep & 0x80) ? 0 : REX_R;
   13059 
   13060       vex.register_specifier = (~(*codep >> 3)) & 0xf;
   13061       if (address_mode != mode_64bit
   13062 	  && vex.register_specifier > 0x7)
   13063 	{
   13064 	  dp = &bad_opcode;
   13065 	  return dp;
   13066 	}
   13067 
   13068       vex.w = 0;
   13069 
   13070       vex.length = (*codep & 0x4) ? 256 : 128;
   13071       switch ((*codep & 0x3))
   13072 	{
   13073 	case 0:
   13074 	  vex.prefix = 0;
   13075 	  break;
   13076 	case 1:
   13077 	  vex.prefix = DATA_PREFIX_OPCODE;
   13078 	  break;
   13079 	case 2:
   13080 	  vex.prefix = REPE_PREFIX_OPCODE;
   13081 	  break;
   13082 	case 3:
   13083 	  vex.prefix = REPNE_PREFIX_OPCODE;
   13084 	  break;
   13085 	}
   13086       need_vex = 1;
   13087       need_vex_reg = 1;
   13088       codep++;
   13089       vindex = *codep++;
   13090       dp = &vex_table[dp->op[1].bytemode][vindex];
   13091       end_codep = codep;
   13092       /* There is no MODRM byte for VEX [82|77].  */
   13093       if (vindex != 0x77 && vindex != 0x82)
   13094 	{
   13095 	  FETCH_DATA (info, codep + 1);
   13096 	  modrm.mod = (*codep >> 6) & 3;
   13097 	  modrm.reg = (*codep >> 3) & 7;
   13098 	  modrm.rm = *codep & 7;
   13099 	}
   13100       break;
   13101 
   13102     case USE_VEX_W_TABLE:
   13103       if (!need_vex)
   13104 	abort ();
   13105 
   13106       dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
   13107       break;
   13108 
   13109     case USE_EVEX_TABLE:
   13110       two_source_ops = 0;
   13111       /* EVEX prefix.  */
   13112       vex.evex = 1;
   13113       FETCH_DATA (info, codep + 4);
   13114       /* All bits in the REX prefix are ignored.  */
   13115       rex_ignored = rex;
   13116       /* The first byte after 0x62.  */
   13117       rex = ~(*codep >> 5) & 0x7;
   13118       vex.r = *codep & 0x10;
   13119       switch ((*codep & 0xf))
   13120 	{
   13121 	default:
   13122 	  return &bad_opcode;
   13123 	case 0x1:
   13124 	  vex_table_index = EVEX_0F;
   13125 	  break;
   13126 	case 0x2:
   13127 	  vex_table_index = EVEX_0F38;
   13128 	  break;
   13129 	case 0x3:
   13130 	  vex_table_index = EVEX_0F3A;
   13131 	  break;
   13132 	}
   13133 
   13134       /* The second byte after 0x62.  */
   13135       codep++;
   13136       vex.w = *codep & 0x80;
   13137       if (vex.w && address_mode == mode_64bit)
   13138 	rex |= REX_W;
   13139 
   13140       vex.register_specifier = (~(*codep >> 3)) & 0xf;
   13141       if (address_mode != mode_64bit)
   13142 	{
   13143 	  /* In 16/32-bit mode silently ignore following bits.  */
   13144 	  rex &= ~REX_B;
   13145 	  vex.r = 1;
   13146 	  vex.v = 1;
   13147 	  vex.register_specifier &= 0x7;
   13148 	}
   13149 
   13150       /* The U bit.  */
   13151       if (!(*codep & 0x4))
   13152 	return &bad_opcode;
   13153 
   13154       switch ((*codep & 0x3))
   13155 	{
   13156 	case 0:
   13157 	  vex.prefix = 0;
   13158 	  break;
   13159 	case 1:
   13160 	  vex.prefix = DATA_PREFIX_OPCODE;
   13161 	  break;
   13162 	case 2:
   13163 	  vex.prefix = REPE_PREFIX_OPCODE;
   13164 	  break;
   13165 	case 3:
   13166 	  vex.prefix = REPNE_PREFIX_OPCODE;
   13167 	  break;
   13168 	}
   13169 
   13170       /* The third byte after 0x62.  */
   13171       codep++;
   13172 
   13173       /* Remember the static rounding bits.  */
   13174       vex.ll = (*codep >> 5) & 3;
   13175       vex.b = (*codep & 0x10) != 0;
   13176 
   13177       vex.v = *codep & 0x8;
   13178       vex.mask_register_specifier = *codep & 0x7;
   13179       vex.zeroing = *codep & 0x80;
   13180 
   13181       need_vex = 1;
   13182       need_vex_reg = 1;
   13183       codep++;
   13184       vindex = *codep++;
   13185       dp = &evex_table[vex_table_index][vindex];
   13186       end_codep = codep;
   13187       FETCH_DATA (info, codep + 1);
   13188       modrm.mod = (*codep >> 6) & 3;
   13189       modrm.reg = (*codep >> 3) & 7;
   13190       modrm.rm = *codep & 7;
   13191 
   13192       /* Set vector length.  */
   13193       if (modrm.mod == 3 && vex.b)
   13194 	vex.length = 512;
   13195       else
   13196 	{
   13197 	  switch (vex.ll)
   13198 	    {
   13199 	    case 0x0:
   13200 	      vex.length = 128;
   13201 	      break;
   13202 	    case 0x1:
   13203 	      vex.length = 256;
   13204 	      break;
   13205 	    case 0x2:
   13206 	      vex.length = 512;
   13207 	      break;
   13208 	    default:
   13209 	      return &bad_opcode;
   13210 	    }
   13211 	}
   13212       break;
   13213 
   13214     case 0:
   13215       dp = &bad_opcode;
   13216       break;
   13217 
   13218     default:
   13219       abort ();
   13220     }
   13221 
   13222   if (dp->name != NULL)
   13223     return dp;
   13224   else
   13225     return get_valid_dis386 (dp, info);
   13226 }
   13227 
   13228 static void
   13229 get_sib (disassemble_info *info, int sizeflag)
   13230 {
   13231   /* If modrm.mod == 3, operand must be register.  */
   13232   if (need_modrm
   13233       && ((sizeflag & AFLAG) || address_mode == mode_64bit)
   13234       && modrm.mod != 3
   13235       && modrm.rm == 4)
   13236     {
   13237       FETCH_DATA (info, codep + 2);
   13238       sib.index = (codep [1] >> 3) & 7;
   13239       sib.scale = (codep [1] >> 6) & 3;
   13240       sib.base = codep [1] & 7;
   13241     }
   13242 }
   13243 
   13244 static int
   13245 print_insn (bfd_vma pc, disassemble_info *info)
   13246 {
   13247   const struct dis386 *dp;
   13248   int i;
   13249   char *op_txt[MAX_OPERANDS];
   13250   int needcomma;
   13251   int sizeflag, orig_sizeflag;
   13252   const char *p;
   13253   struct dis_private priv;
   13254   int prefix_length;
   13255 
   13256   priv.orig_sizeflag = AFLAG | DFLAG;
   13257   if ((info->mach & bfd_mach_i386_i386) != 0)
   13258     address_mode = mode_32bit;
   13259   else if (info->mach == bfd_mach_i386_i8086)
   13260     {
   13261       address_mode = mode_16bit;
   13262       priv.orig_sizeflag = 0;
   13263     }
   13264   else
   13265     address_mode = mode_64bit;
   13266 
   13267   if (intel_syntax == (char) -1)
   13268     intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
   13269 
   13270   for (p = info->disassembler_options; p != NULL; )
   13271     {
   13272       if (CONST_STRNEQ (p, "amd64"))
   13273 	isa64 = amd64;
   13274       else if (CONST_STRNEQ (p, "intel64"))
   13275 	isa64 = intel64;
   13276       else if (CONST_STRNEQ (p, "x86-64"))
   13277 	{
   13278 	  address_mode = mode_64bit;
   13279 	  priv.orig_sizeflag = AFLAG | DFLAG;
   13280 	}
   13281       else if (CONST_STRNEQ (p, "i386"))
   13282 	{
   13283 	  address_mode = mode_32bit;
   13284 	  priv.orig_sizeflag = AFLAG | DFLAG;
   13285 	}
   13286       else if (CONST_STRNEQ (p, "i8086"))
   13287 	{
   13288 	  address_mode = mode_16bit;
   13289 	  priv.orig_sizeflag = 0;
   13290 	}
   13291       else if (CONST_STRNEQ (p, "intel"))
   13292 	{
   13293 	  intel_syntax = 1;
   13294 	  if (CONST_STRNEQ (p + 5, "-mnemonic"))
   13295 	    intel_mnemonic = 1;
   13296 	}
   13297       else if (CONST_STRNEQ (p, "att"))
   13298 	{
   13299 	  intel_syntax = 0;
   13300 	  if (CONST_STRNEQ (p + 3, "-mnemonic"))
   13301 	    intel_mnemonic = 0;
   13302 	}
   13303       else if (CONST_STRNEQ (p, "addr"))
   13304 	{
   13305 	  if (address_mode == mode_64bit)
   13306 	    {
   13307 	      if (p[4] == '3' && p[5] == '2')
   13308 		priv.orig_sizeflag &= ~AFLAG;
   13309 	      else if (p[4] == '6' && p[5] == '4')
   13310 		priv.orig_sizeflag |= AFLAG;
   13311 	    }
   13312 	  else
   13313 	    {
   13314 	      if (p[4] == '1' && p[5] == '6')
   13315 		priv.orig_sizeflag &= ~AFLAG;
   13316 	      else if (p[4] == '3' && p[5] == '2')
   13317 		priv.orig_sizeflag |= AFLAG;
   13318 	    }
   13319 	}
   13320       else if (CONST_STRNEQ (p, "data"))
   13321 	{
   13322 	  if (p[4] == '1' && p[5] == '6')
   13323 	    priv.orig_sizeflag &= ~DFLAG;
   13324 	  else if (p[4] == '3' && p[5] == '2')
   13325 	    priv.orig_sizeflag |= DFLAG;
   13326 	}
   13327       else if (CONST_STRNEQ (p, "suffix"))
   13328 	priv.orig_sizeflag |= SUFFIX_ALWAYS;
   13329 
   13330       p = strchr (p, ',');
   13331       if (p != NULL)
   13332 	p++;
   13333     }
   13334 
   13335   if (address_mode == mode_64bit && sizeof (bfd_vma) < 8)
   13336     {
   13337       (*info->fprintf_func) (info->stream,
   13338 			     _("64-bit address is disabled"));
   13339       return -1;
   13340     }
   13341 
   13342   if (intel_syntax)
   13343     {
   13344       names64 = intel_names64;
   13345       names32 = intel_names32;
   13346       names16 = intel_names16;
   13347       names8 = intel_names8;
   13348       names8rex = intel_names8rex;
   13349       names_seg = intel_names_seg;
   13350       names_mm = intel_names_mm;
   13351       names_bnd = intel_names_bnd;
   13352       names_xmm = intel_names_xmm;
   13353       names_ymm = intel_names_ymm;
   13354       names_zmm = intel_names_zmm;
   13355       index64 = intel_index64;
   13356       index32 = intel_index32;
   13357       names_mask = intel_names_mask;
   13358       index16 = intel_index16;
   13359       open_char = '[';
   13360       close_char = ']';
   13361       separator_char = '+';
   13362       scale_char = '*';
   13363     }
   13364   else
   13365     {
   13366       names64 = att_names64;
   13367       names32 = att_names32;
   13368       names16 = att_names16;
   13369       names8 = att_names8;
   13370       names8rex = att_names8rex;
   13371       names_seg = att_names_seg;
   13372       names_mm = att_names_mm;
   13373       names_bnd = att_names_bnd;
   13374       names_xmm = att_names_xmm;
   13375       names_ymm = att_names_ymm;
   13376       names_zmm = att_names_zmm;
   13377       index64 = att_index64;
   13378       index32 = att_index32;
   13379       names_mask = att_names_mask;
   13380       index16 = att_index16;
   13381       open_char = '(';
   13382       close_char =  ')';
   13383       separator_char = ',';
   13384       scale_char = ',';
   13385     }
   13386 
   13387   /* The output looks better if we put 7 bytes on a line, since that
   13388      puts most long word instructions on a single line.  Use 8 bytes
   13389      for Intel L1OM.  */
   13390   if ((info->mach & bfd_mach_l1om) != 0)
   13391     info->bytes_per_line = 8;
   13392   else
   13393     info->bytes_per_line = 7;
   13394 
   13395   info->private_data = &priv;
   13396   priv.max_fetched = priv.the_buffer;
   13397   priv.insn_start = pc;
   13398 
   13399   obuf[0] = 0;
   13400   for (i = 0; i < MAX_OPERANDS; ++i)
   13401     {
   13402       op_out[i][0] = 0;
   13403       op_index[i] = -1;
   13404     }
   13405 
   13406   the_info = info;
   13407   start_pc = pc;
   13408   start_codep = priv.the_buffer;
   13409   codep = priv.the_buffer;
   13410 
   13411   if (OPCODES_SIGSETJMP (priv.bailout) != 0)
   13412     {
   13413       const char *name;
   13414 
   13415       /* Getting here means we tried for data but didn't get it.  That
   13416 	 means we have an incomplete instruction of some sort.  Just
   13417 	 print the first byte as a prefix or a .byte pseudo-op.  */
   13418       if (codep > priv.the_buffer)
   13419 	{
   13420 	  name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
   13421 	  if (name != NULL)
   13422 	    (*info->fprintf_func) (info->stream, "%s", name);
   13423 	  else
   13424 	    {
   13425 	      /* Just print the first byte as a .byte instruction.  */
   13426 	      (*info->fprintf_func) (info->stream, ".byte 0x%x",
   13427 				     (unsigned int) priv.the_buffer[0]);
   13428 	    }
   13429 
   13430 	  return 1;
   13431 	}
   13432 
   13433       return -1;
   13434     }
   13435 
   13436   obufp = obuf;
   13437   sizeflag = priv.orig_sizeflag;
   13438 
   13439   if (!ckprefix () || rex_used)
   13440     {
   13441       /* Too many prefixes or unused REX prefixes.  */
   13442       for (i = 0;
   13443 	   i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
   13444 	   i++)
   13445 	(*info->fprintf_func) (info->stream, "%s%s",
   13446 			       i == 0 ? "" : " ",
   13447 			       prefix_name (all_prefixes[i], sizeflag));
   13448       return i;
   13449     }
   13450 
   13451   insn_codep = codep;
   13452 
   13453   FETCH_DATA (info, codep + 1);
   13454   two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
   13455 
   13456   if (((prefixes & PREFIX_FWAIT)
   13457        && ((*codep < 0xd8) || (*codep > 0xdf))))
   13458     {
   13459       /* Handle prefixes before fwait.  */
   13460       for (i = 0; i < fwait_prefix && all_prefixes[i];
   13461 	   i++)
   13462 	(*info->fprintf_func) (info->stream, "%s ",
   13463 			       prefix_name (all_prefixes[i], sizeflag));
   13464       (*info->fprintf_func) (info->stream, "fwait");
   13465       return i + 1;
   13466     }
   13467 
   13468   if (*codep == 0x0f)
   13469     {
   13470       unsigned char threebyte;
   13471 
   13472       codep++;
   13473       FETCH_DATA (info, codep + 1);
   13474       threebyte = *codep;
   13475       dp = &dis386_twobyte[threebyte];
   13476       need_modrm = twobyte_has_modrm[*codep];
   13477       codep++;
   13478     }
   13479   else
   13480     {
   13481       dp = &dis386[*codep];
   13482       need_modrm = onebyte_has_modrm[*codep];
   13483       codep++;
   13484     }
   13485 
   13486   /* Save sizeflag for printing the extra prefixes later before updating
   13487      it for mnemonic and operand processing.  The prefix names depend
   13488      only on the address mode.  */
   13489   orig_sizeflag = sizeflag;
   13490   if (prefixes & PREFIX_ADDR)
   13491     sizeflag ^= AFLAG;
   13492   if ((prefixes & PREFIX_DATA))
   13493     sizeflag ^= DFLAG;
   13494 
   13495   end_codep = codep;
   13496   if (need_modrm)
   13497     {
   13498       FETCH_DATA (info, codep + 1);
   13499       modrm.mod = (*codep >> 6) & 3;
   13500       modrm.reg = (*codep >> 3) & 7;
   13501       modrm.rm = *codep & 7;
   13502     }
   13503 
   13504   need_vex = 0;
   13505   need_vex_reg = 0;
   13506   vex_w_done = 0;
   13507   vex.evex = 0;
   13508 
   13509   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
   13510     {
   13511       get_sib (info, sizeflag);
   13512       dofloat (sizeflag);
   13513     }
   13514   else
   13515     {
   13516       dp = get_valid_dis386 (dp, info);
   13517       if (dp != NULL && putop (dp->name, sizeflag) == 0)
   13518 	{
   13519 	  get_sib (info, sizeflag);
   13520 	  for (i = 0; i < MAX_OPERANDS; ++i)
   13521 	    {
   13522 	      obufp = op_out[i];
   13523 	      op_ad = MAX_OPERANDS - 1 - i;
   13524 	      if (dp->op[i].rtn)
   13525 		(*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
   13526 	      /* For EVEX instruction after the last operand masking
   13527 		 should be printed.  */
   13528 	      if (i == 0 && vex.evex)
   13529 		{
   13530 		  /* Don't print {%k0}.  */
   13531 		  if (vex.mask_register_specifier)
   13532 		    {
   13533 		      oappend ("{");
   13534 		      oappend (names_mask[vex.mask_register_specifier]);
   13535 		      oappend ("}");
   13536 		    }
   13537 		  if (vex.zeroing)
   13538 		    oappend ("{z}");
   13539 		}
   13540 	    }
   13541 	}
   13542     }
   13543 
   13544   /* Check if the REX prefix is used.  */
   13545   if (rex_ignored == 0 && (rex ^ rex_used) == 0 && last_rex_prefix >= 0)
   13546     all_prefixes[last_rex_prefix] = 0;
   13547 
   13548   /* Check if the SEG prefix is used.  */
   13549   if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
   13550 		   | PREFIX_FS | PREFIX_GS)) != 0
   13551       && (used_prefixes & active_seg_prefix) != 0)
   13552     all_prefixes[last_seg_prefix] = 0;
   13553 
   13554   /* Check if the ADDR prefix is used.  */
   13555   if ((prefixes & PREFIX_ADDR) != 0
   13556       && (used_prefixes & PREFIX_ADDR) != 0)
   13557     all_prefixes[last_addr_prefix] = 0;
   13558 
   13559   /* Check if the DATA prefix is used.  */
   13560   if ((prefixes & PREFIX_DATA) != 0
   13561       && (used_prefixes & PREFIX_DATA) != 0)
   13562     all_prefixes[last_data_prefix] = 0;
   13563 
   13564   /* Print the extra prefixes.  */
   13565   prefix_length = 0;
   13566   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
   13567     if (all_prefixes[i])
   13568       {
   13569 	const char *name;
   13570 	name = prefix_name (all_prefixes[i], orig_sizeflag);
   13571 	if (name == NULL)
   13572 	  abort ();
   13573 	prefix_length += strlen (name) + 1;
   13574 	(*info->fprintf_func) (info->stream, "%s ", name);
   13575       }
   13576 
   13577   /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
   13578      unused, opcode is invalid.  Since the PREFIX_DATA prefix may be
   13579      used by putop and MMX/SSE operand and may be overriden by the
   13580      PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
   13581      separately.  */
   13582   if (dp->prefix_requirement == PREFIX_OPCODE
   13583       && dp != &bad_opcode
   13584       && (((prefixes
   13585 	    & (PREFIX_REPZ | PREFIX_REPNZ)) != 0
   13586 	   && (used_prefixes
   13587 	       & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
   13588 	  || ((((prefixes
   13589 		 & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
   13590 		== PREFIX_DATA)
   13591 	       && (used_prefixes & PREFIX_DATA) == 0))))
   13592     {
   13593       (*info->fprintf_func) (info->stream, "(bad)");
   13594       return end_codep - priv.the_buffer;
   13595     }
   13596 
   13597   /* Check maximum code length.  */
   13598   if ((codep - start_codep) > MAX_CODE_LENGTH)
   13599     {
   13600       (*info->fprintf_func) (info->stream, "(bad)");
   13601       return MAX_CODE_LENGTH;
   13602     }
   13603 
   13604   obufp = mnemonicendp;
   13605   for (i = strlen (obuf) + prefix_length; i < 6; i++)
   13606     oappend (" ");
   13607   oappend (" ");
   13608   (*info->fprintf_func) (info->stream, "%s", obuf);
   13609 
   13610   /* The enter and bound instructions are printed with operands in the same
   13611      order as the intel book; everything else is printed in reverse order.  */
   13612   if (intel_syntax || two_source_ops)
   13613     {
   13614       bfd_vma riprel;
   13615 
   13616       for (i = 0; i < MAX_OPERANDS; ++i)
   13617 	op_txt[i] = op_out[i];
   13618 
   13619       if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding
   13620           && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL)
   13621 	{
   13622 	  op_txt[2] = op_out[3];
   13623 	  op_txt[3] = op_out[2];
   13624 	}
   13625 
   13626       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
   13627 	{
   13628 	  op_ad = op_index[i];
   13629 	  op_index[i] = op_index[MAX_OPERANDS - 1 - i];
   13630 	  op_index[MAX_OPERANDS - 1 - i] = op_ad;
   13631 	  riprel = op_riprel[i];
   13632 	  op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
   13633 	  op_riprel[MAX_OPERANDS - 1 - i] = riprel;
   13634 	}
   13635     }
   13636   else
   13637     {
   13638       for (i = 0; i < MAX_OPERANDS; ++i)
   13639 	op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
   13640     }
   13641 
   13642   needcomma = 0;
   13643   for (i = 0; i < MAX_OPERANDS; ++i)
   13644     if (*op_txt[i])
   13645       {
   13646 	if (needcomma)
   13647 	  (*info->fprintf_func) (info->stream, ",");
   13648 	if (op_index[i] != -1 && !op_riprel[i])
   13649 	  (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
   13650 	else
   13651 	  (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
   13652 	needcomma = 1;
   13653       }
   13654 
   13655   for (i = 0; i < MAX_OPERANDS; i++)
   13656     if (op_index[i] != -1 && op_riprel[i])
   13657       {
   13658 	(*info->fprintf_func) (info->stream, "        # ");
   13659 	(*info->print_address_func) ((bfd_vma) (start_pc + (codep - start_codep)
   13660 						+ op_address[op_index[i]]), info);
   13661 	break;
   13662       }
   13663   return codep - priv.the_buffer;
   13664 }
   13665 
   13666 static const char *float_mem[] = {
   13667   /* d8 */
   13668   "fadd{s|}",
   13669   "fmul{s|}",
   13670   "fcom{s|}",
   13671   "fcomp{s|}",
   13672   "fsub{s|}",
   13673   "fsubr{s|}",
   13674   "fdiv{s|}",
   13675   "fdivr{s|}",
   13676   /* d9 */
   13677   "fld{s|}",
   13678   "(bad)",
   13679   "fst{s|}",
   13680   "fstp{s|}",
   13681   "fldenvIC",
   13682   "fldcw",
   13683   "fNstenvIC",
   13684   "fNstcw",
   13685   /* da */
   13686   "fiadd{l|}",
   13687   "fimul{l|}",
   13688   "ficom{l|}",
   13689   "ficomp{l|}",
   13690   "fisub{l|}",
   13691   "fisubr{l|}",
   13692   "fidiv{l|}",
   13693   "fidivr{l|}",
   13694   /* db */
   13695   "fild{l|}",
   13696   "fisttp{l|}",
   13697   "fist{l|}",
   13698   "fistp{l|}",
   13699   "(bad)",
   13700   "fld{t||t|}",
   13701   "(bad)",
   13702   "fstp{t||t|}",
   13703   /* dc */
   13704   "fadd{l|}",
   13705   "fmul{l|}",
   13706   "fcom{l|}",
   13707   "fcomp{l|}",
   13708   "fsub{l|}",
   13709   "fsubr{l|}",
   13710   "fdiv{l|}",
   13711   "fdivr{l|}",
   13712   /* dd */
   13713   "fld{l|}",
   13714   "fisttp{ll|}",
   13715   "fst{l||}",
   13716   "fstp{l|}",
   13717   "frstorIC",
   13718   "(bad)",
   13719   "fNsaveIC",
   13720   "fNstsw",
   13721   /* de */
   13722   "fiadd",
   13723   "fimul",
   13724   "ficom",
   13725   "ficomp",
   13726   "fisub",
   13727   "fisubr",
   13728   "fidiv",
   13729   "fidivr",
   13730   /* df */
   13731   "fild",
   13732   "fisttp",
   13733   "fist",
   13734   "fistp",
   13735   "fbld",
   13736   "fild{ll|}",
   13737   "fbstp",
   13738   "fistp{ll|}",
   13739 };
   13740 
   13741 static const unsigned char float_mem_mode[] = {
   13742   /* d8 */
   13743   d_mode,
   13744   d_mode,
   13745   d_mode,
   13746   d_mode,
   13747   d_mode,
   13748   d_mode,
   13749   d_mode,
   13750   d_mode,
   13751   /* d9 */
   13752   d_mode,
   13753   0,
   13754   d_mode,
   13755   d_mode,
   13756   0,
   13757   w_mode,
   13758   0,
   13759   w_mode,
   13760   /* da */
   13761   d_mode,
   13762   d_mode,
   13763   d_mode,
   13764   d_mode,
   13765   d_mode,
   13766   d_mode,
   13767   d_mode,
   13768   d_mode,
   13769   /* db */
   13770   d_mode,
   13771   d_mode,
   13772   d_mode,
   13773   d_mode,
   13774   0,
   13775   t_mode,
   13776   0,
   13777   t_mode,
   13778   /* dc */
   13779   q_mode,
   13780   q_mode,
   13781   q_mode,
   13782   q_mode,
   13783   q_mode,
   13784   q_mode,
   13785   q_mode,
   13786   q_mode,
   13787   /* dd */
   13788   q_mode,
   13789   q_mode,
   13790   q_mode,
   13791   q_mode,
   13792   0,
   13793   0,
   13794   0,
   13795   w_mode,
   13796   /* de */
   13797   w_mode,
   13798   w_mode,
   13799   w_mode,
   13800   w_mode,
   13801   w_mode,
   13802   w_mode,
   13803   w_mode,
   13804   w_mode,
   13805   /* df */
   13806   w_mode,
   13807   w_mode,
   13808   w_mode,
   13809   w_mode,
   13810   t_mode,
   13811   q_mode,
   13812   t_mode,
   13813   q_mode
   13814 };
   13815 
   13816 #define ST { OP_ST, 0 }
   13817 #define STi { OP_STi, 0 }
   13818 
   13819 #define FGRPd9_2 NULL, { { NULL, 0 } }, 0
   13820 #define FGRPd9_4 NULL, { { NULL, 1 } }, 0
   13821 #define FGRPd9_5 NULL, { { NULL, 2 } }, 0
   13822 #define FGRPd9_6 NULL, { { NULL, 3 } }, 0
   13823 #define FGRPd9_7 NULL, { { NULL, 4 } }, 0
   13824 #define FGRPda_5 NULL, { { NULL, 5 } }, 0
   13825 #define FGRPdb_4 NULL, { { NULL, 6 } }, 0
   13826 #define FGRPde_3 NULL, { { NULL, 7 } }, 0
   13827 #define FGRPdf_4 NULL, { { NULL, 8 } }, 0
   13828 
   13829 static const struct dis386 float_reg[][8] = {
   13830   /* d8 */
   13831   {
   13832     { "fadd",	{ ST, STi }, 0 },
   13833     { "fmul",	{ ST, STi }, 0 },
   13834     { "fcom",	{ STi }, 0 },
   13835     { "fcomp",	{ STi }, 0 },
   13836     { "fsub",	{ ST, STi }, 0 },
   13837     { "fsubr",	{ ST, STi }, 0 },
   13838     { "fdiv",	{ ST, STi }, 0 },
   13839     { "fdivr",	{ ST, STi }, 0 },
   13840   },
   13841   /* d9 */
   13842   {
   13843     { "fld",	{ STi }, 0 },
   13844     { "fxch",	{ STi }, 0 },
   13845     { FGRPd9_2 },
   13846     { Bad_Opcode },
   13847     { FGRPd9_4 },
   13848     { FGRPd9_5 },
   13849     { FGRPd9_6 },
   13850     { FGRPd9_7 },
   13851   },
   13852   /* da */
   13853   {
   13854     { "fcmovb",	{ ST, STi }, 0 },
   13855     { "fcmove",	{ ST, STi }, 0 },
   13856     { "fcmovbe",{ ST, STi }, 0 },
   13857     { "fcmovu",	{ ST, STi }, 0 },
   13858     { Bad_Opcode },
   13859     { FGRPda_5 },
   13860     { Bad_Opcode },
   13861     { Bad_Opcode },
   13862   },
   13863   /* db */
   13864   {
   13865     { "fcmovnb",{ ST, STi }, 0 },
   13866     { "fcmovne",{ ST, STi }, 0 },
   13867     { "fcmovnbe",{ ST, STi }, 0 },
   13868     { "fcmovnu",{ ST, STi }, 0 },
   13869     { FGRPdb_4 },
   13870     { "fucomi",	{ ST, STi }, 0 },
   13871     { "fcomi",	{ ST, STi }, 0 },
   13872     { Bad_Opcode },
   13873   },
   13874   /* dc */
   13875   {
   13876     { "fadd",	{ STi, ST }, 0 },
   13877     { "fmul",	{ STi, ST }, 0 },
   13878     { Bad_Opcode },
   13879     { Bad_Opcode },
   13880     { "fsub!M",	{ STi, ST }, 0 },
   13881     { "fsubM",	{ STi, ST }, 0 },
   13882     { "fdiv!M",	{ STi, ST }, 0 },
   13883     { "fdivM",	{ STi, ST }, 0 },
   13884   },
   13885   /* dd */
   13886   {
   13887     { "ffree",	{ STi }, 0 },
   13888     { Bad_Opcode },
   13889     { "fst",	{ STi }, 0 },
   13890     { "fstp",	{ STi }, 0 },
   13891     { "fucom",	{ STi }, 0 },
   13892     { "fucomp",	{ STi }, 0 },
   13893     { Bad_Opcode },
   13894     { Bad_Opcode },
   13895   },
   13896   /* de */
   13897   {
   13898     { "faddp",	{ STi, ST }, 0 },
   13899     { "fmulp",	{ STi, ST }, 0 },
   13900     { Bad_Opcode },
   13901     { FGRPde_3 },
   13902     { "fsub!Mp", { STi, ST }, 0 },
   13903     { "fsubMp",	{ STi, ST }, 0 },
   13904     { "fdiv!Mp", { STi, ST }, 0 },
   13905     { "fdivMp",	{ STi, ST }, 0 },
   13906   },
   13907   /* df */
   13908   {
   13909     { "ffreep",	{ STi }, 0 },
   13910     { Bad_Opcode },
   13911     { Bad_Opcode },
   13912     { Bad_Opcode },
   13913     { FGRPdf_4 },
   13914     { "fucomip", { ST, STi }, 0 },
   13915     { "fcomip", { ST, STi }, 0 },
   13916     { Bad_Opcode },
   13917   },
   13918 };
   13919 
   13920 static char *fgrps[][8] = {
   13921   /* d9_2  0 */
   13922   {
   13923     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
   13924   },
   13925 
   13926   /* d9_4  1 */
   13927   {
   13928     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
   13929   },
   13930 
   13931   /* d9_5  2 */
   13932   {
   13933     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
   13934   },
   13935 
   13936   /* d9_6  3 */
   13937   {
   13938     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
   13939   },
   13940 
   13941   /* d9_7  4 */
   13942   {
   13943     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
   13944   },
   13945 
   13946   /* da_5  5 */
   13947   {
   13948     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
   13949   },
   13950 
   13951   /* db_4  6 */
   13952   {
   13953     "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
   13954     "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
   13955   },
   13956 
   13957   /* de_3  7 */
   13958   {
   13959     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
   13960   },
   13961 
   13962   /* df_4  8 */
   13963   {
   13964     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
   13965   },
   13966 };
   13967 
   13968 static void
   13969 swap_operand (void)
   13970 {
   13971   mnemonicendp[0] = '.';
   13972   mnemonicendp[1] = 's';
   13973   mnemonicendp += 2;
   13974 }
   13975 
   13976 static void
   13977 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
   13978 	       int sizeflag ATTRIBUTE_UNUSED)
   13979 {
   13980   /* Skip mod/rm byte.  */
   13981   MODRM_CHECK;
   13982   codep++;
   13983 }
   13984 
   13985 static void
   13986 dofloat (int sizeflag)
   13987 {
   13988   const struct dis386 *dp;
   13989   unsigned char floatop;
   13990 
   13991   floatop = codep[-1];
   13992 
   13993   if (modrm.mod != 3)
   13994     {
   13995       int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
   13996 
   13997       putop (float_mem[fp_indx], sizeflag);
   13998       obufp = op_out[0];
   13999       op_ad = 2;
   14000       OP_E (float_mem_mode[fp_indx], sizeflag);
   14001       return;
   14002     }
   14003   /* Skip mod/rm byte.  */
   14004   MODRM_CHECK;
   14005   codep++;
   14006 
   14007   dp = &float_reg[floatop - 0xd8][modrm.reg];
   14008   if (dp->name == NULL)
   14009     {
   14010       putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
   14011 
   14012       /* Instruction fnstsw is only one with strange arg.  */
   14013       if (floatop == 0xdf && codep[-1] == 0xe0)
   14014 	strcpy (op_out[0], names16[0]);
   14015     }
   14016   else
   14017     {
   14018       putop (dp->name, sizeflag);
   14019 
   14020       obufp = op_out[0];
   14021       op_ad = 2;
   14022       if (dp->op[0].rtn)
   14023 	(*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
   14024 
   14025       obufp = op_out[1];
   14026       op_ad = 1;
   14027       if (dp->op[1].rtn)
   14028 	(*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
   14029     }
   14030 }
   14031 
   14032 /* Like oappend (below), but S is a string starting with '%'.
   14033    In Intel syntax, the '%' is elided.  */
   14034 static void
   14035 oappend_maybe_intel (const char *s)
   14036 {
   14037   oappend (s + intel_syntax);
   14038 }
   14039 
   14040 static void
   14041 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
   14042 {
   14043   oappend_maybe_intel ("%st");
   14044 }
   14045 
   14046 static void
   14047 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
   14048 {
   14049   sprintf (scratchbuf, "%%st(%d)", modrm.rm);
   14050   oappend_maybe_intel (scratchbuf);
   14051 }
   14052 
   14053 /* Capital letters in template are macros.  */
   14054 static int
   14055 putop (const char *in_template, int sizeflag)
   14056 {
   14057   const char *p;
   14058   int alt = 0;
   14059   int cond = 1;
   14060   unsigned int l = 0, len = 1;
   14061   char last[4];
   14062 
   14063 #define SAVE_LAST(c)			\
   14064   if (l < len && l < sizeof (last))	\
   14065     last[l++] = c;			\
   14066   else					\
   14067     abort ();
   14068 
   14069   for (p = in_template; *p; p++)
   14070     {
   14071       switch (*p)
   14072 	{
   14073 	default:
   14074 	  *obufp++ = *p;
   14075 	  break;
   14076 	case '%':
   14077 	  len++;
   14078 	  break;
   14079 	case '!':
   14080 	  cond = 0;
   14081 	  break;
   14082 	case '{':
   14083 	  alt = 0;
   14084 	  if (intel_syntax)
   14085 	    {
   14086 	      while (*++p != '|')
   14087 		if (*p == '}' || *p == '\0')
   14088 		  abort ();
   14089 	    }
   14090 	  /* Fall through.  */
   14091 	case 'I':
   14092 	  alt = 1;
   14093 	  continue;
   14094 	case '|':
   14095 	  while (*++p != '}')
   14096 	    {
   14097 	      if (*p == '\0')
   14098 		abort ();
   14099 	    }
   14100 	  break;
   14101 	case '}':
   14102 	  break;
   14103 	case 'A':
   14104 	  if (intel_syntax)
   14105 	    break;
   14106 	  if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
   14107 	    *obufp++ = 'b';
   14108 	  break;
   14109 	case 'B':
   14110 	  if (l == 0 && len == 1)
   14111 	    {
   14112 case_B:
   14113 	      if (intel_syntax)
   14114 		break;
   14115 	      if (sizeflag & SUFFIX_ALWAYS)
   14116 		*obufp++ = 'b';
   14117 	    }
   14118 	  else
   14119 	    {
   14120 	      if (l != 1
   14121 		  || len != 2
   14122 		  || last[0] != 'L')
   14123 		{
   14124 		  SAVE_LAST (*p);
   14125 		  break;
   14126 		}
   14127 
   14128 	      if (address_mode == mode_64bit
   14129 		  && !(prefixes & PREFIX_ADDR))
   14130 		{
   14131 		  *obufp++ = 'a';
   14132 		  *obufp++ = 'b';
   14133 		  *obufp++ = 's';
   14134 		}
   14135 
   14136 	      goto case_B;
   14137 	    }
   14138 	  break;
   14139 	case 'C':
   14140 	  if (intel_syntax && !alt)
   14141 	    break;
   14142 	  if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
   14143 	    {
   14144 	      if (sizeflag & DFLAG)
   14145 		*obufp++ = intel_syntax ? 'd' : 'l';
   14146 	      else
   14147 		*obufp++ = intel_syntax ? 'w' : 's';
   14148 	      used_prefixes |= (prefixes & PREFIX_DATA);
   14149 	    }
   14150 	  break;
   14151 	case 'D':
   14152 	  if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
   14153 	    break;
   14154 	  USED_REX (REX_W);
   14155 	  if (modrm.mod == 3)
   14156 	    {
   14157 	      if (rex & REX_W)
   14158 		*obufp++ = 'q';
   14159 	      else
   14160 		{
   14161 		  if (sizeflag & DFLAG)
   14162 		    *obufp++ = intel_syntax ? 'd' : 'l';
   14163 		  else
   14164 		    *obufp++ = 'w';
   14165 		  used_prefixes |= (prefixes & PREFIX_DATA);
   14166 		}
   14167 	    }
   14168 	  else
   14169 	    *obufp++ = 'w';
   14170 	  break;
   14171 	case 'E':		/* For jcxz/jecxz */
   14172 	  if (address_mode == mode_64bit)
   14173 	    {
   14174 	      if (sizeflag & AFLAG)
   14175 		*obufp++ = 'r';
   14176 	      else
   14177 		*obufp++ = 'e';
   14178 	    }
   14179 	  else
   14180 	    if (sizeflag & AFLAG)
   14181 	      *obufp++ = 'e';
   14182 	  used_prefixes |= (prefixes & PREFIX_ADDR);
   14183 	  break;
   14184 	case 'F':
   14185 	  if (intel_syntax)
   14186 	    break;
   14187 	  if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
   14188 	    {
   14189 	      if (sizeflag & AFLAG)
   14190 		*obufp++ = address_mode == mode_64bit ? 'q' : 'l';
   14191 	      else
   14192 		*obufp++ = address_mode == mode_64bit ? 'l' : 'w';
   14193 	      used_prefixes |= (prefixes & PREFIX_ADDR);
   14194 	    }
   14195 	  break;
   14196 	case 'G':
   14197 	  if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
   14198 	    break;
   14199 	  if ((rex & REX_W) || (sizeflag & DFLAG))
   14200 	    *obufp++ = 'l';
   14201 	  else
   14202 	    *obufp++ = 'w';
   14203 	  if (!(rex & REX_W))
   14204 	    used_prefixes |= (prefixes & PREFIX_DATA);
   14205 	  break;
   14206 	case 'H':
   14207 	  if (intel_syntax)
   14208 	    break;
   14209 	  if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
   14210 	      || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
   14211 	    {
   14212 	      used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
   14213 	      *obufp++ = ',';
   14214 	      *obufp++ = 'p';
   14215 	      if (prefixes & PREFIX_DS)
   14216 		*obufp++ = 't';
   14217 	      else
   14218 		*obufp++ = 'n';
   14219 	    }
   14220 	  break;
   14221 	case 'J':
   14222 	  if (intel_syntax)
   14223 	    break;
   14224 	  *obufp++ = 'l';
   14225 	  break;
   14226 	case 'K':
   14227 	  USED_REX (REX_W);
   14228 	  if (rex & REX_W)
   14229 	    *obufp++ = 'q';
   14230 	  else
   14231 	    *obufp++ = 'd';
   14232 	  break;
   14233 	case 'Z':
   14234 	  if (l != 0 || len != 1)
   14235 	    {
   14236 	      if (l != 1 || len != 2 || last[0] != 'X')
   14237 		{
   14238 		  SAVE_LAST (*p);
   14239 		  break;
   14240 		}
   14241 	      if (!need_vex || !vex.evex)
   14242 		abort ();
   14243 	      if (intel_syntax
   14244 		  || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
   14245 		break;
   14246 	      switch (vex.length)
   14247 		{
   14248 		case 128:
   14249 		  *obufp++ = 'x';
   14250 		  break;
   14251 		case 256:
   14252 		  *obufp++ = 'y';
   14253 		  break;
   14254 		case 512:
   14255 		  *obufp++ = 'z';
   14256 		  break;
   14257 		default:
   14258 		  abort ();
   14259 		}
   14260 	      break;
   14261 	    }
   14262 	  if (intel_syntax)
   14263 	    break;
   14264 	  if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
   14265 	    {
   14266 	      *obufp++ = 'q';
   14267 	      break;
   14268 	    }
   14269 	  /* Fall through.  */
   14270 	  goto case_L;
   14271 	case 'L':
   14272 	  if (l != 0 || len != 1)
   14273 	    {
   14274 	      SAVE_LAST (*p);
   14275 	      break;
   14276 	    }
   14277 case_L:
   14278 	  if (intel_syntax)
   14279 	    break;
   14280 	  if (sizeflag & SUFFIX_ALWAYS)
   14281 	    *obufp++ = 'l';
   14282 	  break;
   14283 	case 'M':
   14284 	  if (intel_mnemonic != cond)
   14285 	    *obufp++ = 'r';
   14286 	  break;
   14287 	case 'N':
   14288 	  if ((prefixes & PREFIX_FWAIT) == 0)
   14289 	    *obufp++ = 'n';
   14290 	  else
   14291 	    used_prefixes |= PREFIX_FWAIT;
   14292 	  break;
   14293 	case 'O':
   14294 	  USED_REX (REX_W);
   14295 	  if (rex & REX_W)
   14296 	    *obufp++ = 'o';
   14297 	  else if (intel_syntax && (sizeflag & DFLAG))
   14298 	    *obufp++ = 'q';
   14299 	  else
   14300 	    *obufp++ = 'd';
   14301 	  if (!(rex & REX_W))
   14302 	    used_prefixes |= (prefixes & PREFIX_DATA);
   14303 	  break;
   14304 	case '&':
   14305 	  if (!intel_syntax
   14306 	      && address_mode == mode_64bit
   14307 	      && isa64 == intel64)
   14308 	    {
   14309 	      *obufp++ = 'q';
   14310 	      break;
   14311 	    }
   14312 	  /* Fall through.  */
   14313 	case 'T':
   14314 	  if (!intel_syntax
   14315 	      && address_mode == mode_64bit
   14316 	      && ((sizeflag & DFLAG) || (rex & REX_W)))
   14317 	    {
   14318 	      *obufp++ = 'q';
   14319 	      break;
   14320 	    }
   14321 	  /* Fall through.  */
   14322 	  goto case_P;
   14323 	case 'P':
   14324 	  if (l == 0 && len == 1)
   14325 	    {
   14326 case_P:
   14327 	      if (intel_syntax)
   14328 		{
   14329 		  if ((rex & REX_W) == 0
   14330 		      && (prefixes & PREFIX_DATA))
   14331 		    {
   14332 		      if ((sizeflag & DFLAG) == 0)
   14333 			*obufp++ = 'w';
   14334 		      used_prefixes |= (prefixes & PREFIX_DATA);
   14335 		    }
   14336 		  break;
   14337 		}
   14338 	      if ((prefixes & PREFIX_DATA)
   14339 		  || (rex & REX_W)
   14340 		  || (sizeflag & SUFFIX_ALWAYS))
   14341 		{
   14342 		  USED_REX (REX_W);
   14343 		  if (rex & REX_W)
   14344 		    *obufp++ = 'q';
   14345 		  else
   14346 		    {
   14347 		      if (sizeflag & DFLAG)
   14348 			*obufp++ = 'l';
   14349 		      else
   14350 			*obufp++ = 'w';
   14351 		      used_prefixes |= (prefixes & PREFIX_DATA);
   14352 		    }
   14353 		}
   14354 	    }
   14355 	  else
   14356 	    {
   14357 	      if (l != 1 || len != 2 || last[0] != 'L')
   14358 		{
   14359 		  SAVE_LAST (*p);
   14360 		  break;
   14361 		}
   14362 
   14363 	      if ((prefixes & PREFIX_DATA)
   14364 		  || (rex & REX_W)
   14365 		  || (sizeflag & SUFFIX_ALWAYS))
   14366 		{
   14367 		  USED_REX (REX_W);
   14368 		  if (rex & REX_W)
   14369 		    *obufp++ = 'q';
   14370 		  else
   14371 		    {
   14372 		      if (sizeflag & DFLAG)
   14373 			*obufp++ = intel_syntax ? 'd' : 'l';
   14374 		      else
   14375 			*obufp++ = 'w';
   14376 		      used_prefixes |= (prefixes & PREFIX_DATA);
   14377 		    }
   14378 		}
   14379 	    }
   14380 	  break;
   14381 	case 'U':
   14382 	  if (intel_syntax)
   14383 	    break;
   14384 	  if (address_mode == mode_64bit
   14385 	      && ((sizeflag & DFLAG) || (rex & REX_W)))
   14386 	    {
   14387 	      if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
   14388 		*obufp++ = 'q';
   14389 	      break;
   14390 	    }
   14391 	  /* Fall through.  */
   14392 	  goto case_Q;
   14393 	case 'Q':
   14394 	  if (l == 0 && len == 1)
   14395 	    {
   14396 case_Q:
   14397 	      if (intel_syntax && !alt)
   14398 		break;
   14399 	      USED_REX (REX_W);
   14400 	      if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
   14401 		{
   14402 		  if (rex & REX_W)
   14403 		    *obufp++ = 'q';
   14404 		  else
   14405 		    {
   14406 		      if (sizeflag & DFLAG)
   14407 			*obufp++ = intel_syntax ? 'd' : 'l';
   14408 		      else
   14409 			*obufp++ = 'w';
   14410 		      used_prefixes |= (prefixes & PREFIX_DATA);
   14411 		    }
   14412 		}
   14413 	    }
   14414 	  else
   14415 	    {
   14416 	      if (l != 1 || len != 2 || last[0] != 'L')
   14417 		{
   14418 		  SAVE_LAST (*p);
   14419 		  break;
   14420 		}
   14421 	      if (intel_syntax
   14422 		  || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
   14423 		break;
   14424 	      if ((rex & REX_W))
   14425 		{
   14426 		  USED_REX (REX_W);
   14427 		  *obufp++ = 'q';
   14428 		}
   14429 	      else
   14430 		*obufp++ = 'l';
   14431 	    }
   14432 	  break;
   14433 	case 'R':
   14434 	  USED_REX (REX_W);
   14435 	  if (rex & REX_W)
   14436 	    *obufp++ = 'q';
   14437 	  else if (sizeflag & DFLAG)
   14438 	    {
   14439 	      if (intel_syntax)
   14440 		  *obufp++ = 'd';
   14441 	      else
   14442 		  *obufp++ = 'l';
   14443 	    }
   14444 	  else
   14445 	    *obufp++ = 'w';
   14446 	  if (intel_syntax && !p[1]
   14447 	      && ((rex & REX_W) || (sizeflag & DFLAG)))
   14448 	    *obufp++ = 'e';
   14449 	  if (!(rex & REX_W))
   14450 	    used_prefixes |= (prefixes & PREFIX_DATA);
   14451 	  break;
   14452 	case 'V':
   14453 	  if (l == 0 && len == 1)
   14454 	    {
   14455 	      if (intel_syntax)
   14456 		break;
   14457 	      if (address_mode == mode_64bit
   14458 		  && ((sizeflag & DFLAG) || (rex & REX_W)))
   14459 		{
   14460 		  if (sizeflag & SUFFIX_ALWAYS)
   14461 		    *obufp++ = 'q';
   14462 		  break;
   14463 		}
   14464 	    }
   14465 	  else
   14466 	    {
   14467 	      if (l != 1
   14468 		  || len != 2
   14469 		  || last[0] != 'L')
   14470 		{
   14471 		  SAVE_LAST (*p);
   14472 		  break;
   14473 		}
   14474 
   14475 	      if (rex & REX_W)
   14476 		{
   14477 		  *obufp++ = 'a';
   14478 		  *obufp++ = 'b';
   14479 		  *obufp++ = 's';
   14480 		}
   14481 	    }
   14482 	  /* Fall through.  */
   14483 	  goto case_S;
   14484 	case 'S':
   14485 	  if (l == 0 && len == 1)
   14486 	    {
   14487 case_S:
   14488 	      if (intel_syntax)
   14489 		break;
   14490 	      if (sizeflag & SUFFIX_ALWAYS)
   14491 		{
   14492 		  if (rex & REX_W)
   14493 		    *obufp++ = 'q';
   14494 		  else
   14495 		    {
   14496 		      if (sizeflag & DFLAG)
   14497 			*obufp++ = 'l';
   14498 		      else
   14499 			*obufp++ = 'w';
   14500 		      used_prefixes |= (prefixes & PREFIX_DATA);
   14501 		    }
   14502 		}
   14503 	    }
   14504 	  else
   14505 	    {
   14506 	      if (l != 1
   14507 		  || len != 2
   14508 		  || last[0] != 'L')
   14509 		{
   14510 		  SAVE_LAST (*p);
   14511 		  break;
   14512 		}
   14513 
   14514 	      if (address_mode == mode_64bit
   14515 		  && !(prefixes & PREFIX_ADDR))
   14516 		{
   14517 		  *obufp++ = 'a';
   14518 		  *obufp++ = 'b';
   14519 		  *obufp++ = 's';
   14520 		}
   14521 
   14522 	      goto case_S;
   14523 	    }
   14524 	  break;
   14525 	case 'X':
   14526 	  if (l != 0 || len != 1)
   14527 	    {
   14528 	      SAVE_LAST (*p);
   14529 	      break;
   14530 	    }
   14531 	  if (need_vex && vex.prefix)
   14532 	    {
   14533 	      if (vex.prefix == DATA_PREFIX_OPCODE)
   14534 		*obufp++ = 'd';
   14535 	      else
   14536 		*obufp++ = 's';
   14537 	    }
   14538 	  else
   14539 	    {
   14540 	      if (prefixes & PREFIX_DATA)
   14541 		*obufp++ = 'd';
   14542 	      else
   14543 		*obufp++ = 's';
   14544 	      used_prefixes |= (prefixes & PREFIX_DATA);
   14545 	    }
   14546 	  break;
   14547 	case 'Y':
   14548 	  if (l == 0 && len == 1)
   14549 	    {
   14550 	      if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
   14551 		break;
   14552 	      if (rex & REX_W)
   14553 		{
   14554 		  USED_REX (REX_W);
   14555 		  *obufp++ = 'q';
   14556 		}
   14557 	      break;
   14558 	    }
   14559 	  else
   14560 	    {
   14561 	      if (l != 1 || len != 2 || last[0] != 'X')
   14562 		{
   14563 		  SAVE_LAST (*p);
   14564 		  break;
   14565 		}
   14566 	      if (!need_vex)
   14567 		abort ();
   14568 	      if (intel_syntax
   14569 		  || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
   14570 		break;
   14571 	      switch (vex.length)
   14572 		{
   14573 		case 128:
   14574 		  *obufp++ = 'x';
   14575 		  break;
   14576 		case 256:
   14577 		  *obufp++ = 'y';
   14578 		  break;
   14579 		case 512:
   14580 		  if (!vex.evex)
   14581 		default:
   14582 		    abort ();
   14583 		}
   14584 	    }
   14585 	  break;
   14586 	case 'W':
   14587 	  if (l == 0 && len == 1)
   14588 	    {
   14589 	      /* operand size flag for cwtl, cbtw */
   14590 	      USED_REX (REX_W);
   14591 	      if (rex & REX_W)
   14592 		{
   14593 		  if (intel_syntax)
   14594 		    *obufp++ = 'd';
   14595 		  else
   14596 		    *obufp++ = 'l';
   14597 		}
   14598 	      else if (sizeflag & DFLAG)
   14599 		*obufp++ = 'w';
   14600 	      else
   14601 		*obufp++ = 'b';
   14602 	      if (!(rex & REX_W))
   14603 		used_prefixes |= (prefixes & PREFIX_DATA);
   14604 	    }
   14605 	  else
   14606 	    {
   14607 	      if (l != 1
   14608 		  || len != 2
   14609 		  || (last[0] != 'X'
   14610 		      && last[0] != 'L'))
   14611 		{
   14612 		  SAVE_LAST (*p);
   14613 		  break;
   14614 		}
   14615 	      if (!need_vex)
   14616 		abort ();
   14617 	      if (last[0] == 'X')
   14618 		*obufp++ = vex.w ? 'd': 's';
   14619 	      else
   14620 		*obufp++ = vex.w ? 'q': 'd';
   14621 	    }
   14622 	  break;
   14623 	case '^':
   14624 	  if (intel_syntax)
   14625 	    break;
   14626 	  if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
   14627 	    {
   14628 	      if (sizeflag & DFLAG)
   14629 		*obufp++ = 'l';
   14630 	      else
   14631 		*obufp++ = 'w';
   14632 	      used_prefixes |= (prefixes & PREFIX_DATA);
   14633 	    }
   14634 	  break;
   14635 	case '@':
   14636 	  if (intel_syntax)
   14637 	    break;
   14638 	  if (address_mode == mode_64bit
   14639 	      && (isa64 == intel64
   14640 		  || ((sizeflag & DFLAG) || (rex & REX_W))))
   14641 	      *obufp++ = 'q';
   14642 	  else if ((prefixes & PREFIX_DATA))
   14643 	    {
   14644 	      if (!(sizeflag & DFLAG))
   14645 		*obufp++ = 'w';
   14646 	      used_prefixes |= (prefixes & PREFIX_DATA);
   14647 	    }
   14648 	  break;
   14649 	}
   14650       alt = 0;
   14651     }
   14652   *obufp = 0;
   14653   mnemonicendp = obufp;
   14654   return 0;
   14655 }
   14656 
   14657 static void
   14658 oappend (const char *s)
   14659 {
   14660   obufp = stpcpy (obufp, s);
   14661 }
   14662 
   14663 static void
   14664 append_seg (void)
   14665 {
   14666   /* Only print the active segment register.  */
   14667   if (!active_seg_prefix)
   14668     return;
   14669 
   14670   used_prefixes |= active_seg_prefix;
   14671   switch (active_seg_prefix)
   14672     {
   14673     case PREFIX_CS:
   14674       oappend_maybe_intel ("%cs:");
   14675       break;
   14676     case PREFIX_DS:
   14677       oappend_maybe_intel ("%ds:");
   14678       break;
   14679     case PREFIX_SS:
   14680       oappend_maybe_intel ("%ss:");
   14681       break;
   14682     case PREFIX_ES:
   14683       oappend_maybe_intel ("%es:");
   14684       break;
   14685     case PREFIX_FS:
   14686       oappend_maybe_intel ("%fs:");
   14687       break;
   14688     case PREFIX_GS:
   14689       oappend_maybe_intel ("%gs:");
   14690       break;
   14691     default:
   14692       break;
   14693     }
   14694 }
   14695 
   14696 static void
   14697 OP_indirE (int bytemode, int sizeflag)
   14698 {
   14699   if (!intel_syntax)
   14700     oappend ("*");
   14701   OP_E (bytemode, sizeflag);
   14702 }
   14703 
   14704 static void
   14705 print_operand_value (char *buf, int hex, bfd_vma disp)
   14706 {
   14707   if (address_mode == mode_64bit)
   14708     {
   14709       if (hex)
   14710 	{
   14711 	  char tmp[30];
   14712 	  int i;
   14713 	  buf[0] = '0';
   14714 	  buf[1] = 'x';
   14715 	  sprintf_vma (tmp, disp);
   14716 	  for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
   14717 	  strcpy (buf + 2, tmp + i);
   14718 	}
   14719       else
   14720 	{
   14721 	  bfd_signed_vma v = disp;
   14722 	  char tmp[30];
   14723 	  int i;
   14724 	  if (v < 0)
   14725 	    {
   14726 	      *(buf++) = '-';
   14727 	      v = -disp;
   14728 	      /* Check for possible overflow on 0x8000000000000000.  */
   14729 	      if (v < 0)
   14730 		{
   14731 		  strcpy (buf, "9223372036854775808");
   14732 		  return;
   14733 		}
   14734 	    }
   14735 	  if (!v)
   14736 	    {
   14737 	      strcpy (buf, "0");
   14738 	      return;
   14739 	    }
   14740 
   14741 	  i = 0;
   14742 	  tmp[29] = 0;
   14743 	  while (v)
   14744 	    {
   14745 	      tmp[28 - i] = (v % 10) + '0';
   14746 	      v /= 10;
   14747 	      i++;
   14748 	    }
   14749 	  strcpy (buf, tmp + 29 - i);
   14750 	}
   14751     }
   14752   else
   14753     {
   14754       if (hex)
   14755 	sprintf (buf, "0x%x", (unsigned int) disp);
   14756       else
   14757 	sprintf (buf, "%d", (int) disp);
   14758     }
   14759 }
   14760 
   14761 /* Put DISP in BUF as signed hex number.  */
   14762 
   14763 static void
   14764 print_displacement (char *buf, bfd_vma disp)
   14765 {
   14766   bfd_signed_vma val = disp;
   14767   char tmp[30];
   14768   int i, j = 0;
   14769 
   14770   if (val < 0)
   14771     {
   14772       buf[j++] = '-';
   14773       val = -disp;
   14774 
   14775       /* Check for possible overflow.  */
   14776       if (val < 0)
   14777 	{
   14778 	  switch (address_mode)
   14779 	    {
   14780 	    case mode_64bit:
   14781 	      strcpy (buf + j, "0x8000000000000000");
   14782 	      break;
   14783 	    case mode_32bit:
   14784 	      strcpy (buf + j, "0x80000000");
   14785 	      break;
   14786 	    case mode_16bit:
   14787 	      strcpy (buf + j, "0x8000");
   14788 	      break;
   14789 	    }
   14790 	  return;
   14791 	}
   14792     }
   14793 
   14794   buf[j++] = '0';
   14795   buf[j++] = 'x';
   14796 
   14797   sprintf_vma (tmp, (bfd_vma) val);
   14798   for (i = 0; tmp[i] == '0'; i++)
   14799     continue;
   14800   if (tmp[i] == '\0')
   14801     i--;
   14802   strcpy (buf + j, tmp + i);
   14803 }
   14804 
   14805 static void
   14806 intel_operand_size (int bytemode, int sizeflag)
   14807 {
   14808   if (vex.evex
   14809       && vex.b
   14810       && (bytemode == x_mode
   14811 	  || bytemode == evex_half_bcst_xmmq_mode))
   14812     {
   14813       if (vex.w)
   14814 	oappend ("QWORD PTR ");
   14815       else
   14816 	oappend ("DWORD PTR ");
   14817       return;
   14818     }
   14819   switch (bytemode)
   14820     {
   14821     case b_mode:
   14822     case b_swap_mode:
   14823     case dqb_mode:
   14824     case db_mode:
   14825       oappend ("BYTE PTR ");
   14826       break;
   14827     case w_mode:
   14828     case dw_mode:
   14829     case dqw_mode:
   14830     case dqw_swap_mode:
   14831       oappend ("WORD PTR ");
   14832       break;
   14833     case indir_v_mode:
   14834       if (address_mode == mode_64bit && isa64 == intel64)
   14835 	{
   14836 	  oappend ("QWORD PTR ");
   14837 	  break;
   14838 	}
   14839     case stack_v_mode:
   14840       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
   14841 	{
   14842 	  oappend ("QWORD PTR ");
   14843 	  break;
   14844 	}
   14845       /* FALLTHRU */
   14846     case v_mode:
   14847     case v_swap_mode:
   14848     case dq_mode:
   14849       USED_REX (REX_W);
   14850       if (rex & REX_W)
   14851 	oappend ("QWORD PTR ");
   14852       else
   14853 	{
   14854 	  if ((sizeflag & DFLAG) || bytemode == dq_mode)
   14855 	    oappend ("DWORD PTR ");
   14856 	  else
   14857 	    oappend ("WORD PTR ");
   14858 	  used_prefixes |= (prefixes & PREFIX_DATA);
   14859 	}
   14860       break;
   14861     case z_mode:
   14862       if ((rex & REX_W) || (sizeflag & DFLAG))
   14863 	*obufp++ = 'D';
   14864       oappend ("WORD PTR ");
   14865       if (!(rex & REX_W))
   14866 	used_prefixes |= (prefixes & PREFIX_DATA);
   14867       break;
   14868     case a_mode:
   14869       if (sizeflag & DFLAG)
   14870 	oappend ("QWORD PTR ");
   14871       else
   14872 	oappend ("DWORD PTR ");
   14873       used_prefixes |= (prefixes & PREFIX_DATA);
   14874       break;
   14875     case d_mode:
   14876     case d_scalar_mode:
   14877     case d_scalar_swap_mode:
   14878     case d_swap_mode:
   14879     case dqd_mode:
   14880       oappend ("DWORD PTR ");
   14881       break;
   14882     case q_mode:
   14883     case q_scalar_mode:
   14884     case q_scalar_swap_mode:
   14885     case q_swap_mode:
   14886       oappend ("QWORD PTR ");
   14887       break;
   14888     case m_mode:
   14889       if (address_mode == mode_64bit)
   14890 	oappend ("QWORD PTR ");
   14891       else
   14892 	oappend ("DWORD PTR ");
   14893       break;
   14894     case f_mode:
   14895       if (sizeflag & DFLAG)
   14896 	oappend ("FWORD PTR ");
   14897       else
   14898 	oappend ("DWORD PTR ");
   14899       used_prefixes |= (prefixes & PREFIX_DATA);
   14900       break;
   14901     case t_mode:
   14902       oappend ("TBYTE PTR ");
   14903       break;
   14904     case x_mode:
   14905     case x_swap_mode:
   14906     case evex_x_gscat_mode:
   14907     case evex_x_nobcst_mode:
   14908       if (need_vex)
   14909 	{
   14910 	  switch (vex.length)
   14911 	    {
   14912 	    case 128:
   14913 	      oappend ("XMMWORD PTR ");
   14914 	      break;
   14915 	    case 256:
   14916 	      oappend ("YMMWORD PTR ");
   14917 	      break;
   14918 	    case 512:
   14919 	      oappend ("ZMMWORD PTR ");
   14920 	      break;
   14921 	    default:
   14922 	      abort ();
   14923 	    }
   14924 	}
   14925       else
   14926 	oappend ("XMMWORD PTR ");
   14927       break;
   14928     case xmm_mode:
   14929       oappend ("XMMWORD PTR ");
   14930       break;
   14931     case ymm_mode:
   14932       oappend ("YMMWORD PTR ");
   14933       break;
   14934     case xmmq_mode:
   14935     case evex_half_bcst_xmmq_mode:
   14936       if (!need_vex)
   14937 	abort ();
   14938 
   14939       switch (vex.length)
   14940 	{
   14941 	case 128:
   14942 	  oappend ("QWORD PTR ");
   14943 	  break;
   14944 	case 256:
   14945 	  oappend ("XMMWORD PTR ");
   14946 	  break;
   14947 	case 512:
   14948 	  oappend ("YMMWORD PTR ");
   14949 	  break;
   14950 	default:
   14951 	  abort ();
   14952 	}
   14953       break;
   14954     case xmm_mb_mode:
   14955       if (!need_vex)
   14956 	abort ();
   14957 
   14958       switch (vex.length)
   14959 	{
   14960 	case 128:
   14961 	case 256:
   14962 	case 512:
   14963 	  oappend ("BYTE PTR ");
   14964 	  break;
   14965 	default:
   14966 	  abort ();
   14967 	}
   14968       break;
   14969     case xmm_mw_mode:
   14970       if (!need_vex)
   14971 	abort ();
   14972 
   14973       switch (vex.length)
   14974 	{
   14975 	case 128:
   14976 	case 256:
   14977 	case 512:
   14978 	  oappend ("WORD PTR ");
   14979 	  break;
   14980 	default:
   14981 	  abort ();
   14982 	}
   14983       break;
   14984     case xmm_md_mode:
   14985       if (!need_vex)
   14986 	abort ();
   14987 
   14988       switch (vex.length)
   14989 	{
   14990 	case 128:
   14991 	case 256:
   14992 	case 512:
   14993 	  oappend ("DWORD PTR ");
   14994 	  break;
   14995 	default:
   14996 	  abort ();
   14997 	}
   14998       break;
   14999     case xmm_mq_mode:
   15000       if (!need_vex)
   15001 	abort ();
   15002 
   15003       switch (vex.length)
   15004 	{
   15005 	case 128:
   15006 	case 256:
   15007 	case 512:
   15008 	  oappend ("QWORD PTR ");
   15009 	  break;
   15010 	default:
   15011 	  abort ();
   15012 	}
   15013       break;
   15014     case xmmdw_mode:
   15015       if (!need_vex)
   15016 	abort ();
   15017 
   15018       switch (vex.length)
   15019 	{
   15020 	case 128:
   15021 	  oappend ("WORD PTR ");
   15022 	  break;
   15023 	case 256:
   15024 	  oappend ("DWORD PTR ");
   15025 	  break;
   15026 	case 512:
   15027 	  oappend ("QWORD PTR ");
   15028 	  break;
   15029 	default:
   15030 	  abort ();
   15031 	}
   15032       break;
   15033     case xmmqd_mode:
   15034       if (!need_vex)
   15035 	abort ();
   15036 
   15037       switch (vex.length)
   15038 	{
   15039 	case 128:
   15040 	  oappend ("DWORD PTR ");
   15041 	  break;
   15042 	case 256:
   15043 	  oappend ("QWORD PTR ");
   15044 	  break;
   15045 	case 512:
   15046 	  oappend ("XMMWORD PTR ");
   15047 	  break;
   15048 	default:
   15049 	  abort ();
   15050 	}
   15051       break;
   15052     case ymmq_mode:
   15053       if (!need_vex)
   15054 	abort ();
   15055 
   15056       switch (vex.length)
   15057 	{
   15058 	case 128:
   15059 	  oappend ("QWORD PTR ");
   15060 	  break;
   15061 	case 256:
   15062 	  oappend ("YMMWORD PTR ");
   15063 	  break;
   15064 	case 512:
   15065 	  oappend ("ZMMWORD PTR ");
   15066 	  break;
   15067 	default:
   15068 	  abort ();
   15069 	}
   15070       break;
   15071     case ymmxmm_mode:
   15072       if (!need_vex)
   15073 	abort ();
   15074 
   15075       switch (vex.length)
   15076 	{
   15077 	case 128:
   15078 	case 256:
   15079 	  oappend ("XMMWORD PTR ");
   15080 	  break;
   15081 	default:
   15082 	  abort ();
   15083 	}
   15084       break;
   15085     case o_mode:
   15086       oappend ("OWORD PTR ");
   15087       break;
   15088     case xmm_mdq_mode:
   15089     case vex_w_dq_mode:
   15090     case vex_scalar_w_dq_mode:
   15091       if (!need_vex)
   15092 	abort ();
   15093 
   15094       if (vex.w)
   15095 	oappend ("QWORD PTR ");
   15096       else
   15097 	oappend ("DWORD PTR ");
   15098       break;
   15099     case vex_vsib_d_w_dq_mode:
   15100     case vex_vsib_q_w_dq_mode:
   15101       if (!need_vex)
   15102 	abort ();
   15103 
   15104       if (!vex.evex)
   15105 	{
   15106 	  if (vex.w)
   15107 	    oappend ("QWORD PTR ");
   15108 	  else
   15109 	    oappend ("DWORD PTR ");
   15110 	}
   15111       else
   15112 	{
   15113 	  switch (vex.length)
   15114 	    {
   15115 	    case 128:
   15116 	      oappend ("XMMWORD PTR ");
   15117 	      break;
   15118 	    case 256:
   15119 	      oappend ("YMMWORD PTR ");
   15120 	      break;
   15121 	    case 512:
   15122 	      oappend ("ZMMWORD PTR ");
   15123 	      break;
   15124 	    default:
   15125 	      abort ();
   15126 	    }
   15127 	}
   15128       break;
   15129     case vex_vsib_q_w_d_mode:
   15130     case vex_vsib_d_w_d_mode:
   15131       if (!need_vex || !vex.evex)
   15132 	abort ();
   15133 
   15134       switch (vex.length)
   15135 	{
   15136 	case 128:
   15137 	  oappend ("QWORD PTR ");
   15138 	  break;
   15139 	case 256:
   15140 	  oappend ("XMMWORD PTR ");
   15141 	  break;
   15142 	case 512:
   15143 	  oappend ("YMMWORD PTR ");
   15144 	  break;
   15145 	default:
   15146 	  abort ();
   15147 	}
   15148 
   15149       break;
   15150     case mask_bd_mode:
   15151       if (!need_vex || vex.length != 128)
   15152 	abort ();
   15153       if (vex.w)
   15154 	oappend ("DWORD PTR ");
   15155       else
   15156 	oappend ("BYTE PTR ");
   15157       break;
   15158     case mask_mode:
   15159       if (!need_vex)
   15160 	abort ();
   15161       if (vex.w)
   15162 	oappend ("QWORD PTR ");
   15163       else
   15164 	oappend ("WORD PTR ");
   15165       break;
   15166     case v_bnd_mode:
   15167     default:
   15168       break;
   15169     }
   15170 }
   15171 
   15172 static void
   15173 OP_E_register (int bytemode, int sizeflag)
   15174 {
   15175   int reg = modrm.rm;
   15176   const char **names;
   15177 
   15178   USED_REX (REX_B);
   15179   if ((rex & REX_B))
   15180     reg += 8;
   15181 
   15182   if ((sizeflag & SUFFIX_ALWAYS)
   15183       && (bytemode == b_swap_mode
   15184 	  || bytemode == v_swap_mode
   15185 	  || bytemode == dqw_swap_mode))
   15186     swap_operand ();
   15187 
   15188   switch (bytemode)
   15189     {
   15190     case b_mode:
   15191     case b_swap_mode:
   15192       USED_REX (0);
   15193       if (rex)
   15194 	names = names8rex;
   15195       else
   15196 	names = names8;
   15197       break;
   15198     case w_mode:
   15199       names = names16;
   15200       break;
   15201     case d_mode:
   15202     case dw_mode:
   15203     case db_mode:
   15204       names = names32;
   15205       break;
   15206     case q_mode:
   15207       names = names64;
   15208       break;
   15209     case m_mode:
   15210     case v_bnd_mode:
   15211       names = address_mode == mode_64bit ? names64 : names32;
   15212       break;
   15213     case bnd_mode:
   15214       names = names_bnd;
   15215       break;
   15216     case indir_v_mode:
   15217       if (address_mode == mode_64bit && isa64 == intel64)
   15218 	{
   15219 	  names = names64;
   15220 	  break;
   15221 	}
   15222     case stack_v_mode:
   15223       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
   15224 	{
   15225 	  names = names64;
   15226 	  break;
   15227 	}
   15228       bytemode = v_mode;
   15229       /* FALLTHRU */
   15230     case v_mode:
   15231     case v_swap_mode:
   15232     case dq_mode:
   15233     case dqb_mode:
   15234     case dqd_mode:
   15235     case dqw_mode:
   15236     case dqw_swap_mode:
   15237       USED_REX (REX_W);
   15238       if (rex & REX_W)
   15239 	names = names64;
   15240       else
   15241 	{
   15242 	  if ((sizeflag & DFLAG)
   15243 	      || (bytemode != v_mode
   15244 		  && bytemode != v_swap_mode))
   15245 	    names = names32;
   15246 	  else
   15247 	    names = names16;
   15248 	  used_prefixes |= (prefixes & PREFIX_DATA);
   15249 	}
   15250       break;
   15251     case mask_bd_mode:
   15252     case mask_mode:
   15253       names = names_mask;
   15254       break;
   15255     case 0:
   15256       return;
   15257     default:
   15258       oappend (INTERNAL_DISASSEMBLER_ERROR);
   15259       return;
   15260     }
   15261   oappend (names[reg]);
   15262 }
   15263 
   15264 static void
   15265 OP_E_memory (int bytemode, int sizeflag)
   15266 {
   15267   bfd_vma disp = 0;
   15268   int add = (rex & REX_B) ? 8 : 0;
   15269   int riprel = 0;
   15270   int shift;
   15271 
   15272   if (vex.evex)
   15273     {
   15274       /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0.  */
   15275       if (vex.b
   15276 	  && bytemode != x_mode
   15277 	  && bytemode != xmmq_mode
   15278 	  && bytemode != evex_half_bcst_xmmq_mode)
   15279 	{
   15280 	  BadOp ();
   15281 	  return;
   15282 	}
   15283       switch (bytemode)
   15284 	{
   15285 	case dqw_mode:
   15286 	case dw_mode:
   15287 	case dqw_swap_mode:
   15288 	  shift = 1;
   15289 	  break;
   15290 	case dqb_mode:
   15291 	case db_mode:
   15292 	  shift = 0;
   15293 	  break;
   15294 	case vex_vsib_d_w_dq_mode:
   15295 	case vex_vsib_d_w_d_mode:
   15296 	case vex_vsib_q_w_dq_mode:
   15297 	case vex_vsib_q_w_d_mode:
   15298 	case evex_x_gscat_mode:
   15299 	case xmm_mdq_mode:
   15300 	  shift = vex.w ? 3 : 2;
   15301 	  break;
   15302 	case x_mode:
   15303 	case evex_half_bcst_xmmq_mode:
   15304 	case xmmq_mode:
   15305 	  if (vex.b)
   15306 	    {
   15307 	      shift = vex.w ? 3 : 2;
   15308 	      break;
   15309 	    }
   15310 	  /* Fall through if vex.b == 0.  */
   15311 	case xmmqd_mode:
   15312 	case xmmdw_mode:
   15313 	case ymmq_mode:
   15314 	case evex_x_nobcst_mode:
   15315 	case x_swap_mode:
   15316 	  switch (vex.length)
   15317 	    {
   15318 	    case 128:
   15319 	      shift = 4;
   15320 	      break;
   15321 	    case 256:
   15322 	      shift = 5;
   15323 	      break;
   15324 	    case 512:
   15325 	      shift = 6;
   15326 	      break;
   15327 	    default:
   15328 	      abort ();
   15329 	    }
   15330 	  break;
   15331 	case ymm_mode:
   15332 	  shift = 5;
   15333 	  break;
   15334 	case xmm_mode:
   15335 	  shift = 4;
   15336 	  break;
   15337 	case xmm_mq_mode:
   15338 	case q_mode:
   15339 	case q_scalar_mode:
   15340 	case q_swap_mode:
   15341 	case q_scalar_swap_mode:
   15342 	  shift = 3;
   15343 	  break;
   15344 	case dqd_mode:
   15345 	case xmm_md_mode:
   15346 	case d_mode:
   15347 	case d_scalar_mode:
   15348 	case d_swap_mode:
   15349 	case d_scalar_swap_mode:
   15350 	  shift = 2;
   15351 	  break;
   15352 	case xmm_mw_mode:
   15353 	  shift = 1;
   15354 	  break;
   15355 	case xmm_mb_mode:
   15356 	  shift = 0;
   15357 	  break;
   15358 	default:
   15359 	  abort ();
   15360 	}
   15361       /* Make necessary corrections to shift for modes that need it.
   15362 	 For these modes we currently have shift 4, 5 or 6 depending on
   15363 	 vex.length (it corresponds to xmmword, ymmword or zmmword
   15364 	 operand).  We might want to make it 3, 4 or 5 (e.g. for
   15365 	 xmmq_mode).  In case of broadcast enabled the corrections
   15366 	 aren't needed, as element size is always 32 or 64 bits.  */
   15367       if (!vex.b
   15368 	  && (bytemode == xmmq_mode
   15369 	      || bytemode == evex_half_bcst_xmmq_mode))
   15370 	shift -= 1;
   15371       else if (bytemode == xmmqd_mode)
   15372 	shift -= 2;
   15373       else if (bytemode == xmmdw_mode)
   15374 	shift -= 3;
   15375       else if (bytemode == ymmq_mode && vex.length == 128)
   15376 	shift -= 1;
   15377     }
   15378   else
   15379     shift = 0;
   15380 
   15381   USED_REX (REX_B);
   15382   if (intel_syntax)
   15383     intel_operand_size (bytemode, sizeflag);
   15384   append_seg ();
   15385 
   15386   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
   15387     {
   15388       /* 32/64 bit address mode */
   15389       int havedisp;
   15390       int havesib;
   15391       int havebase;
   15392       int haveindex;
   15393       int needindex;
   15394       int base, rbase;
   15395       int vindex = 0;
   15396       int scale = 0;
   15397       int addr32flag = !((sizeflag & AFLAG)
   15398 			 || bytemode == v_bnd_mode
   15399 			 || bytemode == bnd_mode);
   15400       const char **indexes64 = names64;
   15401       const char **indexes32 = names32;
   15402 
   15403       havesib = 0;
   15404       havebase = 1;
   15405       haveindex = 0;
   15406       base = modrm.rm;
   15407 
   15408       if (base == 4)
   15409 	{
   15410 	  havesib = 1;
   15411 	  vindex = sib.index;
   15412 	  USED_REX (REX_X);
   15413 	  if (rex & REX_X)
   15414 	    vindex += 8;
   15415 	  switch (bytemode)
   15416 	    {
   15417 	    case vex_vsib_d_w_dq_mode:
   15418 	    case vex_vsib_d_w_d_mode:
   15419 	    case vex_vsib_q_w_dq_mode:
   15420 	    case vex_vsib_q_w_d_mode:
   15421 	      if (!need_vex)
   15422 		abort ();
   15423 	      if (vex.evex)
   15424 		{
   15425 		  if (!vex.v)
   15426 		    vindex += 16;
   15427 		}
   15428 
   15429 	      haveindex = 1;
   15430 	      switch (vex.length)
   15431 		{
   15432 		case 128:
   15433 		  indexes64 = indexes32 = names_xmm;
   15434 		  break;
   15435 		case 256:
   15436 		  if (!vex.w
   15437 		      || bytemode == vex_vsib_q_w_dq_mode
   15438 		      || bytemode == vex_vsib_q_w_d_mode)
   15439 		    indexes64 = indexes32 = names_ymm;
   15440 		  else
   15441 		    indexes64 = indexes32 = names_xmm;
   15442 		  break;
   15443 		case 512:
   15444 		  if (!vex.w
   15445 		      || bytemode == vex_vsib_q_w_dq_mode
   15446 		      || bytemode == vex_vsib_q_w_d_mode)
   15447 		    indexes64 = indexes32 = names_zmm;
   15448 		  else
   15449 		    indexes64 = indexes32 = names_ymm;
   15450 		  break;
   15451 		default:
   15452 		  abort ();
   15453 		}
   15454 	      break;
   15455 	    default:
   15456 	      haveindex = vindex != 4;
   15457 	      break;
   15458 	    }
   15459 	  scale = sib.scale;
   15460 	  base = sib.base;
   15461 	  codep++;
   15462 	}
   15463       rbase = base + add;
   15464 
   15465       switch (modrm.mod)
   15466 	{
   15467 	case 0:
   15468 	  if (base == 5)
   15469 	    {
   15470 	      havebase = 0;
   15471 	      if (address_mode == mode_64bit && !havesib)
   15472 		riprel = 1;
   15473 	      disp = get32s ();
   15474 	    }
   15475 	  break;
   15476 	case 1:
   15477 	  FETCH_DATA (the_info, codep + 1);
   15478 	  disp = *codep++;
   15479 	  if ((disp & 0x80) != 0)
   15480 	    disp -= 0x100;
   15481 	  if (vex.evex && shift > 0)
   15482 	    disp <<= shift;
   15483 	  break;
   15484 	case 2:
   15485 	  disp = get32s ();
   15486 	  break;
   15487 	}
   15488 
   15489       /* In 32bit mode, we need index register to tell [offset] from
   15490 	 [eiz*1 + offset].  */
   15491       needindex = (havesib
   15492 		   && !havebase
   15493 		   && !haveindex
   15494 		   && address_mode == mode_32bit);
   15495       havedisp = (havebase
   15496 		  || needindex
   15497 		  || (havesib && (haveindex || scale != 0)));
   15498 
   15499       if (!intel_syntax)
   15500 	if (modrm.mod != 0 || base == 5)
   15501 	  {
   15502 	    if (havedisp || riprel)
   15503 	      print_displacement (scratchbuf, disp);
   15504 	    else
   15505 	      print_operand_value (scratchbuf, 1, disp);
   15506 	    oappend (scratchbuf);
   15507 	    if (riprel)
   15508 	      {
   15509 		set_op (disp, 1);
   15510 		oappend (sizeflag & AFLAG ? "(%rip)" : "(%eip)");
   15511 	      }
   15512 	  }
   15513 
   15514       if ((havebase || haveindex || riprel)
   15515 	  && (bytemode != v_bnd_mode)
   15516 	  && (bytemode != bnd_mode))
   15517 	used_prefixes |= PREFIX_ADDR;
   15518 
   15519       if (havedisp || (intel_syntax && riprel))
   15520 	{
   15521 	  *obufp++ = open_char;
   15522 	  if (intel_syntax && riprel)
   15523 	    {
   15524 	      set_op (disp, 1);
   15525 	      oappend (sizeflag & AFLAG ? "rip" : "eip");
   15526 	    }
   15527 	  *obufp = '\0';
   15528 	  if (havebase)
   15529 	    oappend (address_mode == mode_64bit && !addr32flag
   15530 		     ? names64[rbase] : names32[rbase]);
   15531 	  if (havesib)
   15532 	    {
   15533 	      /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
   15534 		 print index to tell base + index from base.  */
   15535 	      if (scale != 0
   15536 		  || needindex
   15537 		  || haveindex
   15538 		  || (havebase && base != ESP_REG_NUM))
   15539 		{
   15540 		  if (!intel_syntax || havebase)
   15541 		    {
   15542 		      *obufp++ = separator_char;
   15543 		      *obufp = '\0';
   15544 		    }
   15545 		  if (haveindex)
   15546 		    oappend (address_mode == mode_64bit && !addr32flag
   15547 			     ? indexes64[vindex] : indexes32[vindex]);
   15548 		  else
   15549 		    oappend (address_mode == mode_64bit && !addr32flag
   15550 			     ? index64 : index32);
   15551 
   15552 		  *obufp++ = scale_char;
   15553 		  *obufp = '\0';
   15554 		  sprintf (scratchbuf, "%d", 1 << scale);
   15555 		  oappend (scratchbuf);
   15556 		}
   15557 	    }
   15558 	  if (intel_syntax
   15559 	      && (disp || modrm.mod != 0 || base == 5))
   15560 	    {
   15561 	      if (!havedisp || (bfd_signed_vma) disp >= 0)
   15562 		{
   15563 		  *obufp++ = '+';
   15564 		  *obufp = '\0';
   15565 		}
   15566 	      else if (modrm.mod != 1 && disp != -disp)
   15567 		{
   15568 		  *obufp++ = '-';
   15569 		  *obufp = '\0';
   15570 		  disp = - (bfd_signed_vma) disp;
   15571 		}
   15572 
   15573 	      if (havedisp)
   15574 		print_displacement (scratchbuf, disp);
   15575 	      else
   15576 		print_operand_value (scratchbuf, 1, disp);
   15577 	      oappend (scratchbuf);
   15578 	    }
   15579 
   15580 	  *obufp++ = close_char;
   15581 	  *obufp = '\0';
   15582 	}
   15583       else if (intel_syntax)
   15584 	{
   15585 	  if (modrm.mod != 0 || base == 5)
   15586 	    {
   15587 	      if (!active_seg_prefix)
   15588 		{
   15589 		  oappend (names_seg[ds_reg - es_reg]);
   15590 		  oappend (":");
   15591 		}
   15592 	      print_operand_value (scratchbuf, 1, disp);
   15593 	      oappend (scratchbuf);
   15594 	    }
   15595 	}
   15596     }
   15597   else
   15598     {
   15599       /* 16 bit address mode */
   15600       used_prefixes |= prefixes & PREFIX_ADDR;
   15601       switch (modrm.mod)
   15602 	{
   15603 	case 0:
   15604 	  if (modrm.rm == 6)
   15605 	    {
   15606 	      disp = get16 ();
   15607 	      if ((disp & 0x8000) != 0)
   15608 		disp -= 0x10000;
   15609 	    }
   15610 	  break;
   15611 	case 1:
   15612 	  FETCH_DATA (the_info, codep + 1);
   15613 	  disp = *codep++;
   15614 	  if ((disp & 0x80) != 0)
   15615 	    disp -= 0x100;
   15616 	  break;
   15617 	case 2:
   15618 	  disp = get16 ();
   15619 	  if ((disp & 0x8000) != 0)
   15620 	    disp -= 0x10000;
   15621 	  break;
   15622 	}
   15623 
   15624       if (!intel_syntax)
   15625 	if (modrm.mod != 0 || modrm.rm == 6)
   15626 	  {
   15627 	    print_displacement (scratchbuf, disp);
   15628 	    oappend (scratchbuf);
   15629 	  }
   15630 
   15631       if (modrm.mod != 0 || modrm.rm != 6)
   15632 	{
   15633 	  *obufp++ = open_char;
   15634 	  *obufp = '\0';
   15635 	  oappend (index16[modrm.rm]);
   15636 	  if (intel_syntax
   15637 	      && (disp || modrm.mod != 0 || modrm.rm == 6))
   15638 	    {
   15639 	      if ((bfd_signed_vma) disp >= 0)
   15640 		{
   15641 		  *obufp++ = '+';
   15642 		  *obufp = '\0';
   15643 		}
   15644 	      else if (modrm.mod != 1)
   15645 		{
   15646 		  *obufp++ = '-';
   15647 		  *obufp = '\0';
   15648 		  disp = - (bfd_signed_vma) disp;
   15649 		}
   15650 
   15651 	      print_displacement (scratchbuf, disp);
   15652 	      oappend (scratchbuf);
   15653 	    }
   15654 
   15655 	  *obufp++ = close_char;
   15656 	  *obufp = '\0';
   15657 	}
   15658       else if (intel_syntax)
   15659 	{
   15660 	  if (!active_seg_prefix)
   15661 	    {
   15662 	      oappend (names_seg[ds_reg - es_reg]);
   15663 	      oappend (":");
   15664 	    }
   15665 	  print_operand_value (scratchbuf, 1, disp & 0xffff);
   15666 	  oappend (scratchbuf);
   15667 	}
   15668     }
   15669   if (vex.evex && vex.b
   15670       && (bytemode == x_mode
   15671 	  || bytemode == xmmq_mode
   15672 	  || bytemode == evex_half_bcst_xmmq_mode))
   15673     {
   15674       if (vex.w
   15675 	  || bytemode == xmmq_mode
   15676 	  || bytemode == evex_half_bcst_xmmq_mode)
   15677 	{
   15678 	  switch (vex.length)
   15679 	    {
   15680 	    case 128:
   15681 	      oappend ("{1to2}");
   15682 	      break;
   15683 	    case 256:
   15684 	      oappend ("{1to4}");
   15685 	      break;
   15686 	    case 512:
   15687 	      oappend ("{1to8}");
   15688 	      break;
   15689 	    default:
   15690 	      abort ();
   15691 	    }
   15692 	}
   15693       else
   15694 	{
   15695 	  switch (vex.length)
   15696 	    {
   15697 	    case 128:
   15698 	      oappend ("{1to4}");
   15699 	      break;
   15700 	    case 256:
   15701 	      oappend ("{1to8}");
   15702 	      break;
   15703 	    case 512:
   15704 	      oappend ("{1to16}");
   15705 	      break;
   15706 	    default:
   15707 	      abort ();
   15708 	    }
   15709 	}
   15710     }
   15711 }
   15712 
   15713 static void
   15714 OP_E (int bytemode, int sizeflag)
   15715 {
   15716   /* Skip mod/rm byte.  */
   15717   MODRM_CHECK;
   15718   codep++;
   15719 
   15720   if (modrm.mod == 3)
   15721     OP_E_register (bytemode, sizeflag);
   15722   else
   15723     OP_E_memory (bytemode, sizeflag);
   15724 }
   15725 
   15726 static void
   15727 OP_G (int bytemode, int sizeflag)
   15728 {
   15729   int add = 0;
   15730   USED_REX (REX_R);
   15731   if (rex & REX_R)
   15732     add += 8;
   15733   switch (bytemode)
   15734     {
   15735     case b_mode:
   15736       USED_REX (0);
   15737       if (rex)
   15738 	oappend (names8rex[modrm.reg + add]);
   15739       else
   15740 	oappend (names8[modrm.reg + add]);
   15741       break;
   15742     case w_mode:
   15743       oappend (names16[modrm.reg + add]);
   15744       break;
   15745     case d_mode:
   15746     case db_mode:
   15747     case dw_mode:
   15748       oappend (names32[modrm.reg + add]);
   15749       break;
   15750     case q_mode:
   15751       oappend (names64[modrm.reg + add]);
   15752       break;
   15753     case bnd_mode:
   15754       oappend (names_bnd[modrm.reg]);
   15755       break;
   15756     case v_mode:
   15757     case dq_mode:
   15758     case dqb_mode:
   15759     case dqd_mode:
   15760     case dqw_mode:
   15761     case dqw_swap_mode:
   15762       USED_REX (REX_W);
   15763       if (rex & REX_W)
   15764 	oappend (names64[modrm.reg + add]);
   15765       else
   15766 	{
   15767 	  if ((sizeflag & DFLAG) || bytemode != v_mode)
   15768 	    oappend (names32[modrm.reg + add]);
   15769 	  else
   15770 	    oappend (names16[modrm.reg + add]);
   15771 	  used_prefixes |= (prefixes & PREFIX_DATA);
   15772 	}
   15773       break;
   15774     case m_mode:
   15775       if (address_mode == mode_64bit)
   15776 	oappend (names64[modrm.reg + add]);
   15777       else
   15778 	oappend (names32[modrm.reg + add]);
   15779       break;
   15780     case mask_bd_mode:
   15781     case mask_mode:
   15782       oappend (names_mask[modrm.reg + add]);
   15783       break;
   15784     default:
   15785       oappend (INTERNAL_DISASSEMBLER_ERROR);
   15786       break;
   15787     }
   15788 }
   15789 
   15790 static bfd_vma
   15791 get64 (void)
   15792 {
   15793   bfd_vma x;
   15794 #ifdef BFD64
   15795   unsigned int a;
   15796   unsigned int b;
   15797 
   15798   FETCH_DATA (the_info, codep + 8);
   15799   a = *codep++ & 0xff;
   15800   a |= (*codep++ & 0xff) << 8;
   15801   a |= (*codep++ & 0xff) << 16;
   15802   a |= (*codep++ & 0xffu) << 24;
   15803   b = *codep++ & 0xff;
   15804   b |= (*codep++ & 0xff) << 8;
   15805   b |= (*codep++ & 0xff) << 16;
   15806   b |= (*codep++ & 0xffu) << 24;
   15807   x = a + ((bfd_vma) b << 32);
   15808 #else
   15809   abort ();
   15810   x = 0;
   15811 #endif
   15812   return x;
   15813 }
   15814 
   15815 static bfd_signed_vma
   15816 get32 (void)
   15817 {
   15818   bfd_signed_vma x = 0;
   15819 
   15820   FETCH_DATA (the_info, codep + 4);
   15821   x = *codep++ & (bfd_signed_vma) 0xff;
   15822   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
   15823   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
   15824   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
   15825   return x;
   15826 }
   15827 
   15828 static bfd_signed_vma
   15829 get32s (void)
   15830 {
   15831   bfd_signed_vma x = 0;
   15832 
   15833   FETCH_DATA (the_info, codep + 4);
   15834   x = *codep++ & (bfd_signed_vma) 0xff;
   15835   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
   15836   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
   15837   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
   15838 
   15839   x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
   15840 
   15841   return x;
   15842 }
   15843 
   15844 static int
   15845 get16 (void)
   15846 {
   15847   int x = 0;
   15848 
   15849   FETCH_DATA (the_info, codep + 2);
   15850   x = *codep++ & 0xff;
   15851   x |= (*codep++ & 0xff) << 8;
   15852   return x;
   15853 }
   15854 
   15855 static void
   15856 set_op (bfd_vma op, int riprel)
   15857 {
   15858   op_index[op_ad] = op_ad;
   15859   if (address_mode == mode_64bit)
   15860     {
   15861       op_address[op_ad] = op;
   15862       op_riprel[op_ad] = riprel;
   15863     }
   15864   else
   15865     {
   15866       /* Mask to get a 32-bit address.  */
   15867       op_address[op_ad] = op & 0xffffffff;
   15868       op_riprel[op_ad] = riprel & 0xffffffff;
   15869     }
   15870 }
   15871 
   15872 static void
   15873 OP_REG (int code, int sizeflag)
   15874 {
   15875   const char *s;
   15876   int add;
   15877 
   15878   switch (code)
   15879     {
   15880     case es_reg: case ss_reg: case cs_reg:
   15881     case ds_reg: case fs_reg: case gs_reg:
   15882       oappend (names_seg[code - es_reg]);
   15883       return;
   15884     }
   15885 
   15886   USED_REX (REX_B);
   15887   if (rex & REX_B)
   15888     add = 8;
   15889   else
   15890     add = 0;
   15891 
   15892   switch (code)
   15893     {
   15894     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
   15895     case sp_reg: case bp_reg: case si_reg: case di_reg:
   15896       s = names16[code - ax_reg + add];
   15897       break;
   15898     case al_reg: case ah_reg: case cl_reg: case ch_reg:
   15899     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
   15900       USED_REX (0);
   15901       if (rex)
   15902 	s = names8rex[code - al_reg + add];
   15903       else
   15904 	s = names8[code - al_reg];
   15905       break;
   15906     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
   15907     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
   15908       if (address_mode == mode_64bit
   15909 	  && ((sizeflag & DFLAG) || (rex & REX_W)))
   15910 	{
   15911 	  s = names64[code - rAX_reg + add];
   15912 	  break;
   15913 	}
   15914       code += eAX_reg - rAX_reg;
   15915       /* Fall through.  */
   15916     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
   15917     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
   15918       USED_REX (REX_W);
   15919       if (rex & REX_W)
   15920 	s = names64[code - eAX_reg + add];
   15921       else
   15922 	{
   15923 	  if (sizeflag & DFLAG)
   15924 	    s = names32[code - eAX_reg + add];
   15925 	  else
   15926 	    s = names16[code - eAX_reg + add];
   15927 	  used_prefixes |= (prefixes & PREFIX_DATA);
   15928 	}
   15929       break;
   15930     default:
   15931       s = INTERNAL_DISASSEMBLER_ERROR;
   15932       break;
   15933     }
   15934   oappend (s);
   15935 }
   15936 
   15937 static void
   15938 OP_IMREG (int code, int sizeflag)
   15939 {
   15940   const char *s;
   15941 
   15942   switch (code)
   15943     {
   15944     case indir_dx_reg:
   15945       if (intel_syntax)
   15946 	s = "dx";
   15947       else
   15948 	s = "(%dx)";
   15949       break;
   15950     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
   15951     case sp_reg: case bp_reg: case si_reg: case di_reg:
   15952       s = names16[code - ax_reg];
   15953       break;
   15954     case es_reg: case ss_reg: case cs_reg:
   15955     case ds_reg: case fs_reg: case gs_reg:
   15956       s = names_seg[code - es_reg];
   15957       break;
   15958     case al_reg: case ah_reg: case cl_reg: case ch_reg:
   15959     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
   15960       USED_REX (0);
   15961       if (rex)
   15962 	s = names8rex[code - al_reg];
   15963       else
   15964 	s = names8[code - al_reg];
   15965       break;
   15966     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
   15967     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
   15968       USED_REX (REX_W);
   15969       if (rex & REX_W)
   15970 	s = names64[code - eAX_reg];
   15971       else
   15972 	{
   15973 	  if (sizeflag & DFLAG)
   15974 	    s = names32[code - eAX_reg];
   15975 	  else
   15976 	    s = names16[code - eAX_reg];
   15977 	  used_prefixes |= (prefixes & PREFIX_DATA);
   15978 	}
   15979       break;
   15980     case z_mode_ax_reg:
   15981       if ((rex & REX_W) || (sizeflag & DFLAG))
   15982 	s = *names32;
   15983       else
   15984 	s = *names16;
   15985       if (!(rex & REX_W))
   15986 	used_prefixes |= (prefixes & PREFIX_DATA);
   15987       break;
   15988     default:
   15989       s = INTERNAL_DISASSEMBLER_ERROR;
   15990       break;
   15991     }
   15992   oappend (s);
   15993 }
   15994 
   15995 static void
   15996 OP_I (int bytemode, int sizeflag)
   15997 {
   15998   bfd_signed_vma op;
   15999   bfd_signed_vma mask = -1;
   16000 
   16001   switch (bytemode)
   16002     {
   16003     case b_mode:
   16004       FETCH_DATA (the_info, codep + 1);
   16005       op = *codep++;
   16006       mask = 0xff;
   16007       break;
   16008     case q_mode:
   16009       if (address_mode == mode_64bit)
   16010 	{
   16011 	  op = get32s ();
   16012 	  break;
   16013 	}
   16014       /* Fall through.  */
   16015     case v_mode:
   16016       USED_REX (REX_W);
   16017       if (rex & REX_W)
   16018 	op = get32s ();
   16019       else
   16020 	{
   16021 	  if (sizeflag & DFLAG)
   16022 	    {
   16023 	      op = get32 ();
   16024 	      mask = 0xffffffff;
   16025 	    }
   16026 	  else
   16027 	    {
   16028 	      op = get16 ();
   16029 	      mask = 0xfffff;
   16030 	    }
   16031 	  used_prefixes |= (prefixes & PREFIX_DATA);
   16032 	}
   16033       break;
   16034     case w_mode:
   16035       mask = 0xfffff;
   16036       op = get16 ();
   16037       break;
   16038     case const_1_mode:
   16039       if (intel_syntax)
   16040 	oappend ("1");
   16041       return;
   16042     default:
   16043       oappend (INTERNAL_DISASSEMBLER_ERROR);
   16044       return;
   16045     }
   16046 
   16047   op &= mask;
   16048   scratchbuf[0] = '$';
   16049   print_operand_value (scratchbuf + 1, 1, op);
   16050   oappend_maybe_intel (scratchbuf);
   16051   scratchbuf[0] = '\0';
   16052 }
   16053 
   16054 static void
   16055 OP_I64 (int bytemode, int sizeflag)
   16056 {
   16057   bfd_signed_vma op;
   16058   bfd_signed_vma mask = -1;
   16059 
   16060   if (address_mode != mode_64bit)
   16061     {
   16062       OP_I (bytemode, sizeflag);
   16063       return;
   16064     }
   16065 
   16066   switch (bytemode)
   16067     {
   16068     case b_mode:
   16069       FETCH_DATA (the_info, codep + 1);
   16070       op = *codep++;
   16071       mask = 0xff;
   16072       break;
   16073     case v_mode:
   16074       USED_REX (REX_W);
   16075       if (rex & REX_W)
   16076 	op = get64 ();
   16077       else
   16078 	{
   16079 	  if (sizeflag & DFLAG)
   16080 	    {
   16081 	      op = get32 ();
   16082 	      mask = 0xffffffff;
   16083 	    }
   16084 	  else
   16085 	    {
   16086 	      op = get16 ();
   16087 	      mask = 0xfffff;
   16088 	    }
   16089 	  used_prefixes |= (prefixes & PREFIX_DATA);
   16090 	}
   16091       break;
   16092     case w_mode:
   16093       mask = 0xfffff;
   16094       op = get16 ();
   16095       break;
   16096     default:
   16097       oappend (INTERNAL_DISASSEMBLER_ERROR);
   16098       return;
   16099     }
   16100 
   16101   op &= mask;
   16102   scratchbuf[0] = '$';
   16103   print_operand_value (scratchbuf + 1, 1, op);
   16104   oappend_maybe_intel (scratchbuf);
   16105   scratchbuf[0] = '\0';
   16106 }
   16107 
   16108 static void
   16109 OP_sI (int bytemode, int sizeflag)
   16110 {
   16111   bfd_signed_vma op;
   16112 
   16113   switch (bytemode)
   16114     {
   16115     case b_mode:
   16116     case b_T_mode:
   16117       FETCH_DATA (the_info, codep + 1);
   16118       op = *codep++;
   16119       if ((op & 0x80) != 0)
   16120 	op -= 0x100;
   16121       if (bytemode == b_T_mode)
   16122 	{
   16123 	  if (address_mode != mode_64bit
   16124 	      || !((sizeflag & DFLAG) || (rex & REX_W)))
   16125 	    {
   16126 	      /* The operand-size prefix is overridden by a REX prefix.  */
   16127 	      if ((sizeflag & DFLAG) || (rex & REX_W))
   16128 		op &= 0xffffffff;
   16129 	      else
   16130 		op &= 0xffff;
   16131 	  }
   16132 	}
   16133       else
   16134 	{
   16135 	  if (!(rex & REX_W))
   16136 	    {
   16137 	      if (sizeflag & DFLAG)
   16138 		op &= 0xffffffff;
   16139 	      else
   16140 		op &= 0xffff;
   16141 	    }
   16142 	}
   16143       break;
   16144     case v_mode:
   16145       /* The operand-size prefix is overridden by a REX prefix.  */
   16146       if ((sizeflag & DFLAG) || (rex & REX_W))
   16147 	op = get32s ();
   16148       else
   16149 	op = get16 ();
   16150       break;
   16151     default:
   16152       oappend (INTERNAL_DISASSEMBLER_ERROR);
   16153       return;
   16154     }
   16155 
   16156   scratchbuf[0] = '$';
   16157   print_operand_value (scratchbuf + 1, 1, op);
   16158   oappend_maybe_intel (scratchbuf);
   16159 }
   16160 
   16161 static void
   16162 OP_J (int bytemode, int sizeflag)
   16163 {
   16164   bfd_vma disp;
   16165   bfd_vma mask = -1;
   16166   bfd_vma segment = 0;
   16167 
   16168   switch (bytemode)
   16169     {
   16170     case b_mode:
   16171       FETCH_DATA (the_info, codep + 1);
   16172       disp = *codep++;
   16173       if ((disp & 0x80) != 0)
   16174 	disp -= 0x100;
   16175       break;
   16176     case v_mode:
   16177       if (isa64 == amd64)
   16178 	USED_REX (REX_W);
   16179       if ((sizeflag & DFLAG)
   16180 	  || (address_mode == mode_64bit
   16181 	      && (isa64 != amd64 || (rex & REX_W))))
   16182 	disp = get32s ();
   16183       else
   16184 	{
   16185 	  disp = get16 ();
   16186 	  if ((disp & 0x8000) != 0)
   16187 	    disp -= 0x10000;
   16188 	  /* In 16bit mode, address is wrapped around at 64k within
   16189 	     the same segment.  Otherwise, a data16 prefix on a jump
   16190 	     instruction means that the pc is masked to 16 bits after
   16191 	     the displacement is added!  */
   16192 	  mask = 0xffff;
   16193 	  if ((prefixes & PREFIX_DATA) == 0)
   16194 	    segment = ((start_pc + (codep - start_codep))
   16195 		       & ~((bfd_vma) 0xffff));
   16196 	}
   16197       if (address_mode != mode_64bit
   16198 	  || (isa64 == amd64 && !(rex & REX_W)))
   16199 	used_prefixes |= (prefixes & PREFIX_DATA);
   16200       break;
   16201     default:
   16202       oappend (INTERNAL_DISASSEMBLER_ERROR);
   16203       return;
   16204     }
   16205   disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
   16206   set_op (disp, 0);
   16207   print_operand_value (scratchbuf, 1, disp);
   16208   oappend (scratchbuf);
   16209 }
   16210 
   16211 static void
   16212 OP_SEG (int bytemode, int sizeflag)
   16213 {
   16214   if (bytemode == w_mode)
   16215     oappend (names_seg[modrm.reg]);
   16216   else
   16217     OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
   16218 }
   16219 
   16220 static void
   16221 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
   16222 {
   16223   int seg, offset;
   16224 
   16225   if (sizeflag & DFLAG)
   16226     {
   16227       offset = get32 ();
   16228       seg = get16 ();
   16229     }
   16230   else
   16231     {
   16232       offset = get16 ();
   16233       seg = get16 ();
   16234     }
   16235   used_prefixes |= (prefixes & PREFIX_DATA);
   16236   if (intel_syntax)
   16237     sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
   16238   else
   16239     sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
   16240   oappend (scratchbuf);
   16241 }
   16242 
   16243 static void
   16244 OP_OFF (int bytemode, int sizeflag)
   16245 {
   16246   bfd_vma off;
   16247 
   16248   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
   16249     intel_operand_size (bytemode, sizeflag);
   16250   append_seg ();
   16251 
   16252   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
   16253     off = get32 ();
   16254   else
   16255     off = get16 ();
   16256 
   16257   if (intel_syntax)
   16258     {
   16259       if (!active_seg_prefix)
   16260 	{
   16261 	  oappend (names_seg[ds_reg - es_reg]);
   16262 	  oappend (":");
   16263 	}
   16264     }
   16265   print_operand_value (scratchbuf, 1, off);
   16266   oappend (scratchbuf);
   16267 }
   16268 
   16269 static void
   16270 OP_OFF64 (int bytemode, int sizeflag)
   16271 {
   16272   bfd_vma off;
   16273 
   16274   if (address_mode != mode_64bit
   16275       || (prefixes & PREFIX_ADDR))
   16276     {
   16277       OP_OFF (bytemode, sizeflag);
   16278       return;
   16279     }
   16280 
   16281   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
   16282     intel_operand_size (bytemode, sizeflag);
   16283   append_seg ();
   16284 
   16285   off = get64 ();
   16286 
   16287   if (intel_syntax)
   16288     {
   16289       if (!active_seg_prefix)
   16290 	{
   16291 	  oappend (names_seg[ds_reg - es_reg]);
   16292 	  oappend (":");
   16293 	}
   16294     }
   16295   print_operand_value (scratchbuf, 1, off);
   16296   oappend (scratchbuf);
   16297 }
   16298 
   16299 static void
   16300 ptr_reg (int code, int sizeflag)
   16301 {
   16302   const char *s;
   16303 
   16304   *obufp++ = open_char;
   16305   used_prefixes |= (prefixes & PREFIX_ADDR);
   16306   if (address_mode == mode_64bit)
   16307     {
   16308       if (!(sizeflag & AFLAG))
   16309 	s = names32[code - eAX_reg];
   16310       else
   16311 	s = names64[code - eAX_reg];
   16312     }
   16313   else if (sizeflag & AFLAG)
   16314     s = names32[code - eAX_reg];
   16315   else
   16316     s = names16[code - eAX_reg];
   16317   oappend (s);
   16318   *obufp++ = close_char;
   16319   *obufp = 0;
   16320 }
   16321 
   16322 static void
   16323 OP_ESreg (int code, int sizeflag)
   16324 {
   16325   if (intel_syntax)
   16326     {
   16327       switch (codep[-1])
   16328 	{
   16329 	case 0x6d:	/* insw/insl */
   16330 	  intel_operand_size (z_mode, sizeflag);
   16331 	  break;
   16332 	case 0xa5:	/* movsw/movsl/movsq */
   16333 	case 0xa7:	/* cmpsw/cmpsl/cmpsq */
   16334 	case 0xab:	/* stosw/stosl */
   16335 	case 0xaf:	/* scasw/scasl */
   16336 	  intel_operand_size (v_mode, sizeflag);
   16337 	  break;
   16338 	default:
   16339 	  intel_operand_size (b_mode, sizeflag);
   16340 	}
   16341     }
   16342   oappend_maybe_intel ("%es:");
   16343   ptr_reg (code, sizeflag);
   16344 }
   16345 
   16346 static void
   16347 OP_DSreg (int code, int sizeflag)
   16348 {
   16349   if (intel_syntax)
   16350     {
   16351       switch (codep[-1])
   16352 	{
   16353 	case 0x6f:	/* outsw/outsl */
   16354 	  intel_operand_size (z_mode, sizeflag);
   16355 	  break;
   16356 	case 0xa5:	/* movsw/movsl/movsq */
   16357 	case 0xa7:	/* cmpsw/cmpsl/cmpsq */
   16358 	case 0xad:	/* lodsw/lodsl/lodsq */
   16359 	  intel_operand_size (v_mode, sizeflag);
   16360 	  break;
   16361 	default:
   16362 	  intel_operand_size (b_mode, sizeflag);
   16363 	}
   16364     }
   16365   /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
   16366      default segment register DS is printed.  */
   16367   if (!active_seg_prefix)
   16368     active_seg_prefix = PREFIX_DS;
   16369   append_seg ();
   16370   ptr_reg (code, sizeflag);
   16371 }
   16372 
   16373 static void
   16374 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
   16375 {
   16376   int add;
   16377   if (rex & REX_R)
   16378     {
   16379       USED_REX (REX_R);
   16380       add = 8;
   16381     }
   16382   else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
   16383     {
   16384       all_prefixes[last_lock_prefix] = 0;
   16385       used_prefixes |= PREFIX_LOCK;
   16386       add = 8;
   16387     }
   16388   else
   16389     add = 0;
   16390   sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
   16391   oappend_maybe_intel (scratchbuf);
   16392 }
   16393 
   16394 static void
   16395 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
   16396 {
   16397   int add;
   16398   USED_REX (REX_R);
   16399   if (rex & REX_R)
   16400     add = 8;
   16401   else
   16402     add = 0;
   16403   if (intel_syntax)
   16404     sprintf (scratchbuf, "db%d", modrm.reg + add);
   16405   else
   16406     sprintf (scratchbuf, "%%db%d", modrm.reg + add);
   16407   oappend (scratchbuf);
   16408 }
   16409 
   16410 static void
   16411 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
   16412 {
   16413   sprintf (scratchbuf, "%%tr%d", modrm.reg);
   16414   oappend_maybe_intel (scratchbuf);
   16415 }
   16416 
   16417 static void
   16418 OP_R (int bytemode, int sizeflag)
   16419 {
   16420   /* Skip mod/rm byte.  */
   16421   MODRM_CHECK;
   16422   codep++;
   16423   OP_E_register (bytemode, sizeflag);
   16424 }
   16425 
   16426 static void
   16427 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
   16428 {
   16429   int reg = modrm.reg;
   16430   const char **names;
   16431 
   16432   used_prefixes |= (prefixes & PREFIX_DATA);
   16433   if (prefixes & PREFIX_DATA)
   16434     {
   16435       names = names_xmm;
   16436       USED_REX (REX_R);
   16437       if (rex & REX_R)
   16438 	reg += 8;
   16439     }
   16440   else
   16441     names = names_mm;
   16442   oappend (names[reg]);
   16443 }
   16444 
   16445 static void
   16446 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
   16447 {
   16448   int reg = modrm.reg;
   16449   const char **names;
   16450 
   16451   USED_REX (REX_R);
   16452   if (rex & REX_R)
   16453     reg += 8;
   16454   if (vex.evex)
   16455     {
   16456       if (!vex.r)
   16457 	reg += 16;
   16458     }
   16459 
   16460   if (need_vex
   16461       && bytemode != xmm_mode
   16462       && bytemode != xmmq_mode
   16463       && bytemode != evex_half_bcst_xmmq_mode
   16464       && bytemode != ymm_mode
   16465       && bytemode != scalar_mode)
   16466     {
   16467       switch (vex.length)
   16468 	{
   16469 	case 128:
   16470 	  names = names_xmm;
   16471 	  break;
   16472 	case 256:
   16473 	  if (vex.w
   16474 	      || (bytemode != vex_vsib_q_w_dq_mode
   16475 		  && bytemode != vex_vsib_q_w_d_mode))
   16476 	    names = names_ymm;
   16477 	  else
   16478 	    names = names_xmm;
   16479 	  break;
   16480 	case 512:
   16481 	  names = names_zmm;
   16482 	  break;
   16483 	default:
   16484 	  abort ();
   16485 	}
   16486     }
   16487   else if (bytemode == xmmq_mode
   16488 	   || bytemode == evex_half_bcst_xmmq_mode)
   16489     {
   16490       switch (vex.length)
   16491 	{
   16492 	case 128:
   16493 	case 256:
   16494 	  names = names_xmm;
   16495 	  break;
   16496 	case 512:
   16497 	  names = names_ymm;
   16498 	  break;
   16499 	default:
   16500 	  abort ();
   16501 	}
   16502     }
   16503   else if (bytemode == ymm_mode)
   16504     names = names_ymm;
   16505   else
   16506     names = names_xmm;
   16507   oappend (names[reg]);
   16508 }
   16509 
   16510 static void
   16511 OP_EM (int bytemode, int sizeflag)
   16512 {
   16513   int reg;
   16514   const char **names;
   16515 
   16516   if (modrm.mod != 3)
   16517     {
   16518       if (intel_syntax
   16519 	  && (bytemode == v_mode || bytemode == v_swap_mode))
   16520 	{
   16521 	  bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
   16522 	  used_prefixes |= (prefixes & PREFIX_DATA);
   16523 	}
   16524       OP_E (bytemode, sizeflag);
   16525       return;
   16526     }
   16527 
   16528   if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
   16529     swap_operand ();
   16530 
   16531   /* Skip mod/rm byte.  */
   16532   MODRM_CHECK;
   16533   codep++;
   16534   used_prefixes |= (prefixes & PREFIX_DATA);
   16535   reg = modrm.rm;
   16536   if (prefixes & PREFIX_DATA)
   16537     {
   16538       names = names_xmm;
   16539       USED_REX (REX_B);
   16540       if (rex & REX_B)
   16541 	reg += 8;
   16542     }
   16543   else
   16544     names = names_mm;
   16545   oappend (names[reg]);
   16546 }
   16547 
   16548 /* cvt* are the only instructions in sse2 which have
   16549    both SSE and MMX operands and also have 0x66 prefix
   16550    in their opcode. 0x66 was originally used to differentiate
   16551    between SSE and MMX instruction(operands). So we have to handle the
   16552    cvt* separately using OP_EMC and OP_MXC */
   16553 static void
   16554 OP_EMC (int bytemode, int sizeflag)
   16555 {
   16556   if (modrm.mod != 3)
   16557     {
   16558       if (intel_syntax && bytemode == v_mode)
   16559 	{
   16560 	  bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
   16561 	  used_prefixes |= (prefixes & PREFIX_DATA);
   16562 	}
   16563       OP_E (bytemode, sizeflag);
   16564       return;
   16565     }
   16566 
   16567   /* Skip mod/rm byte.  */
   16568   MODRM_CHECK;
   16569   codep++;
   16570   used_prefixes |= (prefixes & PREFIX_DATA);
   16571   oappend (names_mm[modrm.rm]);
   16572 }
   16573 
   16574 static void
   16575 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
   16576 {
   16577   used_prefixes |= (prefixes & PREFIX_DATA);
   16578   oappend (names_mm[modrm.reg]);
   16579 }
   16580 
   16581 static void
   16582 OP_EX (int bytemode, int sizeflag)
   16583 {
   16584   int reg;
   16585   const char **names;
   16586 
   16587   /* Skip mod/rm byte.  */
   16588   MODRM_CHECK;
   16589   codep++;
   16590 
   16591   if (modrm.mod != 3)
   16592     {
   16593       OP_E_memory (bytemode, sizeflag);
   16594       return;
   16595     }
   16596 
   16597   reg = modrm.rm;
   16598   USED_REX (REX_B);
   16599   if (rex & REX_B)
   16600     reg += 8;
   16601   if (vex.evex)
   16602     {
   16603       USED_REX (REX_X);
   16604       if ((rex & REX_X))
   16605 	reg += 16;
   16606     }
   16607 
   16608   if ((sizeflag & SUFFIX_ALWAYS)
   16609       && (bytemode == x_swap_mode
   16610 	  || bytemode == d_swap_mode
   16611 	  || bytemode == dqw_swap_mode
   16612 	  || bytemode == d_scalar_swap_mode
   16613 	  || bytemode == q_swap_mode
   16614 	  || bytemode == q_scalar_swap_mode))
   16615     swap_operand ();
   16616 
   16617   if (need_vex
   16618       && bytemode != xmm_mode
   16619       && bytemode != xmmdw_mode
   16620       && bytemode != xmmqd_mode
   16621       && bytemode != xmm_mb_mode
   16622       && bytemode != xmm_mw_mode
   16623       && bytemode != xmm_md_mode
   16624       && bytemode != xmm_mq_mode
   16625       && bytemode != xmm_mdq_mode
   16626       && bytemode != xmmq_mode
   16627       && bytemode != evex_half_bcst_xmmq_mode
   16628       && bytemode != ymm_mode
   16629       && bytemode != d_scalar_mode
   16630       && bytemode != d_scalar_swap_mode
   16631       && bytemode != q_scalar_mode
   16632       && bytemode != q_scalar_swap_mode
   16633       && bytemode != vex_scalar_w_dq_mode)
   16634     {
   16635       switch (vex.length)
   16636 	{
   16637 	case 128:
   16638 	  names = names_xmm;
   16639 	  break;
   16640 	case 256:
   16641 	  names = names_ymm;
   16642 	  break;
   16643 	case 512:
   16644 	  names = names_zmm;
   16645 	  break;
   16646 	default:
   16647 	  abort ();
   16648 	}
   16649     }
   16650   else if (bytemode == xmmq_mode
   16651 	   || bytemode == evex_half_bcst_xmmq_mode)
   16652     {
   16653       switch (vex.length)
   16654 	{
   16655 	case 128:
   16656 	case 256:
   16657 	  names = names_xmm;
   16658 	  break;
   16659 	case 512:
   16660 	  names = names_ymm;
   16661 	  break;
   16662 	default:
   16663 	  abort ();
   16664 	}
   16665     }
   16666   else if (bytemode == ymm_mode)
   16667     names = names_ymm;
   16668   else
   16669     names = names_xmm;
   16670   oappend (names[reg]);
   16671 }
   16672 
   16673 static void
   16674 OP_MS (int bytemode, int sizeflag)
   16675 {
   16676   if (modrm.mod == 3)
   16677     OP_EM (bytemode, sizeflag);
   16678   else
   16679     BadOp ();
   16680 }
   16681 
   16682 static void
   16683 OP_XS (int bytemode, int sizeflag)
   16684 {
   16685   if (modrm.mod == 3)
   16686     OP_EX (bytemode, sizeflag);
   16687   else
   16688     BadOp ();
   16689 }
   16690 
   16691 static void
   16692 OP_M (int bytemode, int sizeflag)
   16693 {
   16694   if (modrm.mod == 3)
   16695     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
   16696     BadOp ();
   16697   else
   16698     OP_E (bytemode, sizeflag);
   16699 }
   16700 
   16701 static void
   16702 OP_0f07 (int bytemode, int sizeflag)
   16703 {
   16704   if (modrm.mod != 3 || modrm.rm != 0)
   16705     BadOp ();
   16706   else
   16707     OP_E (bytemode, sizeflag);
   16708 }
   16709 
   16710 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
   16711    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
   16712 
   16713 static void
   16714 NOP_Fixup1 (int bytemode, int sizeflag)
   16715 {
   16716   if ((prefixes & PREFIX_DATA) != 0
   16717       || (rex != 0
   16718 	  && rex != 0x48
   16719 	  && address_mode == mode_64bit))
   16720     OP_REG (bytemode, sizeflag);
   16721   else
   16722     strcpy (obuf, "nop");
   16723 }
   16724 
   16725 static void
   16726 NOP_Fixup2 (int bytemode, int sizeflag)
   16727 {
   16728   if ((prefixes & PREFIX_DATA) != 0
   16729       || (rex != 0
   16730 	  && rex != 0x48
   16731 	  && address_mode == mode_64bit))
   16732     OP_IMREG (bytemode, sizeflag);
   16733 }
   16734 
   16735 static const char *const Suffix3DNow[] = {
   16736 /* 00 */	NULL,		NULL,		NULL,		NULL,
   16737 /* 04 */	NULL,		NULL,		NULL,		NULL,
   16738 /* 08 */	NULL,		NULL,		NULL,		NULL,
   16739 /* 0C */	"pi2fw",	"pi2fd",	NULL,		NULL,
   16740 /* 10 */	NULL,		NULL,		NULL,		NULL,
   16741 /* 14 */	NULL,		NULL,		NULL,		NULL,
   16742 /* 18 */	NULL,		NULL,		NULL,		NULL,
   16743 /* 1C */	"pf2iw",	"pf2id",	NULL,		NULL,
   16744 /* 20 */	NULL,		NULL,		NULL,		NULL,
   16745 /* 24 */	NULL,		NULL,		NULL,		NULL,
   16746 /* 28 */	NULL,		NULL,		NULL,		NULL,
   16747 /* 2C */	NULL,		NULL,		NULL,		NULL,
   16748 /* 30 */	NULL,		NULL,		NULL,		NULL,
   16749 /* 34 */	NULL,		NULL,		NULL,		NULL,
   16750 /* 38 */	NULL,		NULL,		NULL,		NULL,
   16751 /* 3C */	NULL,		NULL,		NULL,		NULL,
   16752 /* 40 */	NULL,		NULL,		NULL,		NULL,
   16753 /* 44 */	NULL,		NULL,		NULL,		NULL,
   16754 /* 48 */	NULL,		NULL,		NULL,		NULL,
   16755 /* 4C */	NULL,		NULL,		NULL,		NULL,
   16756 /* 50 */	NULL,		NULL,		NULL,		NULL,
   16757 /* 54 */	NULL,		NULL,		NULL,		NULL,
   16758 /* 58 */	NULL,		NULL,		NULL,		NULL,
   16759 /* 5C */	NULL,		NULL,		NULL,		NULL,
   16760 /* 60 */	NULL,		NULL,		NULL,		NULL,
   16761 /* 64 */	NULL,		NULL,		NULL,		NULL,
   16762 /* 68 */	NULL,		NULL,		NULL,		NULL,
   16763 /* 6C */	NULL,		NULL,		NULL,		NULL,
   16764 /* 70 */	NULL,		NULL,		NULL,		NULL,
   16765 /* 74 */	NULL,		NULL,		NULL,		NULL,
   16766 /* 78 */	NULL,		NULL,		NULL,		NULL,
   16767 /* 7C */	NULL,		NULL,		NULL,		NULL,
   16768 /* 80 */	NULL,		NULL,		NULL,		NULL,
   16769 /* 84 */	NULL,		NULL,		NULL,		NULL,
   16770 /* 88 */	NULL,		NULL,		"pfnacc",	NULL,
   16771 /* 8C */	NULL,		NULL,		"pfpnacc",	NULL,
   16772 /* 90 */	"pfcmpge",	NULL,		NULL,		NULL,
   16773 /* 94 */	"pfmin",	NULL,		"pfrcp",	"pfrsqrt",
   16774 /* 98 */	NULL,		NULL,		"pfsub",	NULL,
   16775 /* 9C */	NULL,		NULL,		"pfadd",	NULL,
   16776 /* A0 */	"pfcmpgt",	NULL,		NULL,		NULL,
   16777 /* A4 */	"pfmax",	NULL,		"pfrcpit1",	"pfrsqit1",
   16778 /* A8 */	NULL,		NULL,		"pfsubr",	NULL,
   16779 /* AC */	NULL,		NULL,		"pfacc",	NULL,
   16780 /* B0 */	"pfcmpeq",	NULL,		NULL,		NULL,
   16781 /* B4 */	"pfmul",	NULL,		"pfrcpit2",	"pmulhrw",
   16782 /* B8 */	NULL,		NULL,		NULL,		"pswapd",
   16783 /* BC */	NULL,		NULL,		NULL,		"pavgusb",
   16784 /* C0 */	NULL,		NULL,		NULL,		NULL,
   16785 /* C4 */	NULL,		NULL,		NULL,		NULL,
   16786 /* C8 */	NULL,		NULL,		NULL,		NULL,
   16787 /* CC */	NULL,		NULL,		NULL,		NULL,
   16788 /* D0 */	NULL,		NULL,		NULL,		NULL,
   16789 /* D4 */	NULL,		NULL,		NULL,		NULL,
   16790 /* D8 */	NULL,		NULL,		NULL,		NULL,
   16791 /* DC */	NULL,		NULL,		NULL,		NULL,
   16792 /* E0 */	NULL,		NULL,		NULL,		NULL,
   16793 /* E4 */	NULL,		NULL,		NULL,		NULL,
   16794 /* E8 */	NULL,		NULL,		NULL,		NULL,
   16795 /* EC */	NULL,		NULL,		NULL,		NULL,
   16796 /* F0 */	NULL,		NULL,		NULL,		NULL,
   16797 /* F4 */	NULL,		NULL,		NULL,		NULL,
   16798 /* F8 */	NULL,		NULL,		NULL,		NULL,
   16799 /* FC */	NULL,		NULL,		NULL,		NULL,
   16800 };
   16801 
   16802 static void
   16803 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
   16804 {
   16805   const char *mnemonic;
   16806 
   16807   FETCH_DATA (the_info, codep + 1);
   16808   /* AMD 3DNow! instructions are specified by an opcode suffix in the
   16809      place where an 8-bit immediate would normally go.  ie. the last
   16810      byte of the instruction.  */
   16811   obufp = mnemonicendp;
   16812   mnemonic = Suffix3DNow[*codep++ & 0xff];
   16813   if (mnemonic)
   16814     oappend (mnemonic);
   16815   else
   16816     {
   16817       /* Since a variable sized modrm/sib chunk is between the start
   16818 	 of the opcode (0x0f0f) and the opcode suffix, we need to do
   16819 	 all the modrm processing first, and don't know until now that
   16820 	 we have a bad opcode.  This necessitates some cleaning up.  */
   16821       op_out[0][0] = '\0';
   16822       op_out[1][0] = '\0';
   16823       BadOp ();
   16824     }
   16825   mnemonicendp = obufp;
   16826 }
   16827 
   16828 static struct op simd_cmp_op[] =
   16829 {
   16830   { STRING_COMMA_LEN ("eq") },
   16831   { STRING_COMMA_LEN ("lt") },
   16832   { STRING_COMMA_LEN ("le") },
   16833   { STRING_COMMA_LEN ("unord") },
   16834   { STRING_COMMA_LEN ("neq") },
   16835   { STRING_COMMA_LEN ("nlt") },
   16836   { STRING_COMMA_LEN ("nle") },
   16837   { STRING_COMMA_LEN ("ord") }
   16838 };
   16839 
   16840 static void
   16841 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
   16842 {
   16843   unsigned int cmp_type;
   16844 
   16845   FETCH_DATA (the_info, codep + 1);
   16846   cmp_type = *codep++ & 0xff;
   16847   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
   16848     {
   16849       char suffix [3];
   16850       char *p = mnemonicendp - 2;
   16851       suffix[0] = p[0];
   16852       suffix[1] = p[1];
   16853       suffix[2] = '\0';
   16854       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
   16855       mnemonicendp += simd_cmp_op[cmp_type].len;
   16856     }
   16857   else
   16858     {
   16859       /* We have a reserved extension byte.  Output it directly.  */
   16860       scratchbuf[0] = '$';
   16861       print_operand_value (scratchbuf + 1, 1, cmp_type);
   16862       oappend_maybe_intel (scratchbuf);
   16863       scratchbuf[0] = '\0';
   16864     }
   16865 }
   16866 
   16867 static void
   16868 OP_Mwaitx (int bytemode ATTRIBUTE_UNUSED,
   16869 	  int sizeflag ATTRIBUTE_UNUSED)
   16870 {
   16871   /* mwaitx %eax,%ecx,%ebx */
   16872   if (!intel_syntax)
   16873     {
   16874       const char **names = (address_mode == mode_64bit
   16875 			    ? names64 : names32);
   16876       strcpy (op_out[0], names[0]);
   16877       strcpy (op_out[1], names[1]);
   16878       strcpy (op_out[2], names[3]);
   16879       two_source_ops = 1;
   16880     }
   16881   /* Skip mod/rm byte.  */
   16882   MODRM_CHECK;
   16883   codep++;
   16884 }
   16885 
   16886 static void
   16887 OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
   16888 	  int sizeflag ATTRIBUTE_UNUSED)
   16889 {
   16890   /* mwait %eax,%ecx  */
   16891   if (!intel_syntax)
   16892     {
   16893       const char **names = (address_mode == mode_64bit
   16894 			    ? names64 : names32);
   16895       strcpy (op_out[0], names[0]);
   16896       strcpy (op_out[1], names[1]);
   16897       two_source_ops = 1;
   16898     }
   16899   /* Skip mod/rm byte.  */
   16900   MODRM_CHECK;
   16901   codep++;
   16902 }
   16903 
   16904 static void
   16905 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
   16906 	    int sizeflag ATTRIBUTE_UNUSED)
   16907 {
   16908   /* monitor %eax,%ecx,%edx"  */
   16909   if (!intel_syntax)
   16910     {
   16911       const char **op1_names;
   16912       const char **names = (address_mode == mode_64bit
   16913 			    ? names64 : names32);
   16914 
   16915       if (!(prefixes & PREFIX_ADDR))
   16916 	op1_names = (address_mode == mode_16bit
   16917 		     ? names16 : names);
   16918       else
   16919 	{
   16920 	  /* Remove "addr16/addr32".  */
   16921 	  all_prefixes[last_addr_prefix] = 0;
   16922 	  op1_names = (address_mode != mode_32bit
   16923 		       ? names32 : names16);
   16924 	  used_prefixes |= PREFIX_ADDR;
   16925 	}
   16926       strcpy (op_out[0], op1_names[0]);
   16927       strcpy (op_out[1], names[1]);
   16928       strcpy (op_out[2], names[2]);
   16929       two_source_ops = 1;
   16930     }
   16931   /* Skip mod/rm byte.  */
   16932   MODRM_CHECK;
   16933   codep++;
   16934 }
   16935 
   16936 static void
   16937 BadOp (void)
   16938 {
   16939   /* Throw away prefixes and 1st. opcode byte.  */
   16940   codep = insn_codep + 1;
   16941   oappend ("(bad)");
   16942 }
   16943 
   16944 static void
   16945 REP_Fixup (int bytemode, int sizeflag)
   16946 {
   16947   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
   16948      lods and stos.  */
   16949   if (prefixes & PREFIX_REPZ)
   16950     all_prefixes[last_repz_prefix] = REP_PREFIX;
   16951 
   16952   switch (bytemode)
   16953     {
   16954     case al_reg:
   16955     case eAX_reg:
   16956     case indir_dx_reg:
   16957       OP_IMREG (bytemode, sizeflag);
   16958       break;
   16959     case eDI_reg:
   16960       OP_ESreg (bytemode, sizeflag);
   16961       break;
   16962     case eSI_reg:
   16963       OP_DSreg (bytemode, sizeflag);
   16964       break;
   16965     default:
   16966       abort ();
   16967       break;
   16968     }
   16969 }
   16970 
   16971 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
   16972    "bnd".  */
   16973 
   16974 static void
   16975 BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
   16976 {
   16977   if (prefixes & PREFIX_REPNZ)
   16978     all_prefixes[last_repnz_prefix] = BND_PREFIX;
   16979 }
   16980 
   16981 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
   16982    "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
   16983  */
   16984 
   16985 static void
   16986 HLE_Fixup1 (int bytemode, int sizeflag)
   16987 {
   16988   if (modrm.mod != 3
   16989       && (prefixes & PREFIX_LOCK) != 0)
   16990     {
   16991       if (prefixes & PREFIX_REPZ)
   16992 	all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
   16993       if (prefixes & PREFIX_REPNZ)
   16994 	all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
   16995     }
   16996 
   16997   OP_E (bytemode, sizeflag);
   16998 }
   16999 
   17000 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
   17001    "xacquire"/"xrelease" for memory operand.  No check for LOCK prefix.
   17002  */
   17003 
   17004 static void
   17005 HLE_Fixup2 (int bytemode, int sizeflag)
   17006 {
   17007   if (modrm.mod != 3)
   17008     {
   17009       if (prefixes & PREFIX_REPZ)
   17010 	all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
   17011       if (prefixes & PREFIX_REPNZ)
   17012 	all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
   17013     }
   17014 
   17015   OP_E (bytemode, sizeflag);
   17016 }
   17017 
   17018 /* Similar to OP_E.  But the 0xf3 prefixes should be displayed as
   17019    "xrelease" for memory operand.  No check for LOCK prefix.   */
   17020 
   17021 static void
   17022 HLE_Fixup3 (int bytemode, int sizeflag)
   17023 {
   17024   if (modrm.mod != 3
   17025       && last_repz_prefix > last_repnz_prefix
   17026       && (prefixes & PREFIX_REPZ) != 0)
   17027     all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
   17028 
   17029   OP_E (bytemode, sizeflag);
   17030 }
   17031 
   17032 static void
   17033 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
   17034 {
   17035   USED_REX (REX_W);
   17036   if (rex & REX_W)
   17037     {
   17038       /* Change cmpxchg8b to cmpxchg16b.  */
   17039       char *p = mnemonicendp - 2;
   17040       mnemonicendp = stpcpy (p, "16b");
   17041       bytemode = o_mode;
   17042     }
   17043   else if ((prefixes & PREFIX_LOCK) != 0)
   17044     {
   17045       if (prefixes & PREFIX_REPZ)
   17046 	all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
   17047       if (prefixes & PREFIX_REPNZ)
   17048 	all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
   17049     }
   17050 
   17051   OP_M (bytemode, sizeflag);
   17052 }
   17053 
   17054 static void
   17055 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
   17056 {
   17057   const char **names;
   17058 
   17059   if (need_vex)
   17060     {
   17061       switch (vex.length)
   17062 	{
   17063 	case 128:
   17064 	  names = names_xmm;
   17065 	  break;
   17066 	case 256:
   17067 	  names = names_ymm;
   17068 	  break;
   17069 	default:
   17070 	  abort ();
   17071 	}
   17072     }
   17073   else
   17074     names = names_xmm;
   17075   oappend (names[reg]);
   17076 }
   17077 
   17078 static void
   17079 CRC32_Fixup (int bytemode, int sizeflag)
   17080 {
   17081   /* Add proper suffix to "crc32".  */
   17082   char *p = mnemonicendp;
   17083 
   17084   switch (bytemode)
   17085     {
   17086     case b_mode:
   17087       if (intel_syntax)
   17088 	goto skip;
   17089 
   17090       *p++ = 'b';
   17091       break;
   17092     case v_mode:
   17093       if (intel_syntax)
   17094 	goto skip;
   17095 
   17096       USED_REX (REX_W);
   17097       if (rex & REX_W)
   17098 	*p++ = 'q';
   17099       else
   17100 	{
   17101 	  if (sizeflag & DFLAG)
   17102 	    *p++ = 'l';
   17103 	  else
   17104 	    *p++ = 'w';
   17105 	  used_prefixes |= (prefixes & PREFIX_DATA);
   17106 	}
   17107       break;
   17108     default:
   17109       oappend (INTERNAL_DISASSEMBLER_ERROR);
   17110       break;
   17111     }
   17112   mnemonicendp = p;
   17113   *p = '\0';
   17114 
   17115 skip:
   17116   if (modrm.mod == 3)
   17117     {
   17118       int add;
   17119 
   17120       /* Skip mod/rm byte.  */
   17121       MODRM_CHECK;
   17122       codep++;
   17123 
   17124       USED_REX (REX_B);
   17125       add = (rex & REX_B) ? 8 : 0;
   17126       if (bytemode == b_mode)
   17127 	{
   17128 	  USED_REX (0);
   17129 	  if (rex)
   17130 	    oappend (names8rex[modrm.rm + add]);
   17131 	  else
   17132 	    oappend (names8[modrm.rm + add]);
   17133 	}
   17134       else
   17135 	{
   17136 	  USED_REX (REX_W);
   17137 	  if (rex & REX_W)
   17138 	    oappend (names64[modrm.rm + add]);
   17139 	  else if ((prefixes & PREFIX_DATA))
   17140 	    oappend (names16[modrm.rm + add]);
   17141 	  else
   17142 	    oappend (names32[modrm.rm + add]);
   17143 	}
   17144     }
   17145   else
   17146     OP_E (bytemode, sizeflag);
   17147 }
   17148 
   17149 static void
   17150 FXSAVE_Fixup (int bytemode, int sizeflag)
   17151 {
   17152   /* Add proper suffix to "fxsave" and "fxrstor".  */
   17153   USED_REX (REX_W);
   17154   if (rex & REX_W)
   17155     {
   17156       char *p = mnemonicendp;
   17157       *p++ = '6';
   17158       *p++ = '4';
   17159       *p = '\0';
   17160       mnemonicendp = p;
   17161     }
   17162   OP_M (bytemode, sizeflag);
   17163 }
   17164 
   17165 /* Display the destination register operand for instructions with
   17166    VEX. */
   17167 
   17168 static void
   17169 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
   17170 {
   17171   int reg;
   17172   const char **names;
   17173 
   17174   if (!need_vex)
   17175     abort ();
   17176 
   17177   if (!need_vex_reg)
   17178     return;
   17179 
   17180   reg = vex.register_specifier;
   17181   if (vex.evex)
   17182     {
   17183       if (!vex.v)
   17184 	reg += 16;
   17185     }
   17186 
   17187   if (bytemode == vex_scalar_mode)
   17188     {
   17189       oappend (names_xmm[reg]);
   17190       return;
   17191     }
   17192 
   17193   switch (vex.length)
   17194     {
   17195     case 128:
   17196       switch (bytemode)
   17197 	{
   17198 	case vex_mode:
   17199 	case vex128_mode:
   17200 	case vex_vsib_q_w_dq_mode:
   17201 	case vex_vsib_q_w_d_mode:
   17202 	  names = names_xmm;
   17203 	  break;
   17204 	case dq_mode:
   17205 	  if (vex.w)
   17206 	    names = names64;
   17207 	  else
   17208 	    names = names32;
   17209 	  break;
   17210 	case mask_bd_mode:
   17211 	case mask_mode:
   17212 	  names = names_mask;
   17213 	  break;
   17214 	default:
   17215 	  abort ();
   17216 	  return;
   17217 	}
   17218       break;
   17219     case 256:
   17220       switch (bytemode)
   17221 	{
   17222 	case vex_mode:
   17223 	case vex256_mode:
   17224 	  names = names_ymm;
   17225 	  break;
   17226 	case vex_vsib_q_w_dq_mode:
   17227 	case vex_vsib_q_w_d_mode:
   17228 	  names = vex.w ? names_ymm : names_xmm;
   17229 	  break;
   17230 	case mask_bd_mode:
   17231 	case mask_mode:
   17232 	  names = names_mask;
   17233 	  break;
   17234 	default:
   17235 	  abort ();
   17236 	  return;
   17237 	}
   17238       break;
   17239     case 512:
   17240       names = names_zmm;
   17241       break;
   17242     default:
   17243       abort ();
   17244       break;
   17245     }
   17246   oappend (names[reg]);
   17247 }
   17248 
   17249 /* Get the VEX immediate byte without moving codep.  */
   17250 
   17251 static unsigned char
   17252 get_vex_imm8 (int sizeflag, int opnum)
   17253 {
   17254   int bytes_before_imm = 0;
   17255 
   17256   if (modrm.mod != 3)
   17257     {
   17258       /* There are SIB/displacement bytes.  */
   17259       if ((sizeflag & AFLAG) || address_mode == mode_64bit)
   17260 	{
   17261 	  /* 32/64 bit address mode */
   17262 	  int base = modrm.rm;
   17263 
   17264 	  /* Check SIB byte.  */
   17265 	  if (base == 4)
   17266 	    {
   17267 	      FETCH_DATA (the_info, codep + 1);
   17268 	      base = *codep & 7;
   17269 	      /* When decoding the third source, don't increase
   17270 		 bytes_before_imm as this has already been incremented
   17271 		 by one in OP_E_memory while decoding the second
   17272 		 source operand.  */
   17273 	      if (opnum == 0)
   17274 		bytes_before_imm++;
   17275 	    }
   17276 
   17277 	  /* Don't increase bytes_before_imm when decoding the third source,
   17278 	     it has already been incremented by OP_E_memory while decoding
   17279 	     the second source operand.  */
   17280 	  if (opnum == 0)
   17281 	    {
   17282 	      switch (modrm.mod)
   17283 		{
   17284 		  case 0:
   17285 		    /* When modrm.rm == 5 or modrm.rm == 4 and base in
   17286 		       SIB == 5, there is a 4 byte displacement.  */
   17287 		    if (base != 5)
   17288 		      /* No displacement. */
   17289 		      break;
   17290 		  case 2:
   17291 		    /* 4 byte displacement.  */
   17292 		    bytes_before_imm += 4;
   17293 		    break;
   17294 		  case 1:
   17295 		    /* 1 byte displacement.  */
   17296 		    bytes_before_imm++;
   17297 		    break;
   17298 		}
   17299 	    }
   17300 	}
   17301       else
   17302 	{
   17303 	  /* 16 bit address mode */
   17304 	  /* Don't increase bytes_before_imm when decoding the third source,
   17305 	     it has already been incremented by OP_E_memory while decoding
   17306 	     the second source operand.  */
   17307 	  if (opnum == 0)
   17308 	    {
   17309 	      switch (modrm.mod)
   17310 		{
   17311 		case 0:
   17312 		  /* When modrm.rm == 6, there is a 2 byte displacement.  */
   17313 		  if (modrm.rm != 6)
   17314 		    /* No displacement. */
   17315 		    break;
   17316 		case 2:
   17317 		  /* 2 byte displacement.  */
   17318 		  bytes_before_imm += 2;
   17319 		  break;
   17320 		case 1:
   17321 		  /* 1 byte displacement: when decoding the third source,
   17322 		     don't increase bytes_before_imm as this has already
   17323 		     been incremented by one in OP_E_memory while decoding
   17324 		     the second source operand.  */
   17325 		  if (opnum == 0)
   17326 		    bytes_before_imm++;
   17327 
   17328 		  break;
   17329 		}
   17330 	    }
   17331 	}
   17332     }
   17333 
   17334   FETCH_DATA (the_info, codep + bytes_before_imm + 1);
   17335   return codep [bytes_before_imm];
   17336 }
   17337 
   17338 static void
   17339 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
   17340 {
   17341   const char **names;
   17342 
   17343   if (reg == -1 && modrm.mod != 3)
   17344     {
   17345       OP_E_memory (bytemode, sizeflag);
   17346       return;
   17347     }
   17348   else
   17349     {
   17350       if (reg == -1)
   17351 	{
   17352 	  reg = modrm.rm;
   17353 	  USED_REX (REX_B);
   17354 	  if (rex & REX_B)
   17355 	    reg += 8;
   17356 	}
   17357       else if (reg > 7 && address_mode != mode_64bit)
   17358 	BadOp ();
   17359     }
   17360 
   17361   switch (vex.length)
   17362     {
   17363     case 128:
   17364       names = names_xmm;
   17365       break;
   17366     case 256:
   17367       names = names_ymm;
   17368       break;
   17369     default:
   17370       abort ();
   17371     }
   17372   oappend (names[reg]);
   17373 }
   17374 
   17375 static void
   17376 OP_EX_VexImmW (int bytemode, int sizeflag)
   17377 {
   17378   int reg = -1;
   17379   static unsigned char vex_imm8;
   17380 
   17381   if (vex_w_done == 0)
   17382     {
   17383       vex_w_done = 1;
   17384 
   17385       /* Skip mod/rm byte.  */
   17386       MODRM_CHECK;
   17387       codep++;
   17388 
   17389       vex_imm8 = get_vex_imm8 (sizeflag, 0);
   17390 
   17391       if (vex.w)
   17392 	  reg = vex_imm8 >> 4;
   17393 
   17394       OP_EX_VexReg (bytemode, sizeflag, reg);
   17395     }
   17396   else if (vex_w_done == 1)
   17397     {
   17398       vex_w_done = 2;
   17399 
   17400       if (!vex.w)
   17401 	  reg = vex_imm8 >> 4;
   17402 
   17403       OP_EX_VexReg (bytemode, sizeflag, reg);
   17404     }
   17405   else
   17406     {
   17407       /* Output the imm8 directly.  */
   17408       scratchbuf[0] = '$';
   17409       print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf);
   17410       oappend_maybe_intel (scratchbuf);
   17411       scratchbuf[0] = '\0';
   17412       codep++;
   17413     }
   17414 }
   17415 
   17416 static void
   17417 OP_Vex_2src (int bytemode, int sizeflag)
   17418 {
   17419   if (modrm.mod == 3)
   17420     {
   17421       int reg = modrm.rm;
   17422       USED_REX (REX_B);
   17423       if (rex & REX_B)
   17424 	reg += 8;
   17425       oappend (names_xmm[reg]);
   17426     }
   17427   else
   17428     {
   17429       if (intel_syntax
   17430 	  && (bytemode == v_mode || bytemode == v_swap_mode))
   17431 	{
   17432 	  bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
   17433 	  used_prefixes |= (prefixes & PREFIX_DATA);
   17434 	}
   17435       OP_E (bytemode, sizeflag);
   17436     }
   17437 }
   17438 
   17439 static void
   17440 OP_Vex_2src_1 (int bytemode, int sizeflag)
   17441 {
   17442   if (modrm.mod == 3)
   17443     {
   17444       /* Skip mod/rm byte.   */
   17445       MODRM_CHECK;
   17446       codep++;
   17447     }
   17448 
   17449   if (vex.w)
   17450     oappend (names_xmm[vex.register_specifier]);
   17451   else
   17452     OP_Vex_2src (bytemode, sizeflag);
   17453 }
   17454 
   17455 static void
   17456 OP_Vex_2src_2 (int bytemode, int sizeflag)
   17457 {
   17458   if (vex.w)
   17459     OP_Vex_2src (bytemode, sizeflag);
   17460   else
   17461     oappend (names_xmm[vex.register_specifier]);
   17462 }
   17463 
   17464 static void
   17465 OP_EX_VexW (int bytemode, int sizeflag)
   17466 {
   17467   int reg = -1;
   17468 
   17469   if (!vex_w_done)
   17470     {
   17471       vex_w_done = 1;
   17472 
   17473       /* Skip mod/rm byte.  */
   17474       MODRM_CHECK;
   17475       codep++;
   17476 
   17477       if (vex.w)
   17478 	reg = get_vex_imm8 (sizeflag, 0) >> 4;
   17479     }
   17480   else
   17481     {
   17482       if (!vex.w)
   17483 	reg = get_vex_imm8 (sizeflag, 1) >> 4;
   17484     }
   17485 
   17486   OP_EX_VexReg (bytemode, sizeflag, reg);
   17487 }
   17488 
   17489 static void
   17490 VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED,
   17491 	     int sizeflag ATTRIBUTE_UNUSED)
   17492 {
   17493   /* Skip the immediate byte and check for invalid bits.  */
   17494   FETCH_DATA (the_info, codep + 1);
   17495   if (*codep++ & 0xf)
   17496     BadOp ();
   17497 }
   17498 
   17499 static void
   17500 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
   17501 {
   17502   int reg;
   17503   const char **names;
   17504 
   17505   FETCH_DATA (the_info, codep + 1);
   17506   reg = *codep++;
   17507 
   17508   if (bytemode != x_mode)
   17509     abort ();
   17510 
   17511   if (reg & 0xf)
   17512       BadOp ();
   17513 
   17514   reg >>= 4;
   17515   if (reg > 7 && address_mode != mode_64bit)
   17516     BadOp ();
   17517 
   17518   switch (vex.length)
   17519     {
   17520     case 128:
   17521       names = names_xmm;
   17522       break;
   17523     case 256:
   17524       names = names_ymm;
   17525       break;
   17526     default:
   17527       abort ();
   17528     }
   17529   oappend (names[reg]);
   17530 }
   17531 
   17532 static void
   17533 OP_XMM_VexW (int bytemode, int sizeflag)
   17534 {
   17535   /* Turn off the REX.W bit since it is used for swapping operands
   17536      now.  */
   17537   rex &= ~REX_W;
   17538   OP_XMM (bytemode, sizeflag);
   17539 }
   17540 
   17541 static void
   17542 OP_EX_Vex (int bytemode, int sizeflag)
   17543 {
   17544   if (modrm.mod != 3)
   17545     {
   17546       if (vex.register_specifier != 0)
   17547 	BadOp ();
   17548       need_vex_reg = 0;
   17549     }
   17550   OP_EX (bytemode, sizeflag);
   17551 }
   17552 
   17553 static void
   17554 OP_XMM_Vex (int bytemode, int sizeflag)
   17555 {
   17556   if (modrm.mod != 3)
   17557     {
   17558       if (vex.register_specifier != 0)
   17559 	BadOp ();
   17560       need_vex_reg = 0;
   17561     }
   17562   OP_XMM (bytemode, sizeflag);
   17563 }
   17564 
   17565 static void
   17566 VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
   17567 {
   17568   switch (vex.length)
   17569     {
   17570     case 128:
   17571       mnemonicendp = stpcpy (obuf, "vzeroupper");
   17572       break;
   17573     case 256:
   17574       mnemonicendp = stpcpy (obuf, "vzeroall");
   17575       break;
   17576     default:
   17577       abort ();
   17578     }
   17579 }
   17580 
   17581 static struct op vex_cmp_op[] =
   17582 {
   17583   { STRING_COMMA_LEN ("eq") },
   17584   { STRING_COMMA_LEN ("lt") },
   17585   { STRING_COMMA_LEN ("le") },
   17586   { STRING_COMMA_LEN ("unord") },
   17587   { STRING_COMMA_LEN ("neq") },
   17588   { STRING_COMMA_LEN ("nlt") },
   17589   { STRING_COMMA_LEN ("nle") },
   17590   { STRING_COMMA_LEN ("ord") },
   17591   { STRING_COMMA_LEN ("eq_uq") },
   17592   { STRING_COMMA_LEN ("nge") },
   17593   { STRING_COMMA_LEN ("ngt") },
   17594   { STRING_COMMA_LEN ("false") },
   17595   { STRING_COMMA_LEN ("neq_oq") },
   17596   { STRING_COMMA_LEN ("ge") },
   17597   { STRING_COMMA_LEN ("gt") },
   17598   { STRING_COMMA_LEN ("true") },
   17599   { STRING_COMMA_LEN ("eq_os") },
   17600   { STRING_COMMA_LEN ("lt_oq") },
   17601   { STRING_COMMA_LEN ("le_oq") },
   17602   { STRING_COMMA_LEN ("unord_s") },
   17603   { STRING_COMMA_LEN ("neq_us") },
   17604   { STRING_COMMA_LEN ("nlt_uq") },
   17605   { STRING_COMMA_LEN ("nle_uq") },
   17606   { STRING_COMMA_LEN ("ord_s") },
   17607   { STRING_COMMA_LEN ("eq_us") },
   17608   { STRING_COMMA_LEN ("nge_uq") },
   17609   { STRING_COMMA_LEN ("ngt_uq") },
   17610   { STRING_COMMA_LEN ("false_os") },
   17611   { STRING_COMMA_LEN ("neq_os") },
   17612   { STRING_COMMA_LEN ("ge_oq") },
   17613   { STRING_COMMA_LEN ("gt_oq") },
   17614   { STRING_COMMA_LEN ("true_us") },
   17615 };
   17616 
   17617 static void
   17618 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
   17619 {
   17620   unsigned int cmp_type;
   17621 
   17622   FETCH_DATA (the_info, codep + 1);
   17623   cmp_type = *codep++ & 0xff;
   17624   if (cmp_type < ARRAY_SIZE (vex_cmp_op))
   17625     {
   17626       char suffix [3];
   17627       char *p = mnemonicendp - 2;
   17628       suffix[0] = p[0];
   17629       suffix[1] = p[1];
   17630       suffix[2] = '\0';
   17631       sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
   17632       mnemonicendp += vex_cmp_op[cmp_type].len;
   17633     }
   17634   else
   17635     {
   17636       /* We have a reserved extension byte.  Output it directly.  */
   17637       scratchbuf[0] = '$';
   17638       print_operand_value (scratchbuf + 1, 1, cmp_type);
   17639       oappend_maybe_intel (scratchbuf);
   17640       scratchbuf[0] = '\0';
   17641     }
   17642 }
   17643 
   17644 static void
   17645 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED,
   17646 	     int sizeflag ATTRIBUTE_UNUSED)
   17647 {
   17648   unsigned int cmp_type;
   17649 
   17650   if (!vex.evex)
   17651     abort ();
   17652 
   17653   FETCH_DATA (the_info, codep + 1);
   17654   cmp_type = *codep++ & 0xff;
   17655   /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
   17656      If it's the case, print suffix, otherwise - print the immediate.  */
   17657   if (cmp_type < ARRAY_SIZE (simd_cmp_op)
   17658       && cmp_type != 3
   17659       && cmp_type != 7)
   17660     {
   17661       char suffix [3];
   17662       char *p = mnemonicendp - 2;
   17663 
   17664       /* vpcmp* can have both one- and two-lettered suffix.  */
   17665       if (p[0] == 'p')
   17666 	{
   17667 	  p++;
   17668 	  suffix[0] = p[0];
   17669 	  suffix[1] = '\0';
   17670 	}
   17671       else
   17672 	{
   17673 	  suffix[0] = p[0];
   17674 	  suffix[1] = p[1];
   17675 	  suffix[2] = '\0';
   17676 	}
   17677 
   17678       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
   17679       mnemonicendp += simd_cmp_op[cmp_type].len;
   17680     }
   17681   else
   17682     {
   17683       /* We have a reserved extension byte.  Output it directly.  */
   17684       scratchbuf[0] = '$';
   17685       print_operand_value (scratchbuf + 1, 1, cmp_type);
   17686       oappend_maybe_intel (scratchbuf);
   17687       scratchbuf[0] = '\0';
   17688     }
   17689 }
   17690 
   17691 static const struct op pclmul_op[] =
   17692 {
   17693   { STRING_COMMA_LEN ("lql") },
   17694   { STRING_COMMA_LEN ("hql") },
   17695   { STRING_COMMA_LEN ("lqh") },
   17696   { STRING_COMMA_LEN ("hqh") }
   17697 };
   17698 
   17699 static void
   17700 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
   17701 	      int sizeflag ATTRIBUTE_UNUSED)
   17702 {
   17703   unsigned int pclmul_type;
   17704 
   17705   FETCH_DATA (the_info, codep + 1);
   17706   pclmul_type = *codep++ & 0xff;
   17707   switch (pclmul_type)
   17708     {
   17709     case 0x10:
   17710       pclmul_type = 2;
   17711       break;
   17712     case 0x11:
   17713       pclmul_type = 3;
   17714       break;
   17715     default:
   17716       break;
   17717     }
   17718   if (pclmul_type < ARRAY_SIZE (pclmul_op))
   17719     {
   17720       char suffix [4];
   17721       char *p = mnemonicendp - 3;
   17722       suffix[0] = p[0];
   17723       suffix[1] = p[1];
   17724       suffix[2] = p[2];
   17725       suffix[3] = '\0';
   17726       sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
   17727       mnemonicendp += pclmul_op[pclmul_type].len;
   17728     }
   17729   else
   17730     {
   17731       /* We have a reserved extension byte.  Output it directly.  */
   17732       scratchbuf[0] = '$';
   17733       print_operand_value (scratchbuf + 1, 1, pclmul_type);
   17734       oappend_maybe_intel (scratchbuf);
   17735       scratchbuf[0] = '\0';
   17736     }
   17737 }
   17738 
   17739 static void
   17740 MOVBE_Fixup (int bytemode, int sizeflag)
   17741 {
   17742   /* Add proper suffix to "movbe".  */
   17743   char *p = mnemonicendp;
   17744 
   17745   switch (bytemode)
   17746     {
   17747     case v_mode:
   17748       if (intel_syntax)
   17749 	goto skip;
   17750 
   17751       USED_REX (REX_W);
   17752       if (sizeflag & SUFFIX_ALWAYS)
   17753 	{
   17754 	  if (rex & REX_W)
   17755 	    *p++ = 'q';
   17756 	  else
   17757 	    {
   17758 	      if (sizeflag & DFLAG)
   17759 		*p++ = 'l';
   17760 	      else
   17761 		*p++ = 'w';
   17762 	      used_prefixes |= (prefixes & PREFIX_DATA);
   17763 	    }
   17764 	}
   17765       break;
   17766     default:
   17767       oappend (INTERNAL_DISASSEMBLER_ERROR);
   17768       break;
   17769     }
   17770   mnemonicendp = p;
   17771   *p = '\0';
   17772 
   17773 skip:
   17774   OP_M (bytemode, sizeflag);
   17775 }
   17776 
   17777 static void
   17778 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
   17779 {
   17780   int reg;
   17781   const char **names;
   17782 
   17783   /* Skip mod/rm byte.  */
   17784   MODRM_CHECK;
   17785   codep++;
   17786 
   17787   if (vex.w)
   17788     names = names64;
   17789   else
   17790     names = names32;
   17791 
   17792   reg = modrm.rm;
   17793   USED_REX (REX_B);
   17794   if (rex & REX_B)
   17795     reg += 8;
   17796 
   17797   oappend (names[reg]);
   17798 }
   17799 
   17800 static void
   17801 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
   17802 {
   17803   const char **names;
   17804 
   17805   if (vex.w)
   17806     names = names64;
   17807   else
   17808     names = names32;
   17809 
   17810   oappend (names[vex.register_specifier]);
   17811 }
   17812 
   17813 static void
   17814 OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
   17815 {
   17816   if (!vex.evex
   17817       || (bytemode != mask_mode && bytemode != mask_bd_mode))
   17818     abort ();
   17819 
   17820   USED_REX (REX_R);
   17821   if ((rex & REX_R) != 0 || !vex.r)
   17822     {
   17823       BadOp ();
   17824       return;
   17825     }
   17826 
   17827   oappend (names_mask [modrm.reg]);
   17828 }
   17829 
   17830 static void
   17831 OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
   17832 {
   17833   if (!vex.evex
   17834       || (bytemode != evex_rounding_mode
   17835 	  && bytemode != evex_sae_mode))
   17836     abort ();
   17837   if (modrm.mod == 3 && vex.b)
   17838     switch (bytemode)
   17839       {
   17840       case evex_rounding_mode:
   17841 	oappend (names_rounding[vex.ll]);
   17842 	break;
   17843       case evex_sae_mode:
   17844 	oappend ("{sae}");
   17845 	break;
   17846       default:
   17847 	break;
   17848       }
   17849 }
   17850