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    Searched refs:ValueVT (Results 1 - 7 of 7) sorted by null

  /external/llvm/lib/Target/Hexagon/
HexagonISelDAGToDAG.cpp 321 EVT ValueVT = LD->getValueType(0);
322 if (ValueVT == MVT::i64 && ExtType != ISD::NON_EXTLOAD) {
326 ValueVT = MVT::i32;
330 MachineSDNode *L = CurDAG->getMachineNode(Opcode, dl, ValueVT,
342 MachineSDNode *L = CurDAG->getMachineNode(Opcode, dl, ValueVT, MVT::Other,
543 EVT ValueVT = Value.getValueType();
588 if (ST->isTruncatingStore() && ValueVT.getSizeInBits() == 64) {
    [all...]
  /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/
SelectionDAGBuilder.cpp 90 EVT PartVT, EVT ValueVT);
94 /// larger then ValueVT then AssertOp can be used to specify whether the extra
95 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
99 unsigned NumParts, EVT PartVT, EVT ValueVT,
101 if (ValueVT.isVector())
102 return getCopyFromPartsVector(DAG, DL, Parts, NumParts, PartVT, ValueVT);
110 if (ValueVT.isInteger()) {
112 unsigned ValueBits = ValueVT.getSizeInBits();
119 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits);
160 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == EVT(MVT::f64) &
    [all...]
FunctionLoweringInfo.cpp 225 EVT ValueVT = ValueVTs[Value];
226 EVT RegisterVT = TLI.getRegisterType(Ty->getContext(), ValueVT);
228 unsigned NumRegs = TLI.getNumRegisters(Ty->getContext(), ValueVT);
  /external/llvm/lib/CodeGen/SelectionDAG/
SelectionDAGBuilder.cpp 121 MVT PartVT, EVT ValueVT, const Value *V);
125 /// larger than ValueVT then AssertOp can be used to specify whether the extra
126 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
130 MVT PartVT, EVT ValueVT, const Value *V,
132 if (ValueVT.isVector())
134 PartVT, ValueVT, V);
142 if (ValueVT.isInteger()) {
144 unsigned ValueBits = ValueVT.getSizeInBits();
151 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits);
193 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == MVT::f64 &
    [all...]
LegalizeTypesGeneric.cpp 261 EVT ValueVT = LD->getValueType(0);
262 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), ValueVT);
292 if (TLI.hasBigEndianPartOrdering(ValueVT, DAG.getDataLayout()))
476 EVT ValueVT = St->getValue().getValueType();
477 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), ValueVT);
491 if (TLI.hasBigEndianPartOrdering(ValueVT, DAG.getDataLayout()))
FunctionLoweringInfo.cpp 384 EVT ValueVT = ValueVTs[Value];
385 MVT RegisterVT = TLI->getRegisterType(Ty->getContext(), ValueVT);
387 unsigned NumRegs = TLI->getNumRegisters(Ty->getContext(), ValueVT);
  /external/llvm/lib/Target/AMDGPU/
R600ISelLowering.cpp     [all...]

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