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  /external/llvm/lib/CodeGen/
CallingConvLower.cpp 215 HaveRegParm = Locs.back().isRegLoc();
221 if (Locs[I].isRegLoc())
275 bool RegLoc1 = Loc1.isRegLoc();
276 if (RegLoc1 != Loc2.isRegLoc())
  /external/llvm/lib/Target/AArch64/
AArch64CallLowering.cpp 82 assert(VA.isRegLoc() && "Not yet implemented");
  /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/
CallingConvLower.h 116 bool isRegLoc() const { return !isMem; }
121 unsigned getLocReg() const { assert(isRegLoc()); return Loc; }
  /external/llvm/include/llvm/CodeGen/
CallingConvLower.h 143 bool isRegLoc() const { return !isMem; }
148 unsigned getLocReg() const { assert(isRegLoc()); return Loc; }
  /prebuilts/clang/host/darwin-x86/clang-4053586/prebuilt_include/llvm/include/llvm/CodeGen/
CallingConvLower.h 143 bool isRegLoc() const { return !isMem; }
148 unsigned getLocReg() const { assert(isRegLoc()); return Loc; }
  /prebuilts/clang/host/darwin-x86/clang-4393122/include/llvm/CodeGen/
CallingConvLower.h 143 bool isRegLoc() const { return !isMem; }
148 unsigned getLocReg() const { assert(isRegLoc()); return Loc; }
  /prebuilts/clang/host/darwin-x86/clang-4479392/include/llvm/CodeGen/
CallingConvLower.h 143 bool isRegLoc() const { return !isMem; }
148 unsigned getLocReg() const { assert(isRegLoc()); return Loc; }
  /prebuilts/clang/host/darwin-x86/clang-4579689/include/llvm/CodeGen/
CallingConvLower.h 144 bool isRegLoc() const { return !isMem; }
149 unsigned getLocReg() const { assert(isRegLoc()); return Loc; }
  /prebuilts/clang/host/darwin-x86/clang-4630689/include/llvm/CodeGen/
CallingConvLower.h 144 bool isRegLoc() const { return !isMem; }
149 unsigned getLocReg() const { assert(isRegLoc()); return Loc; }
  /prebuilts/clang/host/darwin-x86/clang-4639204/include/llvm/CodeGen/
CallingConvLower.h 144 bool isRegLoc() const { return !isMem; }
149 unsigned getLocReg() const { assert(isRegLoc()); return Loc; }
  /prebuilts/clang/host/darwin-x86/clang-4691093/include/llvm/CodeGen/
CallingConvLower.h 144 bool isRegLoc() const { return !isMem; }
149 unsigned getLocReg() const { assert(isRegLoc()); return Loc; }
  /prebuilts/clang/host/linux-x86/clang-4053586/prebuilt_include/llvm/include/llvm/CodeGen/
CallingConvLower.h 143 bool isRegLoc() const { return !isMem; }
148 unsigned getLocReg() const { assert(isRegLoc()); return Loc; }
  /prebuilts/clang/host/linux-x86/clang-4393122/include/llvm/CodeGen/
CallingConvLower.h 143 bool isRegLoc() const { return !isMem; }
148 unsigned getLocReg() const { assert(isRegLoc()); return Loc; }
  /prebuilts/clang/host/linux-x86/clang-4479392/include/llvm/CodeGen/
CallingConvLower.h 143 bool isRegLoc() const { return !isMem; }
148 unsigned getLocReg() const { assert(isRegLoc()); return Loc; }
  /prebuilts/clang/host/linux-x86/clang-4579689/include/llvm/CodeGen/
CallingConvLower.h 144 bool isRegLoc() const { return !isMem; }
149 unsigned getLocReg() const { assert(isRegLoc()); return Loc; }
  /prebuilts/clang/host/linux-x86/clang-4630689/include/llvm/CodeGen/
CallingConvLower.h 144 bool isRegLoc() const { return !isMem; }
149 unsigned getLocReg() const { assert(isRegLoc()); return Loc; }
  /prebuilts/clang/host/linux-x86/clang-4639204/include/llvm/CodeGen/
CallingConvLower.h 144 bool isRegLoc() const { return !isMem; }
149 unsigned getLocReg() const { assert(isRegLoc()); return Loc; }
  /prebuilts/clang/host/linux-x86/clang-4691093/include/llvm/CodeGen/
CallingConvLower.h 144 bool isRegLoc() const { return !isMem; }
149 unsigned getLocReg() const { assert(isRegLoc()); return Loc; }
  /external/swiftshader/third_party/LLVM/lib/Target/SystemZ/
SystemZISelLowering.cpp 308 if (VA.isRegLoc()) {
428 if (VA.isRegLoc()) {
574 if (RVLocs[i].isRegLoc())
584 assert(VA.isRegLoc() && "Can only return in registers!");
    [all...]
  /external/swiftshader/third_party/LLVM/lib/Target/Sparc/
SparcISelLowering.cpp 103 if (RVLocs[i].isRegLoc())
112 assert(VA.isRegLoc() && "Can only return in registers!");
183 if (VA.isRegLoc()) {
478 if (VA.isRegLoc()) {
482 if (NextVA.isRegLoc()) {
515 if (VA.isRegLoc()) {
    [all...]
  /external/swiftshader/third_party/LLVM/lib/Target/MBlaze/
MBlazeISelLowering.cpp 741 if (VA.isRegLoc()) {
    [all...]
  /external/llvm/lib/Target/BPF/
BPFISelLowering.cpp 172 if (VA.isRegLoc()) {
290 if (VA.isRegLoc())
373 assert(VA.isRegLoc() && "Can only return in registers!");
  /external/swiftshader/third_party/LLVM/lib/Target/Blackfin/
BlackfinISelLowering.cpp 184 if (VA.isRegLoc()) {
252 assert(VA.isRegLoc() && "Can only return in registers!");
329 if (VA.isRegLoc()) {
  /external/swiftshader/third_party/LLVM/lib/Target/MSP430/
MSP430ISelLowering.cpp 324 if (VA.isRegLoc()) {
409 if (RVLocs[i].isRegLoc())
418 assert(VA.isRegLoc() && "Can only return in registers!");
491 if (VA.isRegLoc()) {
    [all...]
  /external/llvm/lib/Target/XCore/
XCoreISelLowering.cpp     [all...]

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