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  /external/valgrind/memcheck/tests/amd64/
sse_memory.c 276 TEST_INSN( &AllMask, 16,cvtdq2ps)
  /external/libyuv/files/source/
row_win.cc     [all...]
row_gcc.cc     [all...]
  /external/libvpx/libvpx/third_party/libyuv/source/
row_win.cc     [all...]
row_gcc.cc     [all...]
  /external/llvm/test/CodeGen/X86/
sse2-intrinsics-x86.ll 184 ; SSE-NEXT: cvtdq2ps %xmm0, %xmm0
191 %res = call <4 x float> @llvm.x86.sse2.cvtdq2ps(<4 x i32> %a0) ; <<4 x float>> [#uses=1]
194 declare <4 x float> @llvm.x86.sse2.cvtdq2ps(<4 x i32>) nounwind readnone
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  /external/mesa3d/src/gallium/drivers/swr/rasterizer/core/
format_types.h 708 //asm("cvtdq2ps %1, %0" : "=x" (ret) : "x" (ret));
823 //asm("cvtdq2ps %1, %0" : "=x" (result) : "x" (result));
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  /external/swiftshader/third_party/subzero/src/
IceAssemblerX86Base.h 464 void cvtdq2ps(Type, XmmRegister dst, XmmRegister src);
465 void cvtdq2ps(Type, XmmRegister dst, const Address &src);
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IceAssemblerX86BaseImpl.h 2000 void AssemblerX86Base<TraitsType>::cvtdq2ps(Type \/* Ignore *\/, XmmRegister dst, function in class:Ice::X86NAMESPACE::AssemblerX86Base
2010 void AssemblerX86Base<TraitsType>::cvtdq2ps(Type \/* Ignore *\/, XmmRegister dst, function in class:Ice::X86NAMESPACE::AssemblerX86Base
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  /art/compiler/utils/x86/
assembler_x86.h 464 void cvtdq2ps(XmmRegister dst, XmmRegister src);
assembler_x86.cc 988 void X86Assembler::cvtdq2ps(XmmRegister dst, XmmRegister src) { function in class:art::x86::X86Assembler
    [all...]
  /art/compiler/utils/x86_64/
assembler_x86_64_test.cc     [all...]
assembler_x86_64.h 508 void cvtdq2ps(XmmRegister dst, XmmRegister src);
    [all...]
  /toolchain/binutils/binutils-2.27/gas/testsuite/gas/i386/
sse2.d 133 [ ]*[a-f0-9]+: 0f 5b c8 cvtdq2ps %xmm0,%xmm1
  /external/valgrind/none/tests/amd64/
insn_sse2.def 49 cvtdq2ps xmm.sd[1234,5678,-1234,-5678] xmm.ps[0.0,0.0,0.0,0.0] => 1.ps[1234.0,5678.0,-1234.0,-5678.0]
50 cvtdq2ps m128.sd[1234,5678,-1234,-5678] xmm.ps[0.0,0.0,0.0,0.0] => 1.ps[1234.0,5678.0,-1234.0,-5678.0]
    [all...]
  /external/valgrind/none/tests/x86/
insn_sse2.def 49 cvtdq2ps xmm.sd[1234,5678,-1234,-5678] xmm.ps[0.0,0.0,0.0,0.0] => 1.ps[1234.0,5678.0,-1234.0,-5678.0]
50 cvtdq2ps m128.sd[1234,5678,-1234,-5678] xmm.ps[0.0,0.0,0.0,0.0] => 1.ps[1234.0,5678.0,-1234.0,-5678.0]
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  /external/llvm/test/MC/X86/
x86-32-coverage.s     [all...]
  /external/elfutils/tests/
testfile44.expect.bz2 
  /art/compiler/optimizing/
code_generator_vector_x86.cc 283 __ cvtdq2ps(dst, src);
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code_generator_vector_x86_64.cc 266 __ cvtdq2ps(dst, src);
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  /external/swiftshader/third_party/subzero/tests_lit/llvm2ice_tests/
vector-cast.ll 826 ; X8632: cvtdq2ps
  /external/v8/src/x64/
assembler-x64.cc 4488 void Assembler::cvtdq2ps(XMMRegister dst, XMMRegister src) { function in class:v8::internal::Assembler
4496 void Assembler::cvtdq2ps(XMMRegister dst, const Operand& src) { function in class:v8::internal::Assembler
    [all...]
assembler-x64.h     [all...]
  /art/disassembler/
disassembler_x86.cc 788 opcode1 = "cvtdq2ps";
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  /external/clang/test/CodeGen/
sse2-builtins.c 461 // CHECK: call <4 x float> @llvm.x86.sse2.cvtdq2ps(<4 x i32> %{{.*}})
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