| /device/linaro/bootloader/arm-trusted-firmware/plat/arm/common/ |
| arm_bl2u_setup.c | 44 * In case of ARM FVP platforms x1 is not used.
|
| /device/linaro/bootloader/arm-trusted-firmware/plat/arm/css/common/ |
| css_bl2u_setup.c | 21 * In case of ARM FVP platforms x1 is not used.
|
| /device/linaro/bootloader/arm-trusted-firmware/plat/rockchip/common/ |
| rockchip_gicv2.c | 33 * running on FVP with VE memory map.
|
| /device/linaro/bootloader/arm-trusted-firmware/ |
| readme.rst | 116 `FVP`_\ s (64-bit host machine only):
118 NOTE: Unless otherwise stated, the FVP Version is 11.0, Build 11.0.34.
133 `FVP`_\ s (64-bit host machine only):
138 The Foundation FVP can be downloaded free of charge. The Base FVPs can be
139 licensed from ARM. See the `ARM FVP website`_.
173 the Trusted Firmware with the ARM `FVP`_\ s.
206 .. _ARM FVP website: FVP_
|
| contributing.rst | 74 the Foundation FVP. See `Running the software on FVP`_ for more information.
127 .. _Running the software on FVP: ./docs/user-guide.rst#user-content-running-the-software-on-fvp
|
| /device/linaro/bootloader/OpenPlatformPkg/Platforms/ARM/VExpress/ |
| ArmVExpress-FVP-AArch64.fdf | 193 $(DTB_DIR)/fvp-base-gicv2-psci.dtb
196 $(DTB_DIR)/fvp-base-gicv2legacy-psci.dtb
199 $(DTB_DIR)/fvp-base-gicv3-psci.dtb
202 $(DTB_DIR)/fvp-foundation-gicv2-psci.dtb
205 $(DTB_DIR)/fvp-foundation-gicv2legacy-psci.dtb
208 $(DTB_DIR)/fvp-foundation-gicv3-psci.dtb
|
| ArmVExpress-FVP-AArch64.dsc | 20 PLATFORM_NAME = ArmVExpress-FVP-AArch64
27 OUTPUT_DIRECTORY = Build/ArmVExpress-FVP-AArch64
32 FLASH_DEFINITION = OpenPlatformPkg/Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.fdf
87 gEmbeddedTokenSpaceGuid.PcdEmbeddedPrompt|"ARM-FVP"
178 # the entire FVP address space can be covered by 36 bit VAs
|
| /device/linaro/bootloader/arm-trusted-firmware/docs/ |
| reset-design.rst | 56 On both the FVP and Juno platforms, the reset vector address is not programmable
78 On both the FVP and Juno platforms, although only one core is powered up by
115 Although the ARM FVP platform does not support programming the reset base
117 ``RVBAR_EL3`` register at start-up. This feature is provided on the Base FVP only.
118 It allows the ARM FVP port to support the ``RESET_TO_BL31`` configuration, in
121 address. See the `User Guide`_ for details of running the FVP models in this way.
|
| change-log.rst | 32 ARM GIC-600 IP complies with ARM GICv3 architecture. For FVP platforms, the
41 Implemented the power management APIs for FVP.
118 - For FVP platforms, added AArch32 Trusted Board Boot support, including the
275 - TBBR, including the Firmware Update feature is now supported on FVP
278 - The version of the AEMv8 Base FVP used in this release has resolved the issue
495 - Changed FVP default interrupt driver to be the GICv3-only driver.
508 - The version of the AEMv8 Base FVP used in this release resets the model
624 enabled on FVP.
648 - The FVP and Juno ports may now use the hash of the ROTPK stored in the
659 - The version of the AEMv8 Base FVP used in this release resets the mode
[all...] |
| /device/linaro/bootloader/arm-trusted-firmware/lib/cpus/aarch64/ |
| aem_generic.S | 68 /* cpu_ops for Base AEM FVP */
73 /* cpu_ops for Foundation FVP */
|
| /device/linaro/bootloader/arm-trusted-firmware/plat/arm/board/common/drivers/norflash/ |
| norflash.c | 14 * obtained empirically from Juno. FVP implements a zero wait state NOR flash
26 * memory of juno and fvp. This memory is organized as an interleaved
|
| /device/linaro/bootloader/edk2/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/ |
| RTSM.c | 169 // Only support one cluster on all but ARMv8 FVP platform. FVP still uses CortexA9 ID.
|
| /device/linaro/bootloader/edk2/ArmPlatformPkg/Scripts/ |
| Makefile | 24 ifeq ("$(EDK2_DSC)","ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-FVP-AArch64.dsc")
26 BUILD_PATH=$(WORKSPACE)/Build/ArmVExpress-FVP-AArch64
|
| /device/linaro/bootloader/arm-trusted-firmware/lib/cpus/aarch32/ |
| aem_generic.S | 43 /* cpu_ops for Base AEM FVP */
|
| /device/linaro/bootloader/edk2/ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/ |
| PL111LcdArmVExpress.c | 265 // The FVP foundation model does not have an LCD.
266 // On the FVP models the GIC variant in encoded in bits [15:12].
267 // Note: The DVI Mode is not modelled by RTSM or FVP models.
270 // Take out the FVP GIC variant to reduce the permutations.
|
| /device/linaro/bootloader/arm-trusted-firmware/fdts/ |
| fvp-foundation-gicv2-psci.dts | 15 model = "FVP Foundation";
16 compatible = "arm,fvp-base", "arm,vexpress";
185 /include/ "fvp-foundation-motherboard.dtsi"
|
| fvp-foundation-gicv3-psci.dts | 15 model = "FVP Foundation";
16 compatible = "arm,fvp-base", "arm,vexpress";
194 /include/ "fvp-foundation-motherboard.dtsi"
|
| /device/linaro/bootloader/edk2/ArmPlatformPkg/ArmVExpressPkg/ |
| ArmVExpressPkg.dec | 55 # FVP platforms : install FDT from SemiHosting
63 # FVP platforms
74 # AArch64 FVP platforms
|
| /device/linaro/bootloader/OpenPlatformPkg/Platforms/ARM/VExpress/DeviceTree/ |
| fvp-foundation-gicv2-psci.dts | 39 model = "FVP Foundation";
40 compatible = "arm,fvp-base", "arm,vexpress";
249 /include/ "fvp-foundation-motherboard.dtsi"
|
| fvp-foundation-gicv2legacy-psci.dts | 39 model = "FVP Foundation";
40 compatible = "arm,fvp-base", "arm,vexpress";
249 /include/ "fvp-foundation-motherboard.dtsi"
|
| fvp-foundation-gicv3-psci.dts | 39 model = "FVP Foundation";
40 compatible = "arm,fvp-base", "arm,vexpress";
256 /include/ "fvp-foundation-motherboard-no_psci.dtsi"
|
| /prebuilts/go/darwin-x86/src/cmd/compile/internal/gc/ |
| mpfloat.go | 207 func fconv(fvp *Mpflt, flag FmtFlag) string {
209 return fvp.Val.Text('b', 0)
215 f := &fvp.Val
|
| /prebuilts/go/linux-x86/src/cmd/compile/internal/gc/ |
| mpfloat.go | 207 func fconv(fvp *Mpflt, flag FmtFlag) string {
209 return fvp.Val.Text('b', 0)
215 f := &fvp.Val
|
| /device/linaro/bootloader/arm-trusted-firmware/plat/arm/board/fvp/ |
| fvp_io_storage.c | 127 * FVP provides semihosting as an alternative to load images
|
| /external/clang/test/Index/ |
| complete-memfunc-cvquals.cpp | 18 smart_ptr<Foo> sf, const smart_ptr<Foo> &sfc, Foo volatile *fvp) {
25 fvp->babble();
|
