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  /device/linaro/bootloader/edk2/ArmPkg/Library/CompilerIntrinsicsLib/Arm/
moddi3.S 37 ldrd r0, [sp, #8]
udivmoddi4.S 140 ldrd r10, [sp, #8]
226 ldrd r0, [sp, #8]
  /external/libvpx/libvpx/vpx_dsp/arm/
vpx_convolve_copy_neon_asm.asm 20 ldrd r4, r5, [sp, #32]
vpx_convolve_avg_neon_asm.asm 20 ldrd r4, r5, [sp, #36]
vpx_convolve8_avg_neon_asm.asm 58 ldrd r4, r5, [sp, #32] ; filter, x0_q4
60 ldrd r6, r7, [sp, #52] ; w, h
vpx_convolve8_neon_asm.asm 58 ldrd r4, r5, [sp, #32] ; filter, x0_q4
60 ldrd r6, r7, [sp, #52] ; w, h
  /external/llvm/test/MC/ARM/
big-endian-arm-fixup.s 68 ldrd r0, r1, arm_adr_pcrel_10_unscaled_label+24
  /external/llvm/test/MC/Disassembler/ARM/
unpredictable-LDRD-arm.txt 8 # A8.6.68 LDRD (register)
  /external/swiftshader/third_party/LLVM/test/CodeGen/ARM/
fpcmp-opt.ll 40 ; FINITE: ldrd r0, r1, [r0]
  /art/runtime/base/
quasi_atomic.h 68 // With LPAE support (such as Cortex-A15) then ldrd is defined not to tear.
70 "ldrd %0, %H0, %1"
  /device/linaro/bootloader/edk2/ArmVirtPkg/PrePi/Arm/
ModuleEntryPoint.S 40 ldrd r8, r9, [r5], #8 // read offset into r8 and info into r9
65 ldrd r2, r3, [r12]
  /toolchain/binutils/binutils-2.27/gas/testsuite/gas/arm/
thumb32.s 376 ldrd r2, r3, [r5]
377 ldrd r2, [r5, #0x30]
378 ldrd r2, [r5, #-0x30]
379 ldrd r4, r5, here
810 ldrd r2, r4, [r9, #48]!
811 ldrd r2, r4, [r9, #-48]!
814 ldrd r2, r4, [r9], #48
815 ldrd r2, r4, [r9], #-48
  /external/llvm/test/CodeGen/ARM/
inlineasm-64bit.ll 59 %1 = tail call i64 asm "ldrd $0, ${0:H}, [$1]", "=r,r"(i64* %p) nounwind
65 ; CHECK: ldrd {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}
66 %1 = tail call i64 asm "ldrd ${0:Q}, ${0:R}, [$1]", "=r,r"(i64* %p) nounwind
fpcmp-opt.ll 36 ; CHECK: ldrd [[REG1:(r[0-9]+)]], [[REG2:(r[0-9]+)]], [r0]
  /bionic/libc/arch-arm/cortex-a15/bionic/
__strcpy_chk.S 85 ldrd r2, r3, [r0], #8
  /bionic/libc/arch-arm/cortex-a53/bionic/
__strcpy_chk.S 85 ldrd r2, r3, [r0], #8
  /bionic/libc/arch-arm/cortex-a7/bionic/
__strcpy_chk.S 85 ldrd r2, r3, [r0], #8
  /bionic/libc/arch-arm/denver/bionic/
__strcpy_chk.S 85 ldrd r2, r3, [r0], #8
  /bionic/libc/arch-arm/krait/bionic/
__strcpy_chk.S 85 ldrd r2, r3, [r0], #8
  /device/linaro/bootloader/edk2/ArmPlatformPkg/PrePi/Arm/
ModuleEntryPoint.S 37 ldrd r2, r3, [r1]
ModuleEntryPoint.asm 52 ldrd r2, r3, [r1]
  /external/llvm/lib/Target/ARM/MCTargetDesc/
ARMFixupKinds.h 27 // addresses used in LDRD/LDRH/LDRB/etc. instructions. All bits are encoded.
  /external/vixl/test/
test-code-generation-scopes.cc 354 __ Ldrd(aarch32::r0, aarch32::r1, 0x1234567890abcdef);
430 __ Ldrd(aarch32::r0, aarch32::r1, 0x1234567890abcdef);
709 __ Ldrd(aarch32::r0, aarch32::r1, 0x1234567890abcdef);
717 // otherwise the `Ldrd` will run out of range when we generate the `nop`
  /art/compiler/utils/
assembler_thumb_test_expected.cc.inc 190 " 58: e9d4 2303 ldrd r2, r3, [r4, #12]\n",
191 " 5c: e9d4 23ff ldrd r2, r3, [r4, #1020] ; 0x3fc\n",
193 " 64: e9d2 2300 ldrd r2, r3, [r2]\n",
195 " 6c: e9d2 2329 ldrd r2, r3, [r2, #164] ; 0xa4\n",
199 " 7a: e9d2 2300 ldrd r2, r3, [r2]\n",
203 " 88: e9d4 4500 ldrd r4, r5, [r4]\n",
  /external/vixl/src/aarch32/
macro-assembler-aarch32.cc     [all...]

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