| /art/compiler/optimizing/ |
| code_generator_mips.cc | [all...] |
| code_generator_mips64.cc | [all...] |
| /external/llvm/test/MC/Disassembler/Mips/mips32/ |
| valid-mips32.txt | 139 0x2c 0x63 0x00 0x67 # CHECK: sltiu $3, $3, 103
140 0x2f 0x38 0xc3 0x55 # CHECK: sltiu $24, $25, -15531
141 0x2f 0x39 0xc3 0x55 # CHECK: sltiu $25, $25, -15531
|
| /external/llvm/test/MC/Disassembler/Mips/mips32r2/ |
| valid-mips32r2.txt | 145 0x2c 0x63 0x00 0x67 # CHECK: sltiu $3, $3, 103
146 0x2f 0x38 0xc3 0x55 # CHECK: sltiu $24, $25, -15531
147 0x2f 0x39 0xc3 0x55 # CHECK: sltiu $25, $25, -15531
|
| /external/llvm/test/MC/Disassembler/Mips/mips32r3/ |
| valid-mips32r3.txt | 142 0x2c 0x63 0x00 0x67 # CHECK: sltiu $3, $3, 103
143 0x2f 0x38 0xc3 0x55 # CHECK: sltiu $24, $25, -15531
144 0x2f 0x39 0xc3 0x55 # CHECK: sltiu $25, $25, -15531
|
| /external/llvm/test/MC/Disassembler/Mips/mips32r5/ |
| valid-mips32r5.txt | 142 0x2c 0x63 0x00 0x67 # CHECK: sltiu $3, $3, 103
143 0x2f 0x38 0xc3 0x55 # CHECK: sltiu $24, $25, -15531
144 0x2f 0x39 0xc3 0x55 # CHECK: sltiu $25, $25, -15531
|
| /external/llvm/test/MC/Disassembler/Mips/mips64/ |
| valid-mips64.txt | 181 0x2c 0x63 0x00 0x67 # CHECK: sltiu $3, $3, 103
182 0x2f 0x38 0xc3 0x55 # CHECK: sltiu $24, $25, -15531
183 0x2f 0x39 0xc3 0x55 # CHECK: sltiu $25, $25, -15531
|
| /toolchain/binutils/binutils-2.27/gas/testsuite/gas/mips/ |
| micromips-noinsn32.d | [all...] |
| micromips-trap.d | [all...] |
| micromips-insn32.d | [all...] |
| micromips.d | [all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsScheduleP5600.td | 32 // and, lui, nor, or, slti, sltiu, sub, subu, xor
|
| MipsInstrInfo.td | [all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
| Mips64InstrInfo.td | 101 def SLTiu64 : SetCC_I<0x0b, "sltiu", setult, simm16_64, immSExt16, CPU64Regs>;
|
| /external/llvm/test/CodeGen/Mips/ |
| atomic.ll | 399 ; ALL: sltiu $2, $[[R21]], 1
490 ; ALL: sltiu $3, $[[R12]], 1
|
| /external/llvm/test/MC/Disassembler/Mips/mips4/ |
| valid-mips4.txt | 132 0x2f 0x38 0xc3 0x55 # CHECK: sltiu $24, $25, -15531
133 0x2f 0x39 0xc3 0x55 # CHECK: sltiu $25, $25, -15531
|
| /external/llvm/test/MC/Disassembler/Mips/mips64r2/ |
| valid-mips64r2.txt | 195 0x2c 0x63 0x00 0x67 # CHECK: sltiu $3, $3, 103
196 0x2f 0x38 0xc3 0x55 # CHECK: sltiu $24, $25, -15531
197 0x2f 0x39 0xc3 0x55 # CHECK: sltiu $25, $25, -15531
|
| /external/llvm/test/MC/Disassembler/Mips/mips64r3/ |
| valid-mips64r3.txt | 192 0x2c 0x63 0x00 0x67 # CHECK: sltiu $3, $3, 103
193 0x2f 0x38 0xc3 0x55 # CHECK: sltiu $24, $25, -15531
194 0x2f 0x39 0xc3 0x55 # CHECK: sltiu $25, $25, -15531
|
| /external/llvm/test/MC/Disassembler/Mips/mips64r5/ |
| valid-mips64r5.txt | 192 0x2c 0x63 0x00 0x67 # CHECK: sltiu $3, $3, 103
193 0x2f 0x38 0xc3 0x55 # CHECK: sltiu $24, $25, -15531
194 0x2f 0x39 0xc3 0x55 # CHECK: sltiu $25, $25, -15531
|
| /external/swiftshader/third_party/subzero/src/ |
| IceAssemblerMIPS32.cpp | 1010 void AssemblerMIPS32::sltiu(const Operand *OpRt, const Operand *OpRs, function in class:Ice::MIPS32::AssemblerMIPS32
[all...] |
| IceInstMIPS32.cpp | 134 template <> const char *InstMIPS32Sltiu::Opcode = "sltiu";
[all...] |
| IceInstMIPS32.h | 265 Sltiu,
[all...] |
| /external/v8/src/mips/ |
| constants-mips.h | 355 SLTIU = ((1U << 3) + 3) << kOpcodeShift,
908 OpcodeToBitNumber(SLTI) | OpcodeToBitNumber(SLTIU) |
[all...] |
| disasm-mips.cc | [all...] |
| /external/v8/src/mips64/ |
| constants-mips64.h | 326 SLTIU = ((1U << 3) + 3) << kOpcodeShift,
941 OpcodeToBitNumber(SLTIU) | OpcodeToBitNumber(ANDI) |
[all...] |
