| /external/ltp/testcases/network/stress/route/ |
| route6-redirect | 202 RC=0
204 test_body || RC=`expr $RC + 1`
207 exit $RC
|
| route4-change-dst | 270 RC=0
272 test_body 1 || RC=`expr $RC + 1` # Case of route command
273 test_body 2 || RC=`expr $RC + 1` # Case of ip command
276 exit $RC
|
| route4-ifdown | 255 RC=0
257 test_body 1 || RC=`expr $RC + 1` # Case of route command
258 test_body 2 || RC=`expr $RC + 1` # Case of ip command
261 exit $RC
|
| route4-rmmod | 274 RC=0
276 test_body 1 || RC=`expr $RC + 1` # Case of route command
277 test_body 2 || RC=`expr $RC + 1` # Case of ip command
280 exit $RC
|
| route6-change-dst | 266 RC=0
268 test_body 1 || RC=`expr $RC + 1` # Case of route command
269 test_body 2 || RC=`expr $RC + 1` # Case of ip command
272 exit $RC
|
| route6-ifdown | 253 RC=0
255 test_body 1 || RC=`expr $RC + 1` # Case of route command
256 test_body 2 || RC=`expr $RC + 1` # Case of ip command
259 exit $RC
|
| route6-rmmod | 270 RC=0
272 test_body 1 || RC=`expr $RC + 1` # Case of route command
273 test_body 2 || RC=`expr $RC + 1` # Case of ip command
276 exit $RC
|
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| Thumb2InstrInfo.h | 49 const TargetRegisterClass *RC,
55 const TargetRegisterClass *RC,
|
| /external/swiftshader/third_party/LLVM/lib/Target/CellSPU/ |
| SPURegisterInfo.h | 54 virtual unsigned getRegPressureLimit( const TargetRegisterClass *RC,
95 const TargetRegisterClass *RC,
|
| /toolchain/binutils/binutils-2.27/opcodes/ |
| arc-nps400-tbl.h | 53 { "rflt", 0x382e0000, 0xf8ff8000, ARC_OPCODE_ARC700, BITOP, NPS400, { RA, RB, RC }, { 0 }},
56 { "rflt", 0x3e2e7000, 0xfffff000, ARC_OPCODE_ARC700, BITOP, NPS400, { RA, LIMM, RC }, { 0 }},
62 { "rflt", 0x382e003e, 0xf8ff803f, ARC_OPCODE_ARC700, BITOP, NPS400, { ZA, RB, RC }, { 0 }},
65 { "rflt", 0x3e2e703e, 0xfffff03f, ARC_OPCODE_ARC700, BITOP, NPS400, { ZA, LIMM, RC }, { 0 }},
86 { "crc16", 0x38330000, 0xf8ff0000, ARC_OPCODE_ARC700, BITOP, NPS400, { RA, RB, RC }, { C_NPS_R }},
89 { "crc16", 0x3e337000, 0xffff7000, ARC_OPCODE_ARC700, BITOP, NPS400, { RA, LIMM, RC }, { C_NPS_R }},
95 { "crc16", 0x3833003e, 0xf8ff003f, ARC_OPCODE_ARC700, BITOP, NPS400, { ZA, RB, RC }, { C_NPS_R }},
98 { "crc16", 0x3e33703e, 0xffff703f, ARC_OPCODE_ARC700, BITOP, NPS400, { ZA, LIMM, RC }, { C_NPS_R }},
119 { "crc32", 0x38340000, 0xf8ff0000, ARC_OPCODE_ARC700, BITOP, NPS400, { RA, RB, RC }, { C_NPS_R }},
122 { "crc32", 0x3e347000, 0xffff7000, ARC_OPCODE_ARC700, BITOP, NPS400, { RA, LIMM, RC }, { C_NPS_R }}
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64RegisterBankInfo.h | 48 /// Get a register bank that covers \p RC.
50 /// \pre \p RC is a user-defined register class (as opposed as one
53 /// \note The mapping RC -> RegBank could be built while adding the
61 getRegBankFromRegClass(const TargetRegisterClass &RC) const override;
|
| /external/llvm/lib/Target/AMDGPU/ |
| R600RegisterInfo.h | 41 getRegClassWeight(const TargetRegisterClass *RC) const override;
|
| /external/llvm/lib/Target/X86/ |
| X86RegisterInfo.h | 71 getSubClassWithSubReg(const TargetRegisterClass *RC,
75 getLargestLegalSuperClass(const TargetRegisterClass *RC,
88 getCrossCopyRegClass(const TargetRegisterClass *RC) const override;
95 unsigned getRegPressureLimit(const TargetRegisterClass *RC,
|
| /external/ltp/testcases/kernel/hotplug/cpu_hotplug/functional/ |
| cpuhotplug07.sh | 100 RC=$?
101 echo "Offlining cpu${CPU_TO_TEST}: Return Code = ${RC}"
113 RC=$?
114 echo "Onlining cpu${CPU_TO_TEST}: Return Code = ${RC}"
|
| /external/llvm/lib/Target/Mips/ |
| MipsSEInstrInfo.cpp | 185 const TargetRegisterClass *RC, const TargetRegisterInfo *TRI,
192 if (Mips::GPR32RegClass.hasSubClassEq(RC))
194 else if (Mips::GPR64RegClass.hasSubClassEq(RC))
196 else if (Mips::ACC64RegClass.hasSubClassEq(RC))
198 else if (Mips::ACC64DSPRegClass.hasSubClassEq(RC))
200 else if (Mips::ACC128RegClass.hasSubClassEq(RC))
202 else if (Mips::DSPCCRegClass.hasSubClassEq(RC))
204 else if (Mips::FGR32RegClass.hasSubClassEq(RC))
206 else if (Mips::AFGR64RegClass.hasSubClassEq(RC))
208 else if (Mips::FGR64RegClass.hasSubClassEq(RC))
[all...] |
| /external/ltp/testcases/kernel/security/integrity/ima/tests/ |
| ima_tpm.sh | 30 # - non zero on failure. return value from commands ($RC)
80 RC=0
87 [ "${pcr}" = "${aggr}" ] || RC=$?
90 return $RC
|
| /external/llvm/lib/Target/Hexagon/ |
| BitTracker.h | 49 void put(RegisterRef RR, const RegisterCell &RC);
264 bool meet(const RegisterCell &RC, unsigned SelfR);
265 RegisterCell &insert(const RegisterCell &RC, const BitMask &M);
269 RegisterCell &cat(const RegisterCell &RC); // Concatenate.
273 bool operator== (const RegisterCell &RC) const;
274 bool operator!= (const RegisterCell &RC) const {
275 return !operator==(RC);
294 friend raw_ostream &operator<<(raw_ostream &OS, const RegisterCell &RC);
313 RegisterCell RC(Width);
315 RC.Bits[i] = BitValue::self(BitRef(Reg, i))
[all...] |
| /prebuilts/clang/host/darwin-x86/clang-4053586/prebuilt_include/llvm/include/llvm/CodeGen/ |
| ExecutionDepsFix.h | 127 const TargetRegisterClass *const RC;
170 ExecutionDepsFix(char &PassID, const TargetRegisterClass &RC)
171 : MachineFunctionPass(PassID), RC(&RC), NumRegs(RC.getNumRegs()) {}
|
| /prebuilts/clang/host/darwin-x86/clang-4393122/include/llvm/CodeGen/ |
| ExecutionDepsFix.h | 138 const TargetRegisterClass *const RC;
180 ExecutionDepsFix(char &PassID, const TargetRegisterClass &RC)
181 : MachineFunctionPass(PassID), RC(&RC), NumRegs(RC.getNumRegs()) {}
|
| /prebuilts/clang/host/darwin-x86/clang-4479392/include/llvm/CodeGen/ |
| ExecutionDepsFix.h | 138 const TargetRegisterClass *const RC;
180 ExecutionDepsFix(char &PassID, const TargetRegisterClass &RC)
181 : MachineFunctionPass(PassID), RC(&RC), NumRegs(RC.getNumRegs()) {}
|
| /prebuilts/clang/host/darwin-x86/clang-4579689/include/llvm/CodeGen/ |
| ExecutionDepsFix.h | 138 const TargetRegisterClass *const RC;
180 ExecutionDepsFix(char &PassID, const TargetRegisterClass &RC)
181 : MachineFunctionPass(PassID), RC(&RC), NumRegs(RC.getNumRegs()) {}
|
| /prebuilts/clang/host/darwin-x86/clang-4630689/include/llvm/CodeGen/ |
| ExecutionDepsFix.h | 138 const TargetRegisterClass *const RC;
180 ExecutionDepsFix(char &PassID, const TargetRegisterClass &RC)
181 : MachineFunctionPass(PassID), RC(&RC), NumRegs(RC.getNumRegs()) {}
|
| /prebuilts/clang/host/darwin-x86/clang-4639204/include/llvm/CodeGen/ |
| ExecutionDepsFix.h | 138 const TargetRegisterClass *const RC;
180 ExecutionDepsFix(char &PassID, const TargetRegisterClass &RC)
181 : MachineFunctionPass(PassID), RC(&RC), NumRegs(RC.getNumRegs()) {}
|
| /prebuilts/clang/host/darwin-x86/clang-4691093/include/llvm/CodeGen/ |
| ExecutionDepsFix.h | 138 const TargetRegisterClass *const RC;
180 ExecutionDepsFix(char &PassID, const TargetRegisterClass &RC)
181 : MachineFunctionPass(PassID), RC(&RC), NumRegs(RC.getNumRegs()) {}
|
| /prebuilts/clang/host/linux-x86/clang-4053586/prebuilt_include/llvm/include/llvm/CodeGen/ |
| ExecutionDepsFix.h | 127 const TargetRegisterClass *const RC;
170 ExecutionDepsFix(char &PassID, const TargetRegisterClass &RC)
171 : MachineFunctionPass(PassID), RC(&RC), NumRegs(RC.getNumRegs()) {}
|
