| /external/libvpx/libvpx/test/ |
| dct32x32_test.cc | 328 SSE2, Trans32x32Test,
337 SSE2, Trans32x32Test,
|
| variance_test.cc | 413 unsigned int sse1, sse2, var1, var2; local
419 stride, &sse2, use_high_bit_depth(), params_.bit_depth);
420 EXPECT_EQ(sse1, sse2) << "Error at test index: " << i;
443 unsigned int sse1, sse2; local
449 src_stride, ref_stride, &sse2, use_high_bit_depth(),
451 EXPECT_EQ(sse1, sse2) << "Error at test index: " << i;
516 unsigned int sse1, sse2; local
520 stride, &sse2, false, VPX_BITS_8);
521 EXPECT_EQ(sse1, sse2);
532 unsigned int sse2; local
646 unsigned int sse1, sse2; local
681 unsigned int sse1, sse2; local
717 uint32_t sse1, sse2; local
[all...] |
| comp_avg_pred_test.cc | 63 // The sse2 special-cases when ref width == stride, so make sure to test
169 INSTANTIATE_TEST_CASE_P(SSE2, AvgPredTest,
|
| dct_test.cc | 456 SSE2, TransDCT,
476 SSE2, TransDCT,
660 SSE2, TransHT,
732 INSTANTIATE_TEST_CASE_P(SSE2, TransWHT,
|
| lpf_test.cc | 209 << "Error: Loop8Test6Param, C output doesn't match SSE2 "
272 << "Error: Loop8Test6Param, C output doesn't match SSE2 "
335 << "Error: Loop8Test9Param, C output doesn't match SSE2 "
400 << "Error: Loop8Test9Param, C output doesn't match SSE2"
410 SSE2, Loop8Test6Param,
461 SSE2, Loop8Test6Param,
488 SSE2, Loop8Test9Param,
515 SSE2, Loop8Test9Param,
|
| vp8_fdct4x4_test.cc | 194 INSTANTIATE_TEST_CASE_P(SSE2, FdctTest,
|
| vp9_quantize_test.cc | 164 // The first 16 are skipped in the sse2 code. Do the same here to match.
434 SSE2, VP9QuantizeTest,
451 SSE2, VP9QuantizeTest,
|
| sad_test.cc | 748 INSTANTIATE_TEST_CASE_P(SSE2, SADTest, ::testing::ValuesIn(sse2_tests));
800 INSTANTIATE_TEST_CASE_P(SSE2, SADavgTest, ::testing::ValuesIn(avg_sse2_tests));
[all...] |
| vp9_intrapred_test.cc | 135 SSE2, VP9IntraPredTest,
[all...] |
| /external/fec/ |
| sse2bfly27.s | 1 /* Intel SIMD (SSE2) implementations of Viterbi ACS butterflies
8 # SSE2 (128-bit integer SIMD) version
|
| vtest615.c | 27 {"force-sse2",0,NULL,'t'},
78 Cpu_mode = SSE2;
|
| fec.h | 261 extern enum cpu_mode {UNKNOWN=0,PORT,MMX,SSE,SSE2,ALTIVEC} Cpu_mode;
|
| /external/mesa3d/src/gallium/drivers/swr/rasterizer/common/ |
| isa.hpp | 76 bool SSE2(void) { return CPU_Rep.f_1_EDX_[26]; }
|
| /external/tensorflow/tensorflow/core/platform/ |
| cpu_info.cc | 239 case SSE2: return cpuid->have_sse2_;
|
| /external/clang/lib/Basic/ |
| Targets.cpp | [all...] |
| /device/linaro/bootloader/edk2/UefiCpuPkg/Include/Register/ |
| Cpuid.h | 505 /// [Bit 26] SSE2. The processor supports the SSE2 extensions.
507 UINT32 SSE2:1;
[all...] |
| /external/libjpeg-turbo/simd/ |
| jfdctfst-sse2-64.asm | 2 ; jfdctfst.asm - fast integer FDCT (64-bit SSE2)
|
| jfdctfst-sse2.asm | 2 ; jfdctfst.asm - fast integer FDCT (SSE2)
|
| jidctflt-sse2-64.asm | 2 ; jidctflt.asm - floating-point IDCT (64-bit SSE & SSE2)
|
| jidctfst-sse2-64.asm | 2 ; jidctfst.asm - fast integer IDCT (64-bit SSE2)
|
| jidctfst-sse2.asm | 2 ; jidctfst.asm - fast integer IDCT (SSE2)
|
| /external/swiftshader/third_party/subzero/src/ |
| IceTargetLoweringX8632Traits.h | 270 // SSE2 is the PNaCl baseline instruction set.
271 SSE2 = Begin,
[all...] |
| /device/linaro/bootloader/edk2/MdeModulePkg/Universal/DebugSupportDxe/Ia32/ |
| AsmFuncs.asm | 39 ;; MMX, SSE, SSE2, etc registers. The initialization of the debugsupport driver
|
| /device/linaro/bootloader/edk2/MdeModulePkg/Universal/DebugSupportDxe/X64/ |
| AsmFuncs.asm | 36 ;; MMX, SSE, SSE2, etc registers. The initialization of the debugsupport driver
|
| /device/linaro/bootloader/edk2/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/ |
| SmiException.asm | 707 ; x87 FPU/MMX/SSE/SSE2/SSE3/SSSE3/SSE4 instructions.
|
