| /toolchain/binutils/binutils-2.27/gas/testsuite/gas/mips/ |
| fix-rm7000-1.s | 5 dmult $6,$3
9 dmult $2,$7
|
| fix-rm7000-2.s | 7 dmult $6,$3
13 dmult $6,$3
17 dmult $6,$3
23 dmult $6,$3
|
| micromips@fix-rm7000-1.d | 11 0+0002 <[^>]*> dmult a2,v1
15 0+0010 <[^>]*> dmult v0,a3
|
| micromips@fix-rm7000-2.d | 12 0+000a <[^>]*> dmult a2,v1
18 0+001e <[^>]*> dmult a2,v1
22 0+002e <[^>]*> dmult a2,v1
28 0+0046 <[^>]*> dmult a2,v1
|
| r6-64-removed.s | 5 dmult $2,$3
|
| fix-rm7000-1.d | 11 0+0004 <[^>]*> dmult a2,v1
18 0+0020 <[^>]*> dmult v0,a3
|
| vr4120-2.s | 38 dmult $4,$5
39 dmult $6,$7
50 dmult $4,$5
77 dmult $4,$5
93 dmult $4,$5
101 dmult $4,$5
125 dmult $4,$5
|
| fix-rm7000-2.d | 15 0+0018 <[^>]*> dmult a2,v1
24 0+003c <[^>]*> dmult a2,v1
34 0+0064 <[^>]*> dmult a2,v1
49 0+00a0 <[^>]*> dmult a2,v1
|
| vr4120-2.d | 40 .* <[^>]*> dmult a0,a1
42 .* <[^>]*> dmult a2,a3
52 .* <[^>]*> dmult a0,a1
83 .* <[^>]*> dmult a0,a1
103 .* <[^>]*> dmult a0,a1
113 .* <[^>]*> dmult a0,a1
143 .* <[^>]*> dmult a0,a1
|
| r6-64-removed.l | 5 .*:5: Error: opcode not supported on this processor: .* \(.*\) `dmult \$2,\$3'
|
| mul-ilocks.d | 65 0+00d8 <[^>]*> dmult a1,at
67 0+00e0 <[^>]*> dmult a1,a2
|
| mul.d | 74 0+0110 <[^>]*> dmult a1,at
77 0+0120 <[^>]*> dmult a1,a2
|
| vr4130.d | 322 .* dmult .*
803 .* dmult .*
|
| loongson-2e.s | 12 dmult.g $8, $9, $10
|
| loongson-2f.s | 12 dmult.g $8, $9, $10
|
| /external/llvm/test/MC/Mips/mips2/ |
| invalid-mips3-wrong-error.s | 9 dmult $s7,$a5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
|
| /external/llvm/test/CodeGen/Mips/ |
| mips64muldiv.ll | 14 ; ACC: dmult ${{[45]}}, ${{[45]}}
31 ; ACC: dmult $4, $[[T0]]
|
| octeon.ll | 22 ; MIPS64: dmult $4, $5
|
| /external/llvm/test/MC/Mips/ |
| do_switch3.s | 43 dmult $2, $3
|
| elf-gprel-32-64.s | 51 dmult $3, $4
|
| /external/llvm/test/CodeGen/Mips/llvm-ir/ |
| mul.ll | 200 ; M4: dmult $4, $5
203 ; 64R1-R5: dmult $4, $5
233 ; GP64-NOT-R6: dmult $4, $7
235 ; GP64-NOT-R6: dmult $5, $6
|
| /external/llvm/test/MC/Mips/mips64r6/ |
| invalid-mips3.s | 12 dmult $s7,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| invalid-mips64.s | 16 dmult $s7,$s4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/valgrind/none/tests/mips64/ |
| arithmetic_instruction.c | 10 DMULT, DMULTU, DSUB, DSUBU,
177 case DMULT:
179 TEST4("dmult $t0, $t1", reg_val1[i], reg_val1[N-i-1], t0, t1);
180 TEST4("dmult $v0, $v1", reg_val2[i], reg_val2[N-i-1], v0, v1);
|
| /external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
| Mips64InstrInfo.td | 166 def DMULT : Mul64<0x1c, "dmult", IIImul>;
|
