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  /external/valgrind/none/tests/arm/
ldrt.vgtest 1 prog: ldrt
Makefile.am 8 ldrt.stdout.exp ldrt.stderr.exp ldrt.vgtest \
29 ldrt \
Makefile.in 123 check_PROGRAMS = allexec$(EXEEXT) intdiv$(EXEEXT) ldrt$(EXEEXT) \
150 ldrt_SOURCES = ldrt.c
151 ldrt_OBJECTS = ldrt-ldrt.$(OBJEXT)
261 SOURCES = allexec.c intdiv.c ldrt.c ldrt_arm.c neon128.c neon64.c \
265 DIST_SOURCES = allexec.c intdiv.c ldrt.c ldrt_arm.c neon128.c neon64.c \
665 ldrt.stdout.exp ldrt.stderr.exp ldrt.vgtest \
767 ldrt$(EXEEXT): $(ldrt_OBJECTS) $(ldrt_DEPENDENCIES) $(EXTRA_ldrt_DEPENDENCIES)
    [all...]
ldrt_arm.c 12 // Twice do ldrt for testing post-indexed.
13 "mov r5, %1 ; ldrt r6, [r5], #+132 ; ldrt r6, [r5], #132 ; mov %0, r6"
23 // Twice ldrt for testing post-indexed.
24 "mov r5, %1 ; mov r6, #33; ldrt r7, [r5], +r6, lsl #2 ; ldrt r7, [r5], +r6, lsl #2 ; mov %0, r7"
ldrt.c 3 // handles the T1 encoding of ldrt. This all assumes that we are
15 "mov r5, %1 ; ldrt r6, [r5, #132] ; mov %0, r6"
  /external/llvm/test/MC/ARM/
arm_addrmode2.s 4 @ CHECK: ldrt r1, [r0], r2 @ encoding: [0x02,0x10,0xb0,0xe6]
5 @ CHECK: ldrt r1, [r0], r2, lsr #3 @ encoding: [0xa2,0x11,0xb0,0xe6]
6 @ CHECK: ldrt r1, [r0], #4 @ encoding: [0x04,0x10,0xb0,0xe4]
7 @ CHECK: ldrt r1, [r0], #0 @ encoding: [0x00,0x10,0xb0,0xe4]
20 ldrt r1, [r0], r2
21 ldrt r1, [r0], r2, lsr #3
22 ldrt r1, [r0], #4
23 ldrt r1, [r0]
  /external/swiftshader/third_party/LLVM/test/MC/ARM/
arm_addrmode2.s 4 @ CHECK: ldrt r1, [r0], r2 @ encoding: [0x02,0x10,0xb0,0xe6]
5 @ CHECK: ldrt r1, [r0], r2, lsr #3 @ encoding: [0xa2,0x11,0xb0,0xe6]
6 @ CHECK: ldrt r1, [r0], #4 @ encoding: [0x04,0x10,0xb0,0xe4]
16 ldrt r1, [r0], r2
17 ldrt r1, [r0], r2, lsr #3
18 ldrt r1, [r0], #4
  /external/capstone/suite/MC/ARM/
arm_addrmode2.s.cs 2 0x02,0x10,0xb0,0xe6 = ldrt r1, [r0], r2
3 0xa2,0x11,0xb0,0xe6 = ldrt r1, [r0], r2, lsr #3
4 0x04,0x10,0xb0,0xe4 = ldrt r1, [r0], #4
  /external/llvm/test/MC/Disassembler/ARM/
addrmode2-reencoding.txt 8 # CHECK: ldrt r1, [r0], #0 @ encoding: [0x00,0x10,0xb0,0xe4]
thumb-tests.txt 188 # CHECK: ldrt r5, [r6, #30]
  /toolchain/binutils/binutils-2.27/gas/testsuite/gas/arm/
armv1.s 47 ldrt r0, [r1]
ldr-t-bad.s 61 ldrt r0, =0x0
sp-pc-validations-bad.s 155 @ LDRT
156 ldrt pc, [r0], #4 @ Unpredictable label
157 ldrt r0, [pc], #4 @ ditto label
158 ldrt pc,[r0],r1, LSL #4 @ ditto label
159 ldrt r0,[pc],r1, LSL #4 @ ditto label
160 ldrt r0,[r1],pc, LSL #4 @ ditto label
ldr-t-bad.l 16 [^:]*:61: Error: Instruction does not support =N addresses -- `ldrt r0,=0x0'
sp-pc-validations-bad-t.s 224 @ LDRT
225 @ldrt r0,[pc,#4] => LDR (literal)
226 ldrt pc,[r0,#4] @ BadReg label
227 ldrt sp,[r0,#4] @ ditto label
unpredictable.s 28 .word 0xe6b0f001 @ ldrt pc, [r0], r1
sp-pc-validations-bad.l 99 [^:]*:156: Error: r15 not allowed here -- `ldrt pc,\[r0\],#4'
100 [^:]*:157: Error: cannot use register index with PC-relative addressing -- `ldrt r0,\[pc\],#4'
101 [^:]*:158: Error: r15 not allowed here -- `ldrt pc,\[r0\],r1,LSL#4'
102 [^:]*:159: Error: cannot use register index with PC-relative addressing -- `ldrt r0,\[pc\],r1,LSL#4'
103 [^:]*:160: Error: cannot use register index with PC-relative addressing -- `ldrt r0,\[r1\],pc,LSL#4'
armv1.d 50 0+9c <[^>]*> e4b10000 ? ldrt r0, \[r1\]
inst.s 144 ldrt r1, [r2], r3
inst.d 129 0+1d4 <[^>]*> e6b21003 ? ldrt r1, \[r2\], r3
204 0+2f0 <[^>]*> e6b21003 ? ldrt r1, \[r2\], r3
wince_inst.d 131 0+1d4 <[^>]*> e6b21003 ? ldrt r1, \[r2\], r3
206 0+2f0 <[^>]*> e6b21003 ? ldrt r1, \[r2\], r3
  /device/google/contexthub/firmware/os/cpu/cortexm4/inc/cpu/cmsis/
core_cmInstr.h 308 /** \brief LDRT Unprivileged (8 bit)
310 This function executes a Unprivileged LDRT instruction for 8 bit value.
318 /** \brief LDRT Unprivileged (16 bit)
320 This function executes a Unprivileged LDRT instruction for 16 bit values.
328 /** \brief LDRT Unprivileged (32 bit)
330 This function executes a Unprivileged LDRT instruction for 32 bit values.
750 /** \brief LDRT Unprivileged (8 bit)
752 This function executes a Unprivileged LDRT instruction for 8 bit value.
773 /** \brief LDRT Unprivileged (16 bit)
775 This function executes a Unprivileged LDRT instruction for 16 bit values
    [all...]
  /external/swiftshader/third_party/LLVM/test/MC/Disassembler/ARM/
invalid-LDRT-arm.txt 9 # The bytes have Inst{4} = 1, so it's not an LDRT Encoding A2 instruction.
  /prebuilts/go/darwin-x86/src/cmd/vendor/golang.org/x/arch/arm/armasm/testdata/
decode.txt     [all...]
  /prebuilts/go/linux-x86/src/cmd/vendor/golang.org/x/arch/arm/armasm/testdata/
decode.txt     [all...]

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