1 .syntax unified 2 .arch armv7-a 3 .thumb 4 5 @ldr-immediate 6 7 @wback && (n == t) 8 ldr r1, [r1, #5]! 9 10 @rt == r15 && rn == r15 11 @ && bits<0..1> (immediate) != 00 12 ldr r15, [r15, #5] 13 14 @inITBlock && rt == 15 && !lastInITBlock 15 ittt ge 16 ldrge r15, [r15, #4] 17 nopge 18 nopge 19 20 @ldr-literal 21 22 23 @inITBlock && rt == 15 && !lastInITBlock 24 ittt ge 25 ldrge r15, .0x4 26 nopge 27 nopge 28 29 @rt == r15 && bits<0..1> (immediate) != 00 30 ldr r15, .-0xab7 31 32 @ldr-register 33 34 @inITBlock && rt == 15 && !lastInITBlock 35 ittt ge 36 ldrge r15, [r15, r1] 37 nopge 38 nopge 39 40 @rm == 13 || rm == 15 41 ldr r1, [r2, r13] 42 ldr r2, [r2, r15] 43 44 @str-immediate 45 46 @rt == 15 || rn == 15 47 str r15, [r1, #10] 48 str r1, [r15, #10] 49 50 @wback && (n == t) 51 str r1, [r1, #10]! 52 53 @str-register 54 55 @rt == 15 || rm == 13 || rm == 15 56 str r15, [r1, r2] 57 str r1, [r2, r13] 58 str r1, [r2, r15] 59 60 @ PR 14260 61 ldrt r0, =0x0 62
