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  /device/linaro/bootloader/arm-trusted-firmware/include/lib/cpus/aarch64/
aem_generic.h 10 /* BASE AEM midr for revision 0 */
13 /* Foundation AEM midr for revision 0 */
denver.h 10 /* MIDR values for Denver */
17 /* Implementer code in the MIDR register */
cortex_a55.h 10 /* Cortex-A55 MIDR for revision 0 */
cortex_a75.h 10 /* Cortex-A75 MIDR */
cortex_a73.h 10 /* Cortex-A73 midr for revision 0 */
cortex_a72.h 11 /* Cortex-A72 midr for revision 0 */
cortex_a53.h 10 /* Cortex-A53 midr for revision 0 */
cortex_a57.h 11 /* Cortex-A57 midr for revision 0 */
cpu_macros.S 38 CPU_MIDR: /* cpu_ops midr */
108 * Numeric value expected to read from CPU's MIDR
  /device/linaro/bootloader/arm-trusted-firmware/include/lib/cpus/aarch32/
aem_generic.h 10 /* BASE AEM midr for revision 0 */
cortex_a53.h 10 /* Cortex-A53 midr for revision 0 */
cortex_a72.h 11 /* Cortex-A72 midr for revision 0 */
cortex_a57.h 11 /* Cortex-A57 midr for revision 0 */
cpu_macros.S 38 CPU_MIDR: /* cpu_ops midr */
104 * Numeric value expected to read from CPU's MIDR
  /device/linaro/bootloader/arm-trusted-firmware/plat/nvidia/tegra/include/drivers/
flowctrl.h 52 void tegra_fc_cluster_idle(uint32_t midr);
54 void tegra_fc_cluster_powerdn(uint32_t midr);
55 void tegra_fc_soc_powerdn(uint32_t midr);
  /device/linaro/bootloader/arm-trusted-firmware/lib/cpus/aarch32/
cpu_helpers.S 110 * midr of the core. It reads the MIDR and finds the matching
128 ldcopr r2, MIDR
138 /* load the midr from the cpu_ops */
142 /* Check if midr matches to midr of this core */
158 ldcopr r1, MIDR
  /device/linaro/bootloader/arm-trusted-firmware/lib/cpus/aarch64/
cpu_helpers.S 137 * midr of the core. It reads the MIDR_EL1 and finds the matching
165 /* load the midr from the cpu_ops */
169 /* Check if midr matches to midr of this core */
188 * Extract the variant[23:20] and revision[3:0] from MIDR, and pack them
  /device/linaro/bootloader/arm-trusted-firmware/plat/hisilicon/hikey/
hikey_bl2_setup.c 402 u_register_t midr; local
404 midr = read_midr();
405 mmio_write_32(MEMORY_AXI_CHIP_ADDR, midr);
406 INFO("[BDID] [%x] midr: 0x%x\n", MEMORY_AXI_CHIP_ADDR,
407 (unsigned int)midr);
  /device/linaro/bootloader/edk2/ArmPkg/Include/Chipset/
ArmV7.h 77 // MIDR - Main ID Register definitions
AArch64.h 46 // MIDR - Main ID Register definitions
  /device/linaro/bootloader/edk2/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/Arm/
RTSMHelper.S 44 # Read CP15 MIDR
RTSMHelper.asm 60 // Read CP15 MIDR
  /device/linaro/bootloader/arm-trusted-firmware/plat/nvidia/tegra/soc/t186/
plat_sip_calls.c 148 * x2 = MIDR of the target core
  /device/linaro/bootloader/arm-trusted-firmware/include/lib/aarch32/
arch_helpers.h 229 DEFINE_COPROCR_READ_FUNC(midr, MIDR)
  /device/linaro/bootloader/edk2/ArmPkg/Library/ArmLib/AArch64/
ArmLibSupport.S 23 mrs x0, midr_el1 // Read from Main ID Register (MIDR)

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