| /toolchain/binutils/binutils-2.27/gprof/ |
| tahoe.c | 49 literal, indexed, reg, regdef, autodec, autoinc, autoincdef, enumerator in enum:tahoe_opermodes
84 return regdef;
120 case regdef:
170 case regdef:
271 case regdef:
|
| vax.c | 49 literal, indexed, reg, regdef, autodec, autoinc, autoincdef, enumerator in enum:opermodes
96 return regdef;
132 case regdef:
181 case regdef:
282 case regdef:
|
| /hardware/intel/img/psb_video/src/hwdefs/ |
| dxva_msg.h | 62 dxva_cmdseq_msg.def using the "regdef" tool.
|
| /bionic/libc/arch-mips/string/ |
| strcmp.S | 37 # include <regdef.h>
41 # include "machine/regdef.h"
43 # include <regdef.h>
|
| strncmp.S | 37 # include <regdef.h>
41 # include "machine/regdef.h"
43 # include <regdef.h>
|
| memset.S | 35 # include <regdef.h>
40 # include "machine/regdef.h"
43 # include <regdef.h>
|
| /external/valgrind/coregrind/m_gdbserver/ |
| regcache.c | 24 #include "regdef.h"
|
| valgrind-low-arm.c | 26 #include "regdef.h"
|
| valgrind-low-arm64.c | 26 #include "regdef.h"
|
| valgrind-low-s390x.c | 26 #include "regdef.h"
|
| valgrind-low-x86.c | 26 #include "regdef.h"
|
| valgrind-low-amd64.c | 26 #include "regdef.h"
|
| valgrind-low-mips32.c | 26 #include "regdef.h"
|
| valgrind-low-mips64.c | 26 #include "regdef.h"
|
| valgrind-low-ppc32.c | 26 #include "regdef.h"
|
| target.c | 27 #include "regdef.h"
|
| valgrind-low-ppc64.c | 26 #include "regdef.h"
|
| /external/google-breakpad/src/common/android/ |
| breakpad_getcontext.S | 235 #include <asm/regdef.h>
239 #include <machine/regdef.h>
|
| /external/llvm/lib/CodeGen/ |
| ImplicitNullChecks.cpp | 233 for (auto &RegDef : RegDefs) {
234 unsigned Reg = RegDef.first;
235 MachineInstr *MI = RegDef.second;
|
| /external/llvm/test/CodeGen/X86/ |
| inline-asm-fpstack.ll | 349 ; INLINEASM <es:frndint> [sideeffect] [attdialect], $0:[regdef], %ST0<imp-def,tied5>, $1:[reguse tiedto:$0], %ST0<tied3>, $2:[clobber], %EFLAGS<earlyclobber,imp-def,dead>
|
| /toolchain/binutils/binutils-2.27/gas/config/ |
| tc-aarch64.c | [all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| ScheduleDAGRRList.cpp | 535 SUnit *RegDef = LiveRegDefs[I->getReg()]; (void)RegDef;
536 assert((!RegDef || RegDef == SU || RegDef == I->getSUnit()) &&
[all...] |
| ScheduleDAGSDNodes.cpp | 573 return; // Found a normal regdef.
[all...] |
| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| ScheduleDAGRRList.cpp | 433 SUnit *RegDef = LiveRegDefs[I->getReg()]; (void)RegDef;
434 assert((!RegDef || RegDef == SU || RegDef == I->getSUnit()) &&
[all...] |
| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| MachineInstr.cpp | [all...] |
