1 /* 2 * Copyright (C) 2010 The Android Open Source Project 3 * Copyright (c) 2008 ARM Ltd 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the company may not be used to endorse or promote 15 * products derived from this software without specific prior written 16 * permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY ARM LTD ``AS IS'' AND ANY EXPRESS OR IMPLIED 19 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 20 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL ARM LTD BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 23 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 24 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 25 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 26 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 27 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 * 29 * Android adaptation and tweak by Jim Huang <jserv (at) 0xlab.org>. 30 */ 31 32 #include <private/bionic_asm.h> 33 34 .syntax unified 35 36 ENTRY(strcpy) 37 pld [r1, #0] 38 eor r2, r0, r1 39 mov ip, r0 40 tst r2, #3 41 bne 4f 42 tst r1, #3 43 bne 3f 44 5: 45 str r5, [sp, #-4]! 46 mov r5, #0x01 47 orr r5, r5, r5, lsl #8 48 orr r5, r5, r5, lsl #16 49 50 str r4, [sp, #-4]! 51 tst r1, #4 52 ldr r3, [r1], #4 53 beq 2f 54 sub r2, r3, r5 55 bics r2, r2, r3 56 tst r2, r5, lsl #7 57 itt eq 58 streq r3, [ip], #4 59 ldreq r3, [r1], #4 60 bne 1f 61 /* Inner loop. We now know that r1 is 64-bit aligned, so we 62 can safely fetch up to two words. This allows us to avoid 63 load stalls. */ 64 .p2align 2 65 2: 66 pld [r1, #8] 67 ldr r4, [r1], #4 68 sub r2, r3, r5 69 bics r2, r2, r3 70 tst r2, r5, lsl #7 71 sub r2, r4, r5 72 bne 1f 73 str r3, [ip], #4 74 bics r2, r2, r4 75 tst r2, r5, lsl #7 76 itt eq 77 ldreq r3, [r1], #4 78 streq r4, [ip], #4 79 beq 2b 80 mov r3, r4 81 1: 82 #ifdef __ARMEB__ 83 rors r3, r3, #24 84 #endif 85 strb r3, [ip], #1 86 tst r3, #0xff 87 #ifdef __ARMEL__ 88 ror r3, r3, #8 89 #endif 90 bne 1b 91 ldr r4, [sp], #4 92 ldr r5, [sp], #4 93 bx lr 94 95 /* Strings have the same offset from word alignment, but it's 96 not zero. */ 97 3: 98 tst r1, #1 99 beq 1f 100 ldrb r2, [r1], #1 101 strb r2, [ip], #1 102 cmp r2, #0 103 it eq 104 bxeq lr 105 1: 106 tst r1, #2 107 beq 5b 108 ldrh r2, [r1], #2 109 #ifdef __ARMEB__ 110 tst r2, #0xff00 111 iteet ne 112 strhne r2, [ip], #2 113 lsreq r2, r2, #8 114 strbeq r2, [ip] 115 tstne r2, #0xff 116 #else 117 tst r2, #0xff 118 itet ne 119 strhne r2, [ip], #2 120 strbeq r2, [ip] 121 tstne r2, #0xff00 122 #endif 123 bne 5b 124 bx lr 125 126 /* src and dst do not have a common word-alignement. Fall back to 127 byte copying. */ 128 4: 129 ldrb r2, [r1], #1 130 strb r2, [ip], #1 131 cmp r2, #0 132 bne 4b 133 bx lr 134 END(strcpy) 135
