1 /**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 *** To edit the content of this header, modify the corresponding 11 *** source file (e.g. under external/kernel-headers/original/) then 12 *** run bionic/libc/kernel/tools/update_all.py 13 *** 14 *** Any manual change here will be lost the next time this script will 15 *** be run. You've been warned! 16 *** 17 **************************************************************************** 18 ****************************************************************************/ 19 #ifndef __MSM_DRM_H__ 20 #define __MSM_DRM_H__ 21 #include "drm.h" 22 #ifdef __cplusplus 23 #endif 24 #define MSM_PIPE_NONE 0x00 25 #define MSM_PIPE_2D0 0x01 26 #define MSM_PIPE_2D1 0x02 27 #define MSM_PIPE_3D0 0x10 28 #define MSM_PIPE_ID_MASK 0xffff 29 #define MSM_PIPE_ID(x) ((x) & MSM_PIPE_ID_MASK) 30 #define MSM_PIPE_FLAGS(x) ((x) & ~MSM_PIPE_ID_MASK) 31 struct drm_msm_timespec { 32 __s64 tv_sec; 33 __s64 tv_nsec; 34 }; 35 #define MSM_PARAM_GPU_ID 0x01 36 #define MSM_PARAM_GMEM_SIZE 0x02 37 #define MSM_PARAM_CHIP_ID 0x03 38 #define MSM_PARAM_MAX_FREQ 0x04 39 #define MSM_PARAM_TIMESTAMP 0x05 40 #define MSM_PARAM_GMEM_BASE 0x06 41 #define MSM_PARAM_NR_RINGS 0x07 42 struct drm_msm_param { 43 __u32 pipe; 44 __u32 param; 45 __u64 value; 46 }; 47 #define MSM_BO_SCANOUT 0x00000001 48 #define MSM_BO_GPU_READONLY 0x00000002 49 #define MSM_BO_CACHE_MASK 0x000f0000 50 #define MSM_BO_CACHED 0x00010000 51 #define MSM_BO_WC 0x00020000 52 #define MSM_BO_UNCACHED 0x00040000 53 #define MSM_BO_FLAGS (MSM_BO_SCANOUT | MSM_BO_GPU_READONLY | MSM_BO_CACHED | MSM_BO_WC | MSM_BO_UNCACHED) 54 struct drm_msm_gem_new { 55 __u64 size; 56 __u32 flags; 57 __u32 handle; 58 }; 59 #define MSM_INFO_IOVA 0x01 60 #define MSM_INFO_FLAGS (MSM_INFO_IOVA) 61 struct drm_msm_gem_info { 62 __u32 handle; 63 __u32 flags; 64 __u64 offset; 65 }; 66 #define MSM_PREP_READ 0x01 67 #define MSM_PREP_WRITE 0x02 68 #define MSM_PREP_NOSYNC 0x04 69 #define MSM_PREP_FLAGS (MSM_PREP_READ | MSM_PREP_WRITE | MSM_PREP_NOSYNC) 70 struct drm_msm_gem_cpu_prep { 71 __u32 handle; 72 __u32 op; 73 struct drm_msm_timespec timeout; 74 }; 75 struct drm_msm_gem_cpu_fini { 76 __u32 handle; 77 }; 78 struct drm_msm_gem_submit_reloc { 79 __u32 submit_offset; 80 __u32 or; 81 __s32 shift; 82 __u32 reloc_idx; 83 __u64 reloc_offset; 84 }; 85 #define MSM_SUBMIT_CMD_BUF 0x0001 86 #define MSM_SUBMIT_CMD_IB_TARGET_BUF 0x0002 87 #define MSM_SUBMIT_CMD_CTX_RESTORE_BUF 0x0003 88 struct drm_msm_gem_submit_cmd { 89 __u32 type; 90 __u32 submit_idx; 91 __u32 submit_offset; 92 __u32 size; 93 __u32 pad; 94 __u32 nr_relocs; 95 __u64 relocs; 96 }; 97 #define MSM_SUBMIT_BO_READ 0x0001 98 #define MSM_SUBMIT_BO_WRITE 0x0002 99 #define MSM_SUBMIT_BO_FLAGS (MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE) 100 struct drm_msm_gem_submit_bo { 101 __u32 flags; 102 __u32 handle; 103 __u64 presumed; 104 }; 105 #define MSM_SUBMIT_NO_IMPLICIT 0x80000000 106 #define MSM_SUBMIT_FENCE_FD_IN 0x40000000 107 #define MSM_SUBMIT_FENCE_FD_OUT 0x20000000 108 #define MSM_SUBMIT_FLAGS (MSM_SUBMIT_NO_IMPLICIT | MSM_SUBMIT_FENCE_FD_IN | MSM_SUBMIT_FENCE_FD_OUT | 0) 109 struct drm_msm_gem_submit { 110 __u32 flags; 111 __u32 fence; 112 __u32 nr_bos; 113 __u32 nr_cmds; 114 __u64 bos; 115 __u64 cmds; 116 __s32 fence_fd; 117 __u32 queueid; 118 }; 119 struct drm_msm_wait_fence { 120 __u32 fence; 121 __u32 pad; 122 struct drm_msm_timespec timeout; 123 __u32 queueid; 124 }; 125 #define MSM_MADV_WILLNEED 0 126 #define MSM_MADV_DONTNEED 1 127 #define __MSM_MADV_PURGED 2 128 struct drm_msm_gem_madvise { 129 __u32 handle; 130 __u32 madv; 131 __u32 retained; 132 }; 133 #define MSM_SUBMITQUEUE_FLAGS (0) 134 struct drm_msm_submitqueue { 135 __u32 flags; 136 __u32 prio; 137 __u32 id; 138 }; 139 #define DRM_MSM_GET_PARAM 0x00 140 #define DRM_MSM_GEM_NEW 0x02 141 #define DRM_MSM_GEM_INFO 0x03 142 #define DRM_MSM_GEM_CPU_PREP 0x04 143 #define DRM_MSM_GEM_CPU_FINI 0x05 144 #define DRM_MSM_GEM_SUBMIT 0x06 145 #define DRM_MSM_WAIT_FENCE 0x07 146 #define DRM_MSM_GEM_MADVISE 0x08 147 #define DRM_MSM_SUBMITQUEUE_NEW 0x0A 148 #define DRM_MSM_SUBMITQUEUE_CLOSE 0x0B 149 #define DRM_IOCTL_MSM_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GET_PARAM, struct drm_msm_param) 150 #define DRM_IOCTL_MSM_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_NEW, struct drm_msm_gem_new) 151 #define DRM_IOCTL_MSM_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_INFO, struct drm_msm_gem_info) 152 #define DRM_IOCTL_MSM_GEM_CPU_PREP DRM_IOW(DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_PREP, struct drm_msm_gem_cpu_prep) 153 #define DRM_IOCTL_MSM_GEM_CPU_FINI DRM_IOW(DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_FINI, struct drm_msm_gem_cpu_fini) 154 #define DRM_IOCTL_MSM_GEM_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_SUBMIT, struct drm_msm_gem_submit) 155 #define DRM_IOCTL_MSM_WAIT_FENCE DRM_IOW(DRM_COMMAND_BASE + DRM_MSM_WAIT_FENCE, struct drm_msm_wait_fence) 156 #define DRM_IOCTL_MSM_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_MADVISE, struct drm_msm_gem_madvise) 157 #define DRM_IOCTL_MSM_SUBMITQUEUE_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_SUBMITQUEUE_NEW, struct drm_msm_submitqueue) 158 #define DRM_IOCTL_MSM_SUBMITQUEUE_CLOSE DRM_IOW(DRM_COMMAND_BASE + DRM_MSM_SUBMITQUEUE_CLOSE, __u32) 159 #ifdef __cplusplus 160 #endif 161 #endif 162
