1 /* 2 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of the ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 motherboard { 32 arm,v2m-memory-map = "rs1"; 33 compatible = "arm,vexpress,v2m-p1", "simple-bus"; 34 #address-cells = <2>; /* SMB chipselect number and offset */ 35 #size-cells = <1>; 36 #interrupt-cells = <1>; 37 ranges; 38 39 ethernet@2,02000000 { 40 compatible = "smsc,lan91c111"; 41 reg = <2 0x02000000 0x10000>; 42 interrupts = <15>; 43 }; 44 45 v2m_clk24mhz: clk24mhz { 46 compatible = "fixed-clock"; 47 #clock-cells = <0>; 48 clock-frequency = <24000000>; 49 clock-output-names = "v2m:clk24mhz"; 50 }; 51 52 v2m_refclk1mhz: refclk1mhz { 53 compatible = "fixed-clock"; 54 #clock-cells = <0>; 55 clock-frequency = <1000000>; 56 clock-output-names = "v2m:refclk1mhz"; 57 }; 58 59 v2m_refclk32khz: refclk32khz { 60 compatible = "fixed-clock"; 61 #clock-cells = <0>; 62 clock-frequency = <32768>; 63 clock-output-names = "v2m:refclk32khz"; 64 }; 65 66 iofpga@3,00000000 { 67 compatible = "arm,amba-bus", "simple-bus"; 68 #address-cells = <1>; 69 #size-cells = <1>; 70 ranges = <0 3 0 0x200000>; 71 72 v2m_sysreg: sysreg@010000 { 73 compatible = "arm,vexpress-sysreg"; 74 reg = <0x010000 0x1000>; 75 gpio-controller; 76 #gpio-cells = <2>; 77 }; 78 79 v2m_sysctl: sysctl@020000 { 80 compatible = "arm,sp810", "arm,primecell"; 81 reg = <0x020000 0x1000>; 82 clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&v2m_clk24mhz>; 83 clock-names = "refclk", "timclk", "apb_pclk"; 84 #clock-cells = <1>; 85 clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3"; 86 }; 87 88 v2m_serial0: uart@090000 { 89 compatible = "arm,pl011", "arm,primecell"; 90 reg = <0x090000 0x1000>; 91 interrupts = <5>; 92 clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; 93 clock-names = "uartclk", "apb_pclk"; 94 }; 95 96 v2m_serial1: uart@0a0000 { 97 compatible = "arm,pl011", "arm,primecell"; 98 reg = <0x0a0000 0x1000>; 99 interrupts = <6>; 100 clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; 101 clock-names = "uartclk", "apb_pclk"; 102 }; 103 104 v2m_serial2: uart@0b0000 { 105 compatible = "arm,pl011", "arm,primecell"; 106 reg = <0x0b0000 0x1000>; 107 interrupts = <7>; 108 clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; 109 clock-names = "uartclk", "apb_pclk"; 110 }; 111 112 v2m_serial3: uart@0c0000 { 113 compatible = "arm,pl011", "arm,primecell"; 114 reg = <0x0c0000 0x1000>; 115 interrupts = <8>; 116 clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; 117 clock-names = "uartclk", "apb_pclk"; 118 }; 119 120 wdt@0f0000 { 121 compatible = "arm,sp805", "arm,primecell"; 122 reg = <0x0f0000 0x1000>; 123 interrupts = <0>; 124 clocks = <&v2m_refclk32khz>, <&v2m_clk24mhz>; 125 clock-names = "wdogclk", "apb_pclk"; 126 }; 127 128 v2m_timer01: timer@110000 { 129 compatible = "arm,sp804", "arm,primecell"; 130 reg = <0x110000 0x1000>; 131 interrupts = <2>; 132 clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_clk24mhz>; 133 clock-names = "timclken1", "timclken2", "apb_pclk"; 134 }; 135 136 v2m_timer23: timer@120000 { 137 compatible = "arm,sp804", "arm,primecell"; 138 reg = <0x120000 0x1000>; 139 interrupts = <3>; 140 clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&v2m_clk24mhz>; 141 clock-names = "timclken1", "timclken2", "apb_pclk"; 142 }; 143 144 rtc@170000 { 145 compatible = "arm,pl031", "arm,primecell"; 146 reg = <0x170000 0x1000>; 147 interrupts = <4>; 148 clocks = <&v2m_clk24mhz>; 149 clock-names = "apb_pclk"; 150 }; 151 152 virtio_block@0130000 { 153 compatible = "virtio,mmio"; 154 reg = <0x130000 0x1000>; 155 interrupts = <0x2a>; 156 }; 157 }; 158 159 v2m_fixed_3v3: fixedregulator@0 { 160 compatible = "regulator-fixed"; 161 regulator-name = "3V3"; 162 regulator-min-microvolt = <3300000>; 163 regulator-max-microvolt = <3300000>; 164 regulator-always-on; 165 }; 166 167 168 mcc { 169 compatible = "arm,vexpress,config-bus", "simple-bus"; 170 arm,vexpress,config-bridge = <&v2m_sysreg>; 171 172 reset@0 { 173 compatible = "arm,vexpress-reset"; 174 arm,vexpress-sysreg,func = <5 0>; 175 }; 176 177 muxfpga@0 { 178 compatible = "arm,vexpress-muxfpga"; 179 arm,vexpress-sysreg,func = <7 0>; 180 }; 181 182 shutdown@0 { 183 compatible = "arm,vexpress-shutdown"; 184 arm,vexpress-sysreg,func = <8 0>; 185 }; 186 187 reboot@0 { 188 compatible = "arm,vexpress-reboot"; 189 arm,vexpress-sysreg,func = <9 0>; 190 }; 191 192 dvimode@0 { 193 compatible = "arm,vexpress-dvimode"; 194 arm,vexpress-sysreg,func = <11 0>; 195 }; 196 }; 197 }; 198
