1 /** @file 2 * 3 * Copyright (c) 2015, Hisilicon Limited. All rights reserved. 4 * Copyright (c) 2015, Linaro Limited. All rights reserved. 5 * 6 * This program and the accompanying materials 7 * are licensed and made available under the terms and conditions of the BSD License 8 * which accompanies this distribution. The full text of the license may be found at 9 * http://opensource.org/licenses/bsd-license.php 10 * 11 * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 13 * 14 **/ 15 16 #include <Uefi.h> 17 #include <Library/DebugLib.h> 18 #include <Library/BaseMemoryLib.h> 19 #include <Protocol/Smbios.h> 20 #include <IndustryStandard/SmBios.h> 21 22 #include <PlatformArch.h> 23 #include <Library/OemMiscLib.h> 24 #include <Library/SerdesLib.h> 25 #include <Library/I2CLib.h> 26 #include <Library/HiiLib.h> 27 28 I2C_DEVICE gDS3231RtcDevice = { 29 .Socket = 0, 30 .Port = 6, 31 .DeviceType = DEVICE_TYPE_SPD, 32 .SlaveDeviceAddress = 0x68 33 }; 34 35 SERDES_POLARITY_INVERT gSerdesPolarityTxDesc[] = 36 { 37 {SERDES_INVALID_MACRO_ID, SERDES_INVALID_LANE_NUM} 38 }; 39 40 SERDES_POLARITY_INVERT gSerdesPolarityRxDesc[] = 41 { 42 {SERDES_INVALID_MACRO_ID, SERDES_INVALID_LANE_NUM} 43 }; 44 45 SERDES_PARAM gSerdesParam = { 46 .Hilink0Mode = EmHilink0Pcie1X8, 47 .Hilink1Mode = EmHilink1Pcie0X8, 48 .Hilink2Mode = EmHilink2Pcie2X8, 49 .Hilink3Mode = 0x0, 50 .Hilink4Mode = 0xF, 51 .Hilink5Mode = EmHilink5Sas1X4, 52 .Hilink6Mode = 0x0, 53 .UseSsc = 0, 54 }; 55 56 SERDES_PARAM gSerdesParam0 = { 57 .Hilink0Mode = EmHilink0Hccs1X8Width16, 58 .Hilink1Mode = EmHilink1Hccs0X8Width16, 59 .Hilink2Mode = EmHilink2Pcie2X8, 60 .Hilink3Mode = 0x0, 61 .Hilink4Mode = 0xF, 62 .Hilink5Mode = EmHilink5Sas1X4, 63 .Hilink6Mode = 0x0, 64 .UseSsc = 0, 65 }; 66 67 SERDES_PARAM gSerdesParam1 = { 68 .Hilink0Mode = EmHilink0Hccs1X8Width16, 69 .Hilink1Mode = EmHilink1Hccs0X8Width16, 70 .Hilink2Mode = EmHilink2Pcie2X8, 71 .Hilink3Mode = 0x0, 72 .Hilink4Mode = 0xF, 73 .Hilink5Mode = EmHilink5Pcie3X4, 74 .Hilink6Mode = 0xF, 75 .UseSsc = 0, 76 }; 77 78 EFI_STATUS OemGetSerdesParam (SERDES_PARAM *ParamA, SERDES_PARAM *ParamB, UINT32 SocketId) 79 { 80 if (ParamA == NULL) { 81 DEBUG((EFI_D_ERROR, "[%a]:[%dL] Param == NULL!\n", __FUNCTION__, __LINE__)); 82 return EFI_INVALID_PARAMETER; 83 } 84 85 (VOID) CopyMem(ParamA, &gSerdesParam, sizeof(*ParamA)); 86 return EFI_SUCCESS; 87 } 88 89 90 VOID OemPcieResetAndOffReset(void) 91 { 92 return; 93 } 94 95 SMBIOS_TABLE_TYPE9 gPcieSlotInfo[] = { 96 // PCIe0 Slot 1 97 { 98 { // Hdr 99 EFI_SMBIOS_TYPE_SYSTEM_SLOTS, // Type, 100 0, // Length, 101 0 // Handle 102 }, 103 1, // SlotDesignation 104 SlotTypePciExpressX8, // SlotType 105 SlotDataBusWidth8X, // SlotDataBusWidth 106 SlotUsageAvailable, // SlotUsage 107 SlotLengthOther, // SlotLength 108 0x0001, // SlotId 109 { // SlotCharacteristics1 110 0, // CharacteristicsUnknown :1; 111 0, // Provides50Volts :1; 112 0, // Provides33Volts :1; 113 0, // SharedSlot :1; 114 0, // PcCard16Supported :1; 115 0, // CardBusSupported :1; 116 0, // ZoomVideoSupported :1; 117 0 // ModemRingResumeSupported:1; 118 }, 119 { // SlotCharacteristics2 120 0, // PmeSignalSupported :1; 121 0, // HotPlugDevicesSupported :1; 122 0, // SmbusSignalSupported :1; 123 0 // Reserved :5; 124 }, 125 0x00, // SegmentGroupNum 126 0x00, // BusNum 127 0 // DevFuncNum 128 }, 129 130 // PCIe0 Slot 4 131 { 132 { // Hdr 133 EFI_SMBIOS_TYPE_SYSTEM_SLOTS, // Type, 134 0, // Length, 135 0 // Handle 136 }, 137 1, // SlotDesignation 138 SlotTypePciExpressX8, // SlotType 139 SlotDataBusWidth8X, // SlotDataBusWidth 140 SlotUsageAvailable, // SlotUsage 141 SlotLengthOther, // SlotLength 142 0x0004, // SlotId 143 { // SlotCharacteristics1 144 0, // CharacteristicsUnknown :1; 145 0, // Provides50Volts :1; 146 0, // Provides33Volts :1; 147 0, // SharedSlot :1; 148 0, // PcCard16Supported :1; 149 0, // CardBusSupported :1; 150 0, // ZoomVideoSupported :1; 151 0 // ModemRingResumeSupported:1; 152 }, 153 { // SlotCharacteristics2 154 0, // PmeSignalSupported :1; 155 0, // HotPlugDevicesSupported :1; 156 0, // SmbusSignalSupported :1; 157 0 // Reserved :5; 158 }, 159 0x00, // SegmentGroupNum 160 0x00, // BusNum 161 0 // DevFuncNum 162 } 163 }; 164 165 166 UINT8 OemGetPcieSlotNumber () 167 { 168 return sizeof (gPcieSlotInfo) / sizeof (SMBIOS_TABLE_TYPE9); 169 } 170 171 EFI_STRING_ID gDimmToDevLocator[MAX_SOCKET][MAX_CHANNEL][MAX_DIMM] = { 172 {{STRING_TOKEN(STR_LEMON_C10_DIMM_000), STRING_TOKEN(STR_LEMON_C10_DIMM_001), STRING_TOKEN(STR_LEMON_C10_DIMM_002)}, 173 {STRING_TOKEN(STR_LEMON_C10_DIMM_010), STRING_TOKEN(STR_LEMON_C10_DIMM_011), STRING_TOKEN(STR_LEMON_C10_DIMM_012)}, 174 {STRING_TOKEN(STR_LEMON_C10_DIMM_020), STRING_TOKEN(STR_LEMON_C10_DIMM_021), STRING_TOKEN(STR_LEMON_C10_DIMM_022)}, 175 {STRING_TOKEN(STR_LEMON_C10_DIMM_030), STRING_TOKEN(STR_LEMON_C10_DIMM_031), STRING_TOKEN(STR_LEMON_C10_DIMM_032)}}, 176 177 {{STRING_TOKEN(STR_LEMON_C10_DIMM_100), STRING_TOKEN(STR_LEMON_C10_DIMM_101), STRING_TOKEN(STR_LEMON_C10_DIMM_102)}, 178 {STRING_TOKEN(STR_LEMON_C10_DIMM_110), STRING_TOKEN(STR_LEMON_C10_DIMM_111), STRING_TOKEN(STR_LEMON_C10_DIMM_112)}, 179 {STRING_TOKEN(STR_LEMON_C10_DIMM_120), STRING_TOKEN(STR_LEMON_C10_DIMM_121), STRING_TOKEN(STR_LEMON_C10_DIMM_122)}, 180 {STRING_TOKEN(STR_LEMON_C10_DIMM_130), STRING_TOKEN(STR_LEMON_C10_DIMM_131), STRING_TOKEN(STR_LEMON_C10_DIMM_132)}} 181 }; 182 183 EFI_HII_HANDLE 184 EFIAPI 185 OemGetPackages ( 186 ) 187 { 188 return HiiAddPackages ( 189 &gEfiCallerIdGuid, 190 NULL, 191 OemMiscLib2PStrings, 192 NULL, 193 NULL 194 ); 195 } 196 197 198
