1 /* 2 * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch.h> 8 #include <asm_macros.S> 9 #include <bl_common.h> 10 11 12 .globl bl2_vector_table 13 .globl bl2_entrypoint 14 15 16 vector_base bl2_vector_table 17 b bl2_entrypoint 18 b report_exception /* Undef */ 19 b report_exception /* SVC call */ 20 b report_exception /* Prefetch abort */ 21 b report_exception /* Data abort */ 22 b report_exception /* Reserved */ 23 b report_exception /* IRQ */ 24 b report_exception /* FIQ */ 25 26 27 func bl2_entrypoint 28 /*--------------------------------------------- 29 * Save from r1 the extents of the trusted ram 30 * available to BL2 for future use. 31 * r0 is not currently used. 32 * --------------------------------------------- 33 */ 34 mov r11, r1 35 36 /* --------------------------------------------- 37 * Set the exception vector to something sane. 38 * --------------------------------------------- 39 */ 40 ldr r0, =bl2_vector_table 41 stcopr r0, VBAR 42 isb 43 44 /* ----------------------------------------------------- 45 * Enable the instruction cache 46 * ----------------------------------------------------- 47 */ 48 ldcopr r0, SCTLR 49 orr r0, r0, #SCTLR_I_BIT 50 stcopr r0, SCTLR 51 isb 52 53 /* --------------------------------------------- 54 * Since BL2 executes after BL1, it is assumed 55 * here that BL1 has already has done the 56 * necessary register initializations. 57 * --------------------------------------------- 58 */ 59 60 /* --------------------------------------------- 61 * Invalidate the RW memory used by the BL2 62 * image. This includes the data and NOBITS 63 * sections. This is done to safeguard against 64 * possible corruption of this memory by dirty 65 * cache lines in a system cache as a result of 66 * use by an earlier boot loader stage. 67 * --------------------------------------------- 68 */ 69 ldr r0, =__RW_START__ 70 ldr r1, =__RW_END__ 71 sub r1, r1, r0 72 bl inv_dcache_range 73 74 /* --------------------------------------------- 75 * Zero out NOBITS sections. There are 2 of them: 76 * - the .bss section; 77 * - the coherent memory section. 78 * --------------------------------------------- 79 */ 80 ldr r0, =__BSS_START__ 81 ldr r1, =__BSS_SIZE__ 82 bl zeromem 83 84 #if USE_COHERENT_MEM 85 ldr r0, =__COHERENT_RAM_START__ 86 ldr r1, =__COHERENT_RAM_UNALIGNED_SIZE__ 87 bl zeromem 88 #endif 89 90 /* -------------------------------------------- 91 * Allocate a stack whose memory will be marked 92 * as Normal-IS-WBWA when the MMU is enabled. 93 * There is no risk of reading stale stack 94 * memory after enabling the MMU as only the 95 * primary cpu is running at the moment. 96 * -------------------------------------------- 97 */ 98 bl plat_set_my_stack 99 100 /* --------------------------------------------- 101 * Initialize the stack protector canary before 102 * any C code is called. 103 * --------------------------------------------- 104 */ 105 #if STACK_PROTECTOR_ENABLED 106 bl update_stack_protector_canary 107 #endif 108 109 /* --------------------------------------------- 110 * Perform early platform setup & platform 111 * specific early arch. setup e.g. mmu setup 112 * --------------------------------------------- 113 */ 114 mov r0, r11 115 bl bl2_early_platform_setup 116 bl bl2_plat_arch_setup 117 118 /* --------------------------------------------- 119 * Jump to main function. 120 * --------------------------------------------- 121 */ 122 bl bl2_main 123 124 /* --------------------------------------------- 125 * Should never reach this point. 126 * --------------------------------------------- 127 */ 128 no_ret plat_panic_handler 129 130 endfunc bl2_entrypoint 131
