1 /* 2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __DRAM_REGS_H__ 8 #define __DRAM_REGS_H__ 9 10 #define CTL_REG_NUM 332 11 #define PHY_REG_NUM 959 12 #define PI_REG_NUM 200 13 14 #define MSCH_ID_COREID 0x0 15 #define MSCH_ID_REVISIONID 0x4 16 #define MSCH_DEVICECONF 0x8 17 #define MSCH_DEVICESIZE 0xc 18 #define MSCH_DDRTIMINGA0 0x10 19 #define MSCH_DDRTIMINGB0 0x14 20 #define MSCH_DDRTIMINGC0 0x18 21 #define MSCH_DEVTODEV0 0x1c 22 #define MSCH_DDRMODE 0x110 23 #define MSCH_AGINGX0 0x1000 24 25 #define CIC_CTRL0 0x0 26 #define CIC_CTRL1 0x4 27 #define CIC_IDLE_TH 0x8 28 #define CIC_CG_WAIT_TH 0xc 29 #define CIC_STATUS0 0x10 30 #define CIC_STATUS1 0x14 31 #define CIC_CTRL2 0x18 32 #define CIC_CTRL3 0x1c 33 #define CIC_CTRL4 0x20 34 35 /* DENALI_CTL_00 */ 36 #define START 1 37 38 /* DENALI_CTL_68 */ 39 #define PWRUP_SREFRESH_EXIT (1 << 16) 40 41 /* DENALI_CTL_274 */ 42 #define MEM_RST_VALID 1 43 44 #define PHY_DRV_ODT_Hi_Z 0x0 45 #define PHY_DRV_ODT_240 0x1 46 #define PHY_DRV_ODT_120 0x8 47 #define PHY_DRV_ODT_80 0x9 48 #define PHY_DRV_ODT_60 0xc 49 #define PHY_DRV_ODT_48 0xd 50 #define PHY_DRV_ODT_40 0xe 51 #define PHY_DRV_ODT_34_3 0xf 52 53 /* 54 * sys_reg bitfield struct 55 * [31] row_3_4_ch1 56 * [30] row_3_4_ch0 57 * [29:28] chinfo 58 * [27] rank_ch1 59 * [26:25] col_ch1 60 * [24] bk_ch1 61 * [23:22] cs0_row_ch1 62 * [21:20] cs1_row_ch1 63 * [19:18] bw_ch1 64 * [17:16] dbw_ch1; 65 * [15:13] ddrtype 66 * [12] channelnum 67 * [11] rank_ch0 68 * [10:9] col_ch0 69 * [8] bk_ch0 70 * [7:6] cs0_row_ch0 71 * [5:4] cs1_row_ch0 72 * [3:2] bw_ch0 73 * [1:0] dbw_ch0 74 */ 75 #define SYS_REG_ENC_ROW_3_4(n, ch) ((n) << (30 + (ch))) 76 #define SYS_REG_DEC_ROW_3_4(n, ch) (((n) >> (30 + (ch))) & 0x1) 77 #define SYS_REG_ENC_CHINFO(ch) (1 << (28 + (ch))) 78 #define SYS_REG_DEC_CHINFO(n, ch) (((n) >> (28 + (ch))) & 0x1) 79 #define SYS_REG_ENC_DDRTYPE(n) ((n) << 13) 80 #define SYS_REG_DEC_DDRTYPE(n) (((n) >> 13) & 0x7) 81 #define SYS_REG_ENC_NUM_CH(n) (((n) - 1) << 12) 82 #define SYS_REG_DEC_NUM_CH(n) (1 + (((n) >> 12) & 0x1)) 83 #define SYS_REG_ENC_RANK(n, ch) (((n) - 1) << (11 + (ch) * 16)) 84 #define SYS_REG_DEC_RANK(n, ch) (1 + (((n) >> (11 + (ch) * 16)) & 0x1)) 85 #define SYS_REG_ENC_COL(n, ch) (((n) - 9) << (9 + (ch) * 16)) 86 #define SYS_REG_DEC_COL(n, ch) (9 + (((n) >> (9 + (ch) * 16)) & 0x3)) 87 #define SYS_REG_ENC_BK(n, ch) (((n) == 3 ? 0 : 1) << (8 + (ch) * 16)) 88 #define SYS_REG_DEC_BK(n, ch) (3 - (((n) >> (8 + (ch) * 16)) & 0x1)) 89 #define SYS_REG_ENC_CS0_ROW(n, ch) (((n) - 13) << (6 + (ch) * 16)) 90 #define SYS_REG_DEC_CS0_ROW(n, ch) (13 + (((n) >> (6 + (ch) * 16)) & 0x3)) 91 #define SYS_REG_ENC_CS1_ROW(n, ch) (((n) - 13) << (4 + (ch) * 16)) 92 #define SYS_REG_DEC_CS1_ROW(n, ch) (13 + (((n) >> (4 + (ch) * 16)) & 0x3)) 93 #define SYS_REG_ENC_BW(n, ch) ((2 >> (n)) << (2 + (ch) * 16)) 94 #define SYS_REG_DEC_BW(n, ch) (2 >> (((n) >> (2 + (ch) * 16)) & 0x3)) 95 #define SYS_REG_ENC_DBW(n, ch) ((2 >> (n)) << (0 + (ch) * 16)) 96 #define SYS_REG_DEC_DBW(n, ch) (2 >> (((n) >> (0 + (ch) * 16)) & 0x3)) 97 #define DDR_STRIDE(n) mmio_write_32(SGRF_BASE + SGRF_SOC_CON3_7(4), \ 98 (0x1f<<(10+16))|((n)<<10)) 99 100 #endif /* __DRAM_REGS_H__ */ 101
