1 /** @file 2 x64 Long Mode Virtual Memory Management Definitions 3 4 References: 5 1) IA-32 Intel(R) Atchitecture Software Developer's Manual Volume 1:Basic Architecture, Intel 6 2) IA-32 Intel(R) Atchitecture Software Developer's Manual Volume 2:Instruction Set Reference, Intel 7 3) IA-32 Intel(R) Atchitecture Software Developer's Manual Volume 3:System Programmer's Guide, Intel 8 4) AMD64 Architecture Programmer's Manual Volume 2: System Programming 9 10 Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR> 11 This program and the accompanying materials 12 are licensed and made available under the terms and conditions of the BSD License 13 which accompanies this distribution. The full text of the license may be found at 14 http://opensource.org/licenses/bsd-license.php 15 16 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 17 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 18 19 **/ 20 21 #ifndef _VIRTUAL_MEMORY_H_ 22 #define _VIRTUAL_MEMORY_H_ 23 24 #include "CommonLib.h" 25 26 #pragma pack(1) 27 28 // 29 // Page-Map Level-4 Offset (PML4) and 30 // Page-Directory-Pointer Offset (PDPE) entries 4K & 2MB 31 // 32 33 typedef union { 34 struct { 35 UINT64 Present:1; // 0 = Not present in memory, 1 = Present in memory 36 UINT64 ReadWrite:1; // 0 = Read-Only, 1= Read/Write 37 UINT64 UserSupervisor:1; // 0 = Supervisor, 1=User 38 UINT64 WriteThrough:1; // 0 = Write-Back caching, 1=Write-Through caching 39 UINT64 CacheDisabled:1; // 0 = Cached, 1=Non-Cached 40 UINT64 Accessed:1; // 0 = Not accessed, 1 = Accessed (set by CPU) 41 UINT64 Reserved:1; // Reserved 42 UINT64 MustBeZero:2; // Must Be Zero 43 UINT64 Available:3; // Available for use by system software 44 UINT64 PageTableBaseAddress:40; // Page Table Base Address 45 UINT64 AvabilableHigh:11; // Available for use by system software 46 UINT64 Nx:1; // No Execute bit 47 } Bits; 48 UINT64 Uint64; 49 } X64_PAGE_MAP_AND_DIRECTORY_POINTER_2MB_4K; 50 51 // 52 // Page-Directory Offset 4K 53 // 54 typedef union { 55 struct { 56 UINT64 Present:1; // 0 = Not present in memory, 1 = Present in memory 57 UINT64 ReadWrite:1; // 0 = Read-Only, 1= Read/Write 58 UINT64 UserSupervisor:1; // 0 = Supervisor, 1=User 59 UINT64 WriteThrough:1; // 0 = Write-Back caching, 1=Write-Through caching 60 UINT64 CacheDisabled:1; // 0 = Cached, 1=Non-Cached 61 UINT64 Accessed:1; // 0 = Not accessed, 1 = Accessed (set by CPU) 62 UINT64 Reserved:1; // Reserved 63 UINT64 MustBeZero:1; // Must Be Zero 64 UINT64 Reserved2:1; // Reserved 65 UINT64 Available:3; // Available for use by system software 66 UINT64 PageTableBaseAddress:40; // Page Table Base Address 67 UINT64 AvabilableHigh:11; // Available for use by system software 68 UINT64 Nx:1; // No Execute bit 69 } Bits; 70 UINT64 Uint64; 71 } X64_PAGE_DIRECTORY_ENTRY_4K; 72 73 // 74 // Page Table Entry 4K 75 // 76 typedef union { 77 struct { 78 UINT64 Present:1; // 0 = Not present in memory, 1 = Present in memory 79 UINT64 ReadWrite:1; // 0 = Read-Only, 1= Read/Write 80 UINT64 UserSupervisor:1; // 0 = Supervisor, 1=User 81 UINT64 WriteThrough:1; // 0 = Write-Back caching, 1=Write-Through caching 82 UINT64 CacheDisabled:1; // 0 = Cached, 1=Non-Cached 83 UINT64 Accessed:1; // 0 = Not accessed, 1 = Accessed (set by CPU) 84 UINT64 Dirty:1; // 0 = Not Dirty, 1 = written by processor on access to page 85 UINT64 PAT:1; // 0 = Ignore Page Attribute Table 86 UINT64 Global:1; // 0 = Not global page, 1 = global page TLB not cleared on CR3 write 87 UINT64 Available:3; // Available for use by system software 88 UINT64 PageTableBaseAddress:40; // Page Table Base Address 89 UINT64 AvabilableHigh:11; // Available for use by system software 90 UINT64 Nx:1; // 0 = Execute Code, 1 = No Code Execution 91 } Bits; 92 UINT64 Uint64; 93 } X64_PAGE_TABLE_ENTRY_4K; 94 95 96 // 97 // Page Table Entry 2MB 98 // 99 typedef union { 100 struct { 101 UINT64 Present:1; // 0 = Not present in memory, 1 = Present in memory 102 UINT64 ReadWrite:1; // 0 = Read-Only, 1= Read/Write 103 UINT64 UserSupervisor:1; // 0 = Supervisor, 1=User 104 UINT64 WriteThrough:1; // 0 = Write-Back caching, 1=Write-Through caching 105 UINT64 CacheDisabled:1; // 0 = Cached, 1=Non-Cached 106 UINT64 Accessed:1; // 0 = Not accessed, 1 = Accessed (set by CPU) 107 UINT64 Dirty:1; // 0 = Not Dirty, 1 = written by processor on access to page 108 UINT64 MustBe1:1; // Must be 1 109 UINT64 Global:1; // 0 = Not global page, 1 = global page TLB not cleared on CR3 write 110 UINT64 Available:3; // Available for use by system software 111 UINT64 PAT:1; // 112 UINT64 MustBeZero:8; // Must be zero; 113 UINT64 PageTableBaseAddress:31; // Page Table Base Address 114 UINT64 AvabilableHigh:11; // Available for use by system software 115 UINT64 Nx:1; // 0 = Execute Code, 1 = No Code Execution 116 } Bits; 117 UINT64 Uint64; 118 } X64_PAGE_TABLE_ENTRY_2M; 119 120 #pragma pack() 121 122 #endif 123
