1 /*++ 2 3 Copyright (c) 2005 - 2006, Intel Corporation. All rights reserved.<BR> 4 This program and the accompanying materials 5 are licensed and made available under the terms and conditions of the BSD License 6 which accompanies this distribution. The full text of the license may be found at 7 http://opensource.org/licenses/bsd-license.php 8 9 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 10 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 11 12 Module Name: 13 14 CpuFuncs.h 15 16 Abstract: 17 18 --*/ 19 20 #ifndef _CPU_FUNCS_H_ 21 #define _CPU_FUNCS_H_ 22 23 #define EFI_CPUID_SIGNATURE 0x0 24 #define EFI_CPUID_VERSION_INFO 0x1 25 #define EFI_CPUID_CACHE_INFO 0x2 26 #define EFI_CPUID_SERIAL_NUMBER 0x3 27 #define EFI_CPUID_EXTENDED_FUNCTION 0x80000000 28 #define EFI_CPUID_EXTENDED_CPU_SIG 0x80000001 29 #define EFI_CPUID_BRAND_STRING1 0x80000002 30 #define EFI_CPUID_BRAND_STRING2 0x80000003 31 #define EFI_CPUID_BRAND_STRING3 0x80000004 32 33 // 34 // CPUID version information masks 35 // Note: leaving masks here is for the compatibility 36 // use EfiCpuVersion (...) instead 37 // 38 39 #define EFI_CPUID_FAMILY 0x0F00 40 #define EFI_CPUID_MODEL 0x00F0 41 #define EFI_CPUID_STEPPING 0x000F 42 43 #define EFI_CPUID_PENTIUM_M 0x0600 44 #define EFI_CPUID_BANIAS 0x0090 45 #define EFI_CPUID_DOTHAN 0x00D0 46 #define EFI_CPUID_NETBURST 0x0F00 47 48 #define EFI_MSR_IA32_PLATFORM_ID 0x17 49 #define EFI_MSR_IA32_APIC_BASE 0x1B 50 #define EFI_MSR_EBC_HARD_POWERON 0x2A 51 #define EFI_MSR_EBC_SOFT_POWERON 0x2B 52 #define BINIT_DRIVER_DISABLE 0x40 53 #define INTERNAL_MCERR_DISABLE 0x20 54 #define INITIATOR_MCERR_DISABLE 0x10 55 #define EFI_MSR_EBC_FREQUENCY_ID 0x2C 56 #define EFI_MSR_IA32_BIOS_UPDT_TRIG 0x79 57 #define EFI_MSR_IA32_BIOS_SIGN_ID 0x8B 58 #define EFI_MSR_PSB_CLOCK_STATUS 0xCD 59 #define EFI_APIC_GLOBAL_ENABLE 0x800 60 #define EFI_MSR_IA32_MISC_ENABLE 0x1A0 61 #define LIMIT_CPUID_MAXVAL_ENABLE_BIT 0x00400000 62 #define AUTOMATIC_THERMAL_CONTROL_ENABLE_BIT 0x00000008 63 #define COMPATIBLE_FPU_OPCODE_ENABLE_BIT 0x00000004 64 #define LOGICAL_PROCESSOR_PRIORITY_ENABLE_BIT 0x00000002 65 #define FAST_STRING_ENABLE_BIT 0x00000001 66 67 #define EFI_CACHE_VARIABLE_MTRR_BASE 0x200 68 #define EFI_CACHE_VARIABLE_MTRR_END 0x20F 69 #define EFI_CACHE_IA32_MTRR_DEF_TYPE 0x2FF 70 #define EFI_CACHE_VALID_ADDRESS 0xFFFFFF000 71 #define EFI_CACHE_MTRR_VALID 0x800 72 #define EFI_CACHE_FIXED_MTRR_VALID 0x400 73 #define EFI_MSR_VALID_MASK 0xFFFFFFFFF 74 75 #define EFI_IA32_MTRR_FIX64K_00000 0x250 76 #define EFI_IA32_MTRR_FIX16K_80000 0x258 77 #define EFI_IA32_MTRR_FIX16K_A0000 0x259 78 #define EFI_IA32_MTRR_FIX4K_C0000 0x268 79 #define EFI_IA32_MTRR_FIX4K_C8000 0x269 80 #define EFI_IA32_MTRR_FIX4K_D0000 0x26A 81 #define EFI_IA32_MTRR_FIX4K_D8000 0x26B 82 #define EFI_IA32_MTRR_FIX4K_E0000 0x26C 83 #define EFI_IA32_MTRR_FIX4K_E8000 0x26D 84 #define EFI_IA32_MTRR_FIX4K_F0000 0x26E 85 #define EFI_IA32_MTRR_FIX4K_F8000 0x26F 86 87 #define EFI_IA32_MCG_CAP 0x179 88 #define EFI_IA32_MCG_CTL 0x17B 89 #define EFI_IA32_MC0_CTL 0x400 90 #define EFI_IA32_MC0_STATUS 0x401 91 92 #define EFI_CACHE_UNCACHEABLE 0 93 #define EFI_CACHE_WRITECOMBINING 1 94 #define EFI_CACHE_WRITETHROUGH 4 95 #define EFI_CACHE_WRITEPROTECTED 5 96 #define EFI_CACHE_WRITEBACK 6 97 98 // 99 // Combine f(FamilyId), m(Model), s(SteppingId) to a single 32 bit number 100 // 101 #define EfiMakeCpuVersion(f, m, s) \ 102 (((UINT32) (f) << 16) | ((UINT32) (m) << 8) | ((UINT32) (s))) 103 104 105 typedef struct { 106 UINT32 HeaderVersion; 107 UINT32 UpdateRevision; 108 UINT32 Date; 109 UINT32 ProcessorId; 110 UINT32 Checksum; 111 UINT32 LoaderRevision; 112 UINT32 ProcessorFlags; 113 UINT32 DataSize; 114 UINT32 TotalSize; 115 UINT8 Reserved[12]; 116 } EFI_CPU_MICROCODE_HEADER; 117 118 typedef struct { 119 UINT32 ExtSigCount; 120 UINT32 ExtChecksum; 121 UINT8 Reserved[12]; 122 UINT32 ProcessorId; 123 UINT32 ProcessorFlags; 124 UINT32 Checksum; 125 } EFI_CPU_MICROCODE_EXT_HEADER; 126 127 typedef struct { 128 UINT32 RegEax; 129 UINT32 RegEbx; 130 UINT32 RegEcx; 131 UINT32 RegEdx; 132 } EFI_CPUID_REGISTER; 133 134 VOID 135 EfiWriteMsr ( 136 IN UINT32 Input, 137 IN UINT64 Value 138 ) 139 /*++ 140 141 Routine Description: 142 143 Write Cpu MSR 144 145 Arguments: 146 147 Input -The index value to select the register 148 Value -The value to write to the selected register 149 150 Returns: 151 152 None 153 154 --*/ 155 ; 156 157 UINT64 158 EfiReadMsr ( 159 IN UINT32 Input 160 ) 161 /*++ 162 163 Routine Description: 164 165 Read Cpu MSR. 166 167 Arguments: 168 169 Input: -The index value to select the register 170 171 Returns: 172 173 Return the read data 174 175 --*/ 176 ; 177 178 VOID 179 EfiCpuid ( 180 IN UINT32 RegEax, 181 OUT EFI_CPUID_REGISTER *Reg 182 ) 183 /*++ 184 185 Routine Description: 186 187 Get the Cpu info by execute the CPUID instruction. 188 189 Arguments: 190 191 RegEax -The input value to put into register EAX 192 Reg -The Output value 193 194 Returns: 195 196 None 197 198 --*/ 199 ; 200 201 VOID 202 EfiCpuVersion ( 203 IN UINT16 *FamilyId, OPTIONAL 204 IN UINT8 *Model, OPTIONAL 205 IN UINT8 *SteppingId, OPTIONAL 206 IN UINT8 *Processor OPTIONAL 207 ) 208 /*++ 209 210 Routine Description: 211 Extract CPU detail version infomation 212 213 Arguments: 214 FamilyId - FamilyId, including ExtendedFamilyId 215 Model - Model, including ExtendedModel 216 SteppingId - SteppingId 217 Processor - Processor 218 219 --*/ 220 ; 221 222 UINT64 223 EfiReadTsc ( 224 VOID 225 ) 226 /*++ 227 228 Routine Description: 229 230 Read Time stamp. 231 232 Arguments: 233 234 None 235 236 Returns: 237 238 Return the read data 239 240 --*/ 241 ; 242 VOID 243 EfiCpuidExt ( 244 IN UINT32 RegisterInEax, 245 IN UINT32 CacheLevel, 246 OUT EFI_CPUID_REGISTER *Regs 247 ) 248 /*++ 249 Routine Description: 250 When RegisterInEax != 4, the functionality is the same as EfiCpuid. 251 When RegisterInEax == 4, the function return the deterministic cache 252 parameters by excuting the CPUID instruction 253 Arguments: 254 RegisterInEax: - The input value to put into register EAX 255 CacheLevel: - The deterministic cache level 256 Regs: - The Output value 257 Returns: 258 None 259 --*/ 260 ; 261 262 #endif 263
