1 /** @file 2 Macros to simplify and abstract the interface to PCI configuration. 3 4 Copyright (c) 2013-2015 Intel Corporation. 5 6 This program and the accompanying materials 7 are licensed and made available under the terms and conditions of the BSD License 8 which accompanies this distribution. The full text of the license may be found at 9 http://opensource.org/licenses/bsd-license.php 10 11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 13 14 15 **/ 16 17 #ifndef _QNC_ACCESS_H_ 18 #define _QNC_ACCESS_H_ 19 20 #include "QuarkNcSocId.h" 21 #include "QNCCommonDefinitions.h" 22 23 #define EFI_LPC_PCI_ADDRESS( Register ) \ 24 EFI_PCI_ADDRESS(PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_LPC, PCI_FUNCTION_NUMBER_QNC_LPC, Register) 25 26 // 27 // QNC Controller PCI access macros 28 // 29 #define QNC_RCRB_BASE (QNCMmio32 (PciDeviceMmBase (0, PCI_DEVICE_NUMBER_QNC_LPC, 0), R_QNC_LPC_RCBA) & B_QNC_LPC_RCBA_MASK) 30 31 // 32 // Device 0x1f, Function 0 33 // 34 35 #define LpcPciCfg32( Register ) \ 36 QNCMmPci32(0,PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_LPC, 0, Register ) 37 38 #define LpcPciCfg32Or( Register, OrData ) \ 39 QNCMmPci32Or( 0,PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_LPC, 0, Register, OrData ) 40 41 #define LpcPciCfg32And( Register, AndData ) \ 42 QNCMmPci32And( 0,PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_LPC, 0, Register, AndData ) 43 44 #define LpcPciCfg32AndThenOr( Register, AndData, OrData ) \ 45 QNCMmPci32AndThenOr( 0,PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_LPC, 0, Register, AndData, OrData ) 46 47 #define LpcPciCfg16( Register ) \ 48 QNCMmPci16( 0,PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_LPC, 0, Register ) 49 50 #define LpcPciCfg16Or( Register, OrData ) \ 51 QNCMmPci16Or( 0,PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_LPC, 0, Register, OrData ) 52 53 #define LpcPciCfg16And( Register, AndData ) \ 54 QNCMmPci16And( 0,PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_LPC, 0, Register, AndData ) 55 56 #define LpcPciCfg16AndThenOr( Register, AndData, OrData ) \ 57 QNCMmPci16AndThenOr( 0,PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_LPC, 0, Register, AndData, OrData ) 58 59 #define LpcPciCfg8( Register ) \ 60 QNCMmPci8( 0,PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_LPC, 0, Register ) 61 62 #define LpcPciCfg8Or( Register, OrData ) \ 63 QNCMmPci8Or( 0,PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_LPC, 0, Register, OrData ) 64 65 #define LpcPciCfg8And( Register, AndData ) \ 66 QNCMmPci8And( 0,PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_LPC, 0, Register, AndData ) 67 68 #define LpcPciCfg8AndThenOr( Register, AndData, OrData ) \ 69 QNCMmPci8AndThenOr( 0,PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_LPC, 0, Register, AndData, OrData ) 70 71 // 72 // Root Complex Register Block 73 // 74 75 #define MmRcrb32( Register ) \ 76 QNCMmio32( QNC_RCRB_BASE, Register ) 77 78 #define MmRcrb32Or( Register, OrData ) \ 79 QNCMmio32Or( QNC_RCRB_BASE, Register, OrData ) 80 81 #define MmRcrb32And( Register, AndData ) \ 82 QNCMmio32And( QNC_RCRB_BASE, Register, AndData ) 83 84 #define MmRcrb32AndThenOr( Register, AndData, OrData ) \ 85 QNCMmio32AndThenOr( QNC_RCRB_BASE, Register, AndData, OrData ) 86 87 #define MmRcrb16( Register ) \ 88 QNCMmio16( QNC_RCRB_BASE, Register ) 89 90 #define MmRcrb16Or( Register, OrData ) \ 91 QNCMmio16Or( QNC_RCRB_BASE, Register, OrData ) 92 93 #define MmRcrb16And( Register, AndData ) \ 94 QNCMmio16And( QNC_RCRB_BASE, Register, AndData ) 95 96 #define MmRcrb16AndThenOr( Register, AndData, OrData ) \ 97 QNCMmio16AndThenOr( QNC_RCRB_BASE, Register, AndData, OrData ) 98 99 #define MmRcrb8( Register ) \ 100 QNCMmio8( QNC_RCRB_BASE, Register ) 101 102 #define MmRcrb8Or( Register, OrData ) \ 103 QNCMmio8Or( QNC_RCRB_BASE, Register, OrData ) 104 105 #define MmRcrb8And( Register, AndData ) \ 106 QNCMmio8And( QNC_RCRB_BASE, Register, AndData ) 107 108 #define MmRcrb8AndThenOr( Register, AndData, OrData ) \ 109 QNCMmio8AndThenOr( QNC_RCRB_BASE, Register, AndData, OrData ) 110 111 // 112 // Memory Controller PCI access macros 113 // 114 115 // 116 // Device 0, Function 0 117 // 118 119 #define McD0PciCfg64(Register) QNCMmPci32 (0, MC_BUS, 0, 0, Register) 120 #define McD0PciCfg64Or(Register, OrData) QNCMmPci32Or (0, MC_BUS, 0, 0, Register, OrData) 121 #define McD0PciCfg64And(Register, AndData) QNCMmPci32And (0, MC_BUS, 0, 0, Register, AndData) 122 #define McD0PciCfg64AndThenOr(Register, AndData, OrData) QNCMmPci32AndThenOr (0, MC_BUS, 0, 0, Register, AndData, OrData) 123 124 #define McD0PciCfg32(Register) QNCMmPci32 (0, MC_BUS, 0, 0, Register) 125 #define McD0PciCfg32Or(Register, OrData) QNCMmPci32Or (0, MC_BUS, 0, 0, Register, OrData) 126 #define McD0PciCfg32And(Register, AndData) QNCMmPci32And (0, MC_BUS, 0, 0, Register, AndData) 127 #define McD0PciCfg32AndThenOr(Register, AndData, OrData) QNCMmPci32AndThenOr (0, MC_BUS, 0, 0, Register, AndData, OrData) 128 129 #define McD0PciCfg16(Register) QNCMmPci16 (0, MC_BUS, 0, 0, Register) 130 #define McD0PciCfg16Or(Register, OrData) QNCMmPci16Or (0, MC_BUS, 0, 0, Register, OrData) 131 #define McD0PciCfg16And(Register, AndData) QNCMmPci16And (0, MC_BUS, 0, 0, Register, AndData) 132 #define McD0PciCfg16AndThenOr(Register, AndData, OrData) QNCMmPci16AndThenOr (0, MC_BUS, 0, 0, Register, AndData, OrData) 133 134 #define McD0PciCfg8(Register) QNCMmPci8 (0, MC_BUS, 0, 0, Register) 135 #define McD0PciCfg8Or(Register, OrData) QNCMmPci8Or (0, MC_BUS, 0, 0, Register, OrData) 136 #define McD0PciCfg8And(Register, AndData) QNCMmPci8And (0, MC_BUS, 0, 0, Register, AndData) 137 #define McD0PciCfg8AndThenOr( Register, AndData, OrData ) QNCMmPci8AndThenOr (0, MC_BUS, 0, 0, Register, AndData, OrData) 138 139 140 // 141 // Memory Controller Hub Memory Mapped IO register access ??? 142 // 143 #define MCH_REGION_BASE (McD0PciCfg64 (MC_MCHBAR_OFFSET) & ~BIT0) 144 #define McMmioAddress(Register) ((UINTN) MCH_REGION_BASE + (UINTN) (Register)) 145 146 #define McMmio32Ptr(Register) ((volatile UINT32*) McMmioAddress (Register)) 147 #define McMmio64Ptr(Register) ((volatile UINT64*) McMmioAddress (Register)) 148 149 #define McMmio64(Register) *McMmio64Ptr( Register ) 150 #define McMmio64Or(Register, OrData) (McMmio64 (Register) |= (UINT64)(OrData)) 151 #define McMmio64And(Register, AndData) (McMmio64 (Register) &= (UINT64)(AndData)) 152 #define McMmio64AndThenOr(Register, AndData, OrData) (McMmio64 ( Register ) = (McMmio64( Register ) & (UINT64)(AndData)) | (UINT64)(OrData)) 153 154 #define McMmio32(Register) *McMmio32Ptr (Register) 155 #define McMmio32Or(Register, OrData) (McMmio32 (Register) |= (UINT32)(OrData)) 156 #define McMmio32And(Register, AndData) (McMmio32 (Register) &= (UINT32)(AndData)) 157 #define McMmio32AndThenOr(Register, AndData, OrData) (McMmio32 (Register) = (McMmio32 (Register) & (UINT32) (AndData)) | (UINT32) (OrData)) 158 159 #define McMmio16Ptr(Register) ((volatile UINT16*) McMmioAddress (Register)) 160 #define McMmio16(Register) *McMmio16Ptr (Register) 161 #define McMmio16Or(Register, OrData) (McMmio16 (Register) |= (UINT16) (OrData)) 162 #define McMmio16And(Register, AndData) (McMmio16 (Register) &= (UINT16) (AndData)) 163 #define McMmio16AndThenOr(Register, AndData, OrData) (McMmio16 (Register) = (McMmio16 (Register) & (UINT16) (AndData)) | (UINT16) (OrData)) 164 165 #define McMmio8Ptr(Register) ((volatile UINT8 *)McMmioAddress (Register)) 166 #define McMmio8(Register) *McMmio8Ptr (Register) 167 #define McMmio8Or(Register, OrData) (McMmio8 (Register) |= (UINT8) (OrData)) 168 #define McMmio8And(Register, AndData) (McMmio8 (Register) &= (UINT8) (AndData)) 169 #define McMmio8AndThenOr(Register, AndData, OrData) (McMmio8 (Register) = (McMmio8 (Register) & (UINT8) (AndData)) | (UINT8) (OrData)) 170 171 // 172 // QNC memory mapped related data structure deifinition 173 // 174 typedef enum { 175 QNCMmioWidthUint8 = 0, 176 QNCMmioWidthUint16 = 1, 177 QNCMmioWidthUint32 = 2, 178 QNCMmioWidthUint64 = 3, 179 QNCMmioWidthMaximum 180 } QNC_MEM_IO_WIDTH; 181 182 #endif 183 184
