1 /* Capstone Disassembler Engine */ 2 /* By Nguyen Anh Quynh <aquynh (at) gmail.com>, 2013> */ 3 4 #include <stdio.h> 5 #include <stdlib.h> 6 7 #include <platform.h> 8 #include <capstone.h> 9 10 static csh handle; 11 12 struct platform { 13 cs_arch arch; 14 cs_mode mode; 15 unsigned char *code; 16 size_t size; 17 char *comment; 18 int syntax; 19 }; 20 21 static void print_string_hex(char *comment, unsigned char *str, size_t len) 22 { 23 unsigned char *c; 24 25 printf("%s", comment); 26 for (c = str; c < str + len; c++) { 27 printf("0x%02x ", *c & 0xff); 28 } 29 30 printf("\n"); 31 } 32 33 static void print_insn_detail(cs_insn *ins) 34 { 35 cs_arm *arm; 36 int i; 37 38 // detail can be NULL on "data" instruction if SKIPDATA option is turned ON 39 if (ins->detail == NULL) 40 return; 41 42 arm = &(ins->detail->arm); 43 44 if (arm->op_count) 45 printf("\top_count: %u\n", arm->op_count); 46 47 for (i = 0; i < arm->op_count; i++) { 48 cs_arm_op *op = &(arm->operands[i]); 49 switch((int)op->type) { 50 default: 51 break; 52 case ARM_OP_REG: 53 printf("\t\toperands[%u].type: REG = %s\n", i, cs_reg_name(handle, op->reg)); 54 break; 55 case ARM_OP_IMM: 56 printf("\t\toperands[%u].type: IMM = 0x%x\n", i, op->imm); 57 break; 58 case ARM_OP_FP: 59 #if defined(_KERNEL_MODE) 60 // Issue #681: Windows kernel does not support formatting float point 61 printf("\t\toperands[%u].type: FP = <float_point_unsupported>\n", i); 62 #else 63 printf("\t\toperands[%u].type: FP = %f\n", i, op->fp); 64 #endif 65 break; 66 case ARM_OP_MEM: 67 printf("\t\toperands[%u].type: MEM\n", i); 68 if (op->mem.base != ARM_REG_INVALID) 69 printf("\t\t\toperands[%u].mem.base: REG = %s\n", 70 i, cs_reg_name(handle, op->mem.base)); 71 if (op->mem.index != ARM_REG_INVALID) 72 printf("\t\t\toperands[%u].mem.index: REG = %s\n", 73 i, cs_reg_name(handle, op->mem.index)); 74 if (op->mem.scale != 1) 75 printf("\t\t\toperands[%u].mem.scale: %u\n", i, op->mem.scale); 76 if (op->mem.disp != 0) 77 printf("\t\t\toperands[%u].mem.disp: 0x%x\n", i, op->mem.disp); 78 79 break; 80 case ARM_OP_PIMM: 81 printf("\t\toperands[%u].type: P-IMM = %u\n", i, op->imm); 82 break; 83 case ARM_OP_CIMM: 84 printf("\t\toperands[%u].type: C-IMM = %u\n", i, op->imm); 85 break; 86 case ARM_OP_SETEND: 87 printf("\t\toperands[%u].type: SETEND = %s\n", i, op->setend == ARM_SETEND_BE? "be" : "le"); 88 break; 89 case ARM_OP_SYSREG: 90 printf("\t\toperands[%u].type: SYSREG = %u\n", i, op->reg); 91 break; 92 } 93 94 if (op->shift.type != ARM_SFT_INVALID && op->shift.value) { 95 if (op->shift.type < ARM_SFT_ASR_REG) 96 // shift with constant value 97 printf("\t\t\tShift: %u = %u\n", op->shift.type, op->shift.value); 98 else 99 // shift with register 100 printf("\t\t\tShift: %u = %s\n", op->shift.type, 101 cs_reg_name(handle, op->shift.value)); 102 } 103 104 if (op->vector_index != -1) { 105 printf("\t\toperands[%u].vector_index = %u\n", i, op->vector_index); 106 } 107 108 if (op->subtracted) 109 printf("\t\tSubtracted: True\n"); 110 } 111 112 if (arm->cc != ARM_CC_AL && arm->cc != ARM_CC_INVALID) 113 printf("\tCode condition: %u\n", arm->cc); 114 115 if (arm->update_flags) 116 printf("\tUpdate-flags: True\n"); 117 118 if (arm->writeback) 119 printf("\tWrite-back: True\n"); 120 121 if (arm->cps_mode) 122 printf("\tCPSI-mode: %u\n", arm->cps_mode); 123 124 if (arm->cps_flag) 125 printf("\tCPSI-flag: %u\n", arm->cps_flag); 126 127 if (arm->vector_data) 128 printf("\tVector-data: %u\n", arm->vector_data); 129 130 if (arm->vector_size) 131 printf("\tVector-size: %u\n", arm->vector_size); 132 133 if (arm->usermode) 134 printf("\tUser-mode: True\n"); 135 136 if (arm->mem_barrier) 137 printf("\tMemory-barrier: %u\n", arm->mem_barrier); 138 139 printf("\n"); 140 } 141 142 static void test() 143 { 144 //#define ARM_CODE "\x04\xe0\x2d\xe5" // str lr, [sp, #-0x4]! 145 //#define ARM_CODE "\xe0\x83\x22\xe5" // str r8, [r2, #-0x3e0]! 146 //#define ARM_CODE "\xf1\x02\x03\x0e" // mcreq p0x2, #0x0, r0, c0x3, c0x1, #0x7 147 //#define ARM_CODE "\x00\x00\xa0\xe3" // mov r0, #0x0 148 //#define ARM_CODE "\x02\x30\xc1\xe7" // strb r3, [r1, r2] 149 //#define ARM_CODE "\x00\x00\x53\xe3" // cmp r3, #0x0 150 //#define ARM_CODE "\x02\x00\xa1\xe2" // adc r0, r1, r2 151 //#define ARM_CODE "\x21\x01\xa0\xe0" // adc r0, r0, r1, lsr #2 152 //#define ARM_CODE "\x21\x01\xb0\xe0" // adcs r0, r0, r1, lsr #2 153 //#define ARM_CODE "\x32\x03\xa1\xe0" // adc r0, r1, r2, lsr r3 154 //#define ARM_CODE "\x22\x01\xa1\xe0" // adc r0, r1, r2, lsr #2 155 //#define ARM_CODE "\x65\x61\x4f\x50" // subpl r6, pc, r5, ror #2 156 //#define ARM_CODE "\x30\x30\x53\xe5" // ldrb r3, [r3, #-0x30] 157 //#define ARM_CODE "\xb6\x10\xdf\xe1" // ldrh r1, [pc, #0x6] 158 //#define ARM_CODE "\x02\x00\x9f\xef" // svc #0x9f0002 159 //#define ARM_CODE "\x00\xc0\x27\xea" // b 0x9F0002: FIXME: disasm as "b #0x9f0000" 160 //#define ARM_CODE "\x12\x13\xa0\xe1" // lsl r1, r2, r3 161 //#define ARM_CODE "\x82\x11\xa0\xe1" // lsl r1, r2, #0x3 162 //#define ARM_CODE "\x00\xc0\xa0\xe1" // mov ip, r0 163 //#define ARM_CODE "\x02\x00\x12\xe3" // tst r2, #2 164 //#define ARM_CODE "\x51\x12\xa0\xe1" // asr r1, r2 165 //#define ARM_CODE "\x72\x10\xef\xe6" // uxtb r1, r2 166 //#define ARM_CODE "\xe0\x0a\xb7\xee" // vcvt.f64.f32 d0, s1 167 //#define ARM_CODE "\x9f\x0f\x91\xe1" // ldrex r0, [r1] 168 //#define ARM_CODE "\x0f\x06\x20\xf4" // vld1.8 {d0, d1, d2}, [r0] 169 //#define ARM_CODE "\x72\x00\xa1\xe6" // sxtab r0, r1, r2 170 //#define ARM_CODE "\x50\x06\x84\xf2" // vmov.i32 q0, #0x40000000 171 //#define ARM_CODE "\x73\xe0\xb8\xee" // mrc p0, #5, lr, c8, c3, #3 172 //#define ARM_CODE "\x12\x02\x81\xe6" // pkhbt r0, r1, r2, lsl #0x4 173 //#define ARM_CODE "\x12\x00\xa0\xe6" // ssat r0, #0x1, r2 174 //#define ARM_CODE "\x03\x60\x2d\xe9" // push {r0, r1, sp, lr} 175 //#define ARM_CODE "\x8f\x40\x60\xf4" // vld4.32 {d20, d21, d22, d23}, [r0] 176 //#define ARM_CODE "\xd0\x00\xc2\xe1" // ldrd r0, r1, [r2] 177 //#define ARM_CODE "\x08\xf0\xd0\xf5" // pld [r0, #0x8] 178 //#define ARM_CODE "\x10\x8b\xbc\xec" // ldc p11, c8, [r12], #64 179 //#define ARM_CODE "\xd4\x30\xd2\xe1" // ldrsb r3, [r2, #0x4] 180 //#define ARM_CODE "\x11\x0f\xbe\xf2" // vcvt.s32.f32 d0, d1, #2 181 //#define ARM_CODE "\x01\x01\x70\xe1" // cmn r0, r1, lsl #2 182 //#define ARM_CODE "\x06\x00\x91\xe2" // adds r0, r1, #6 183 //#define ARM_CODE "\x5b\xf0\x7f\xf5" // dmb ish 184 //#define ARM_CODE "\xf7\xff\xff\xfe" 185 //#define ARM_CODE "\x00\x20\xbd\xe8" // ldm sp!, {sp} 186 //#define ARM_CODE "\x00\xa0\xbd\xe8" // pop {sp, pc} 187 //#define ARM_CODE "\x90\x04\x0E\x00" // muleq lr, r0, r4 188 //#define ARM_CODE "\x90\x24\x0E\x00" // muleq lr, r0, r4 189 //#define ARM_CODE "\xb6\x10\x5f\xe1" // ldrh r1, [pc, #-6] 190 #define ARM_CODE "\xED\xFF\xFF\xEB\x04\xe0\x2d\xe5\x00\x00\x00\x00\xe0\x83\x22\xe5\xf1\x02\x03\x0e\x00\x00\xa0\xe3\x02\x30\xc1\xe7\x00\x00\x53\xe3\x00\x02\x01\xf1\x05\x40\xd0\xe8\xf4\x80\x00\x00" 191 //#define ARM_CODE2 "\xf0\x24" 192 //#define ARM_CODE2 "\x83\xb0" 193 #define ARM_CODE2 "\xd1\xe8\x00\xf0\xf0\x24\x04\x07\x1f\x3c\xf2\xc0\x00\x00\x4f\xf0\x00\x01\x46\x6c" 194 //#define THUMB_CODE "\x70\x47" // bl 0x26 195 //#define THUMB_CODE "\x07\xdd" // ble 0x1c 196 //#define THUMB_CODE "\x00\x47" // bx r0 197 //#define THUMB_CODE "\x01\x47" // bx r0 198 //#define THUMB_CODE "\x02\x47" // bx r0 199 //#define THUMB_CODE "\x0a\xbf" // itet eq 200 #define THUMB_CODE "\x70\x47\x00\xf0\x10\xe8\xeb\x46\x83\xb0\xc9\x68\x1f\xb1\x30\xbf\xaf\xf3\x20\x84" 201 #define THUMB_CODE2 "\x4f\xf0\x00\x01\xbd\xe8\x00\x88\xd1\xe8\x00\xf0\x18\xbf\xad\xbf\xf3\xff\x0b\x0c\x86\xf3\x00\x89\x80\xf3\x00\x8c\x4f\xfa\x99\xf6\xd0\xff\xa2\x01" 202 #define THUMB_MCLASS "\xef\xf3\x02\x80" 203 #define ARMV8 "\xe0\x3b\xb2\xee\x42\x00\x01\xe1\x51\xf0\x7f\xf5" 204 205 struct platform platforms[] = { 206 { 207 CS_ARCH_ARM, 208 CS_MODE_ARM, 209 (unsigned char *)ARM_CODE, 210 sizeof(ARM_CODE) - 1, 211 "ARM" 212 }, 213 { 214 CS_ARCH_ARM, 215 CS_MODE_THUMB, 216 (unsigned char *)THUMB_CODE, 217 sizeof(THUMB_CODE) - 1, 218 "Thumb" 219 }, 220 { 221 CS_ARCH_ARM, 222 CS_MODE_THUMB, 223 (unsigned char *)ARM_CODE2, 224 sizeof(ARM_CODE2) - 1, 225 "Thumb-mixed" 226 }, 227 { 228 CS_ARCH_ARM, 229 CS_MODE_THUMB, 230 (unsigned char *)THUMB_CODE2, 231 sizeof(THUMB_CODE2) - 1, 232 "Thumb-2 & register named with numbers", 233 CS_OPT_SYNTAX_NOREGNAME 234 }, 235 { 236 CS_ARCH_ARM, 237 (cs_mode)(CS_MODE_THUMB + CS_MODE_MCLASS), 238 (unsigned char*)THUMB_MCLASS, 239 sizeof(THUMB_MCLASS) - 1, 240 "Thumb-MClass" 241 }, 242 { 243 CS_ARCH_ARM, 244 (cs_mode)(CS_MODE_ARM + CS_MODE_V8), 245 (unsigned char*)ARMV8, 246 sizeof(ARMV8) - 1, 247 "Arm-V8" 248 }, 249 }; 250 251 uint64_t address = 0x80001000; 252 cs_insn *insn; 253 int i; 254 size_t count; 255 256 for (i = 0; i < sizeof(platforms)/sizeof(platforms[0]); i++) { 257 cs_err err = cs_open(platforms[i].arch, platforms[i].mode, &handle); 258 if (err) { 259 printf("Failed on cs_open() with error returned: %u\n", err); 260 continue; 261 } 262 263 cs_option(handle, CS_OPT_DETAIL, CS_OPT_ON); 264 265 if (platforms[i].syntax) 266 cs_option(handle, CS_OPT_SYNTAX, platforms[i].syntax); 267 268 count = cs_disasm(handle, platforms[i].code, platforms[i].size, address, 0, &insn); 269 if (count) { 270 size_t j; 271 printf("****************\n"); 272 printf("Platform: %s\n", platforms[i].comment); 273 print_string_hex("Code:", platforms[i].code, platforms[i].size); 274 printf("Disasm:\n"); 275 276 for (j = 0; j < count; j++) { 277 printf("0x%" PRIx64 ":\t%s\t%s\n", insn[j].address, insn[j].mnemonic, insn[j].op_str); 278 print_insn_detail(&insn[j]); 279 } 280 printf("0x%" PRIx64 ":\n", insn[j-1].address + insn[j-1].size); 281 282 // free memory allocated by cs_disasm() 283 cs_free(insn, count); 284 } else { 285 printf("****************\n"); 286 printf("Platform: %s\n", platforms[i].comment); 287 print_string_hex("Code:", platforms[i].code, platforms[i].size); 288 printf("ERROR: Failed to disasm given code!\n"); 289 } 290 291 printf("\n"); 292 293 cs_close(&handle); 294 } 295 } 296 297 int main() 298 { 299 test(); 300 301 return 0; 302 } 303 304
