1 @/****************************************************************************** 2 @ * 3 @ * Copyright (C) 2018 The Android Open Source Project 4 @ * 5 @ * Licensed under the Apache License, Version 2.0 (the "License"); 6 @ * you may not use this file except in compliance with the License. 7 @ * You may obtain a copy of the License at: 8 @ * 9 @ * http://www.apache.org/licenses/LICENSE-2.0 10 @ * 11 @ * Unless required by applicable law or agreed to in writing, software 12 @ * distributed under the License is distributed on an "AS IS" BASIS, 13 @ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 @ * See the License for the specific language governing permissions and 15 @ * limitations under the License. 16 @ * 17 @ ***************************************************************************** 18 @ * Originally developed and contributed by Ittiam Systems Pvt. Ltd, Bangalore 19 @*/ 20 21 22 .text 23 .p2align 2 24 .extern ixheaacd_esbr_cos_sin_mod 25 .hidden ixheaacd_esbr_cos_sin_mod 26 .global ixheaacd_esbr_fwd_modulation 27 ixheaacd_esbr_fwd_modulation: 28 29 STMFD sp!, {r4-r12, lr} 30 VPUSH {D8 - D15} 31 LDR R4, [R3] 32 ADD R5, R0, R4, LSL #3 33 MOV R6, R1 34 MOV R7, R2 35 36 LOOP1: 37 SUB R5, R5, #32 38 VLD1.32 {D0, D1, D2, D3}, [R0]! 39 VLD1.32 {D4, D5, D6, D7}, [R5] 40 VSHR.S32 Q0, Q0, #4 41 VSHR.S32 Q1, Q1, #4 42 VSHR.S32 Q2, Q2, #4 43 VSHR.S32 Q3, Q3, #4 44 45 vswp d4, d7 46 vswp d5, d6 47 48 vrev64.32 q2, q2 49 vrev64.32 q3, q3 50 51 VQSUB.S32 Q4, Q0, Q2 52 VQSUB.S32 Q5, Q1, Q3 53 54 VADD.S32 Q6, Q0, Q2 55 VADD.S32 Q7, Q1, Q3 56 57 SUBS R4, R4, #8 58 VST1.32 {D8, D9, D10, D11}, [R6]! 59 VST1.32 {D12, D13, D14, D15}, [R7]! 60 61 BGT LOOP1 62 STMFD sp!, {r0-r3, lr} 63 LDR R4, [SP, #124] 64 MOV R0, R1 65 MOV R1, R3 66 ldr R5, =0x41FC 67 ADD R2, R4, R5 68 ADD R3, R4, #0xB8 69 70 BL ixheaacd_esbr_cos_sin_mod 71 72 LDMFD sp!, {r0-r3, r14} 73 74 LDR R0, [R3, #0x5C] 75 LDRSH R4, [R3, #0x2C] 76 LDRSH R5, [R3, #0x2A] 77 78 SUB R4, R4, R5 79 80 LOOP2: 81 VLD2.32 {D0, D1}, [R0]! 82 VLD1.32 {D2}, [R1] 83 VLD1.32 {D3}, [R2] 84 85 VMULL.S32 q2, d0, d2 86 VMULL.S32 q3, d0, d3 87 VMULL.S32 q4, d1, d2 88 VMULL.S32 q5, d1, d3 89 90 VADD.I64 Q0, Q2, Q5 91 VQSUB.S64 Q1, Q3, Q4 92 93 VSHRN.I64 D0, Q0, #31 94 VSHRN.I64 D2, Q1, #31 95 96 SUBS R4, R4, #2 97 VST1.32 {D0}, [R1]! 98 VST1.32 {D2}, [R2]! 99 100 BGT LOOP2 101 102 VPOP {D8-D15} 103 LDMFD sp!, {r4-r12, r15} 104 105 106 107 108 109 110 111 112
