1 //===---- AMDCallingConv.td - Calling Conventions for Radeon GPUs ---------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This describes the calling conventions for the AMD Radeon GPUs. 11 // 12 //===----------------------------------------------------------------------===// 13 14 // Inversion of CCIfInReg 15 class CCIfNotInReg<CCAction A> : CCIf<"!ArgFlags.isInReg()", A> {} 16 17 // Calling convention for SI 18 def CC_SI : CallingConv<[ 19 20 CCIfInReg<CCIfType<[f32, i32] , CCAssignToReg<[ 21 SGPR0, SGPR1, SGPR2, SGPR3, SGPR4, SGPR5, SGPR6, SGPR7, 22 SGPR8, SGPR9, SGPR10, SGPR11, SGPR12, SGPR13, SGPR14, SGPR15, 23 SGPR16, SGPR17, SGPR18, SGPR19, SGPR20, SGPR21, SGPR22, SGPR23, 24 SGPR24, SGPR25, SGPR26, SGPR27, SGPR28, SGPR29, SGPR30, SGPR31, 25 SGPR32, SGPR33, SGPR34, SGPR35, SGPR36, SGPR37, SGPR38, SGPR39 26 ]>>>, 27 28 CCIfInReg<CCIfType<[i64] , CCAssignToRegWithShadow< 29 [ SGPR0, SGPR2, SGPR4, SGPR6, SGPR8, SGPR10, SGPR12, SGPR14, 30 SGPR16, SGPR18, SGPR20, SGPR22, SGPR24, SGPR26, SGPR28, SGPR30, 31 SGPR32, SGPR34, SGPR36, SGPR38 ], 32 [ SGPR1, SGPR3, SGPR5, SGPR7, SGPR9, SGPR11, SGPR13, SGPR15, 33 SGPR17, SGPR19, SGPR21, SGPR23, SGPR25, SGPR27, SGPR29, SGPR31, 34 SGPR33, SGPR35, SGPR37, SGPR39 ] 35 >>>, 36 37 // 32*4 + 4 is the minimum for a fetch shader consumer with 32 inputs. 38 CCIfNotInReg<CCIfType<[f32, i32] , CCAssignToReg<[ 39 VGPR0, VGPR1, VGPR2, VGPR3, VGPR4, VGPR5, VGPR6, VGPR7, 40 VGPR8, VGPR9, VGPR10, VGPR11, VGPR12, VGPR13, VGPR14, VGPR15, 41 VGPR16, VGPR17, VGPR18, VGPR19, VGPR20, VGPR21, VGPR22, VGPR23, 42 VGPR24, VGPR25, VGPR26, VGPR27, VGPR28, VGPR29, VGPR30, VGPR31, 43 VGPR32, VGPR33, VGPR34, VGPR35, VGPR36, VGPR37, VGPR38, VGPR39, 44 VGPR40, VGPR41, VGPR42, VGPR43, VGPR44, VGPR45, VGPR46, VGPR47, 45 VGPR48, VGPR49, VGPR50, VGPR51, VGPR52, VGPR53, VGPR54, VGPR55, 46 VGPR56, VGPR57, VGPR58, VGPR59, VGPR60, VGPR61, VGPR62, VGPR63, 47 VGPR64, VGPR65, VGPR66, VGPR67, VGPR68, VGPR69, VGPR70, VGPR71, 48 VGPR72, VGPR73, VGPR74, VGPR75, VGPR76, VGPR77, VGPR78, VGPR79, 49 VGPR80, VGPR81, VGPR82, VGPR83, VGPR84, VGPR85, VGPR86, VGPR87, 50 VGPR88, VGPR89, VGPR90, VGPR91, VGPR92, VGPR93, VGPR94, VGPR95, 51 VGPR96, VGPR97, VGPR98, VGPR99, VGPR100, VGPR101, VGPR102, VGPR103, 52 VGPR104, VGPR105, VGPR106, VGPR107, VGPR108, VGPR109, VGPR110, VGPR111, 53 VGPR112, VGPR113, VGPR114, VGPR115, VGPR116, VGPR117, VGPR118, VGPR119, 54 VGPR120, VGPR121, VGPR122, VGPR123, VGPR124, VGPR125, VGPR126, VGPR127, 55 VGPR128, VGPR129, VGPR130, VGPR131, VGPR132, VGPR133, VGPR134, VGPR135 56 ]>>>, 57 58 CCIfByVal<CCIfType<[i64] , CCAssignToRegWithShadow< 59 [ SGPR0, SGPR2, SGPR4, SGPR6, SGPR8, SGPR10, SGPR12, SGPR14, 60 SGPR16, SGPR18, SGPR20, SGPR22, SGPR24, SGPR26, SGPR28, SGPR30, 61 SGPR32, SGPR34, SGPR36, SGPR38 ], 62 [ SGPR1, SGPR3, SGPR5, SGPR7, SGPR9, SGPR11, SGPR13, SGPR15, 63 SGPR17, SGPR19, SGPR21, SGPR23, SGPR25, SGPR27, SGPR29, SGPR31, 64 SGPR33, SGPR35, SGPR37, SGPR39 ] 65 >>> 66 67 ]>; 68 69 def RetCC_SI : CallingConv<[ 70 CCIfType<[i32] , CCAssignToReg<[ 71 SGPR0, SGPR1, SGPR2, SGPR3, SGPR4, SGPR5, SGPR6, SGPR7, 72 SGPR8, SGPR9, SGPR10, SGPR11, SGPR12, SGPR13, SGPR14, SGPR15, 73 SGPR16, SGPR17, SGPR18, SGPR19, SGPR20, SGPR21, SGPR22, SGPR23, 74 SGPR24, SGPR25, SGPR26, SGPR27, SGPR28, SGPR29, SGPR30, SGPR31, 75 SGPR32, SGPR33, SGPR34, SGPR35, SGPR36, SGPR37, SGPR38, SGPR39 76 ]>>, 77 78 // 32*4 + 4 is the minimum for a fetch shader with 32 outputs. 79 CCIfType<[f32] , CCAssignToReg<[ 80 VGPR0, VGPR1, VGPR2, VGPR3, VGPR4, VGPR5, VGPR6, VGPR7, 81 VGPR8, VGPR9, VGPR10, VGPR11, VGPR12, VGPR13, VGPR14, VGPR15, 82 VGPR16, VGPR17, VGPR18, VGPR19, VGPR20, VGPR21, VGPR22, VGPR23, 83 VGPR24, VGPR25, VGPR26, VGPR27, VGPR28, VGPR29, VGPR30, VGPR31, 84 VGPR32, VGPR33, VGPR34, VGPR35, VGPR36, VGPR37, VGPR38, VGPR39, 85 VGPR40, VGPR41, VGPR42, VGPR43, VGPR44, VGPR45, VGPR46, VGPR47, 86 VGPR48, VGPR49, VGPR50, VGPR51, VGPR52, VGPR53, VGPR54, VGPR55, 87 VGPR56, VGPR57, VGPR58, VGPR59, VGPR60, VGPR61, VGPR62, VGPR63, 88 VGPR64, VGPR65, VGPR66, VGPR67, VGPR68, VGPR69, VGPR70, VGPR71, 89 VGPR72, VGPR73, VGPR74, VGPR75, VGPR76, VGPR77, VGPR78, VGPR79, 90 VGPR80, VGPR81, VGPR82, VGPR83, VGPR84, VGPR85, VGPR86, VGPR87, 91 VGPR88, VGPR89, VGPR90, VGPR91, VGPR92, VGPR93, VGPR94, VGPR95, 92 VGPR96, VGPR97, VGPR98, VGPR99, VGPR100, VGPR101, VGPR102, VGPR103, 93 VGPR104, VGPR105, VGPR106, VGPR107, VGPR108, VGPR109, VGPR110, VGPR111, 94 VGPR112, VGPR113, VGPR114, VGPR115, VGPR116, VGPR117, VGPR118, VGPR119, 95 VGPR120, VGPR121, VGPR122, VGPR123, VGPR124, VGPR125, VGPR126, VGPR127, 96 VGPR128, VGPR129, VGPR130, VGPR131, VGPR132, VGPR133, VGPR134, VGPR135 97 ]>> 98 ]>; 99 100 // Calling convention for R600 101 def CC_R600 : CallingConv<[ 102 CCIfInReg<CCIfType<[v4f32, v4i32] , CCAssignToReg<[ 103 T0_XYZW, T1_XYZW, T2_XYZW, T3_XYZW, T4_XYZW, T5_XYZW, T6_XYZW, T7_XYZW, 104 T8_XYZW, T9_XYZW, T10_XYZW, T11_XYZW, T12_XYZW, T13_XYZW, T14_XYZW, T15_XYZW, 105 T16_XYZW, T17_XYZW, T18_XYZW, T19_XYZW, T20_XYZW, T21_XYZW, T22_XYZW, 106 T23_XYZW, T24_XYZW, T25_XYZW, T26_XYZW, T27_XYZW, T28_XYZW, T29_XYZW, 107 T30_XYZW, T31_XYZW, T32_XYZW 108 ]>>> 109 ]>; 110 111 // Calling convention for compute kernels 112 def CC_AMDGPU_Kernel : CallingConv<[ 113 CCCustom<"allocateKernArg"> 114 ]>; 115 116 def CC_AMDGPU : CallingConv<[ 117 CCIf<"static_cast<const AMDGPUSubtarget&>" 118 "(State.getMachineFunction().getSubtarget()).getGeneration() >=" 119 "AMDGPUSubtarget::SOUTHERN_ISLANDS && " 120 "!AMDGPU::isShader(State.getCallingConv())", 121 CCDelegateTo<CC_AMDGPU_Kernel>>, 122 CCIf<"static_cast<const AMDGPUSubtarget&>" 123 "(State.getMachineFunction().getSubtarget()).getGeneration() < " 124 "AMDGPUSubtarget::SOUTHERN_ISLANDS && " 125 "!AMDGPU::isShader(State.getCallingConv())", 126 CCDelegateTo<CC_AMDGPU_Kernel>>, 127 CCIf<"static_cast<const AMDGPUSubtarget&>" 128 "(State.getMachineFunction().getSubtarget()).getGeneration() >= " 129 "AMDGPUSubtarget::SOUTHERN_ISLANDS", 130 CCDelegateTo<CC_SI>>, 131 CCIf<"static_cast<const AMDGPUSubtarget&>" 132 "(State.getMachineFunction().getSubtarget()).getGeneration() < " 133 "AMDGPUSubtarget::SOUTHERN_ISLANDS", 134 CCDelegateTo<CC_R600>> 135 ]>; 136
